forked from luck/tmp_suning_uos_patched
i2c-designware: split of i2c-designware.c into core and bus specific parts
This patch splits i2c-designware.c into three pieces:
i2c-designware-core.c, contains the code that interacts directly
with the core.
i2c-designware-platdrv.c, contains the code specific to the
platform driver using the core.
i2c-designware-core.h contains the definitions and declareations
shared by i2c-designware-core.c and i2c-designware-platdrv.c.
This patch is the first in a set to allow multiple instances of the
designware I2C core in the system.
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This commit is contained in:
Dirk Brandewie
Ben Dooks
parent
4a423a8c81
commit
2373f6b974
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@ -350,15 +350,15 @@ config I2C_DAVINCI
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devices such as DaVinci NIC.
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For details please see http://www.ti.com/davinci
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config I2C_DESIGNWARE
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tristate "Synopsys DesignWare"
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config I2C_DESIGNWARE_PLATFORM
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tristate "Synopsys DesignWare Platfrom"
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depends on HAVE_CLK
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help
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If you say yes to this option, support will be included for the
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Synopsys DesignWare I2C adapter. Only master mode is supported.
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This driver can also be built as a module. If so, the module
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will be called i2c-designware.
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will be called i2c-designware-platform.
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config I2C_GPIO
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tristate "GPIO-based bitbanging I2C"
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@ -33,7 +33,8 @@ obj-$(CONFIG_I2C_AU1550) += i2c-au1550.o
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obj-$(CONFIG_I2C_BLACKFIN_TWI) += i2c-bfin-twi.o
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obj-$(CONFIG_I2C_CPM) += i2c-cpm.o
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obj-$(CONFIG_I2C_DAVINCI) += i2c-davinci.o
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obj-$(CONFIG_I2C_DESIGNWARE) += i2c-designware.o
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obj-$(CONFIG_I2C_DESIGNWARE_PLATFORM) += i2c-designware-platform.o
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i2c-designware-platform-objs := i2c-designware-platdrv.o i2c-designware-core.o
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obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o
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obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o
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obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o
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@ -25,127 +25,14 @@
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* ----------------------------------------------------------------------------
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/clk.h>
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/err.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/swab.h>
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/*
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* Registers offset
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*/
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#define DW_IC_CON 0x0
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#define DW_IC_TAR 0x4
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#define DW_IC_DATA_CMD 0x10
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#define DW_IC_SS_SCL_HCNT 0x14
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#define DW_IC_SS_SCL_LCNT 0x18
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#define DW_IC_FS_SCL_HCNT 0x1c
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#define DW_IC_FS_SCL_LCNT 0x20
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#define DW_IC_INTR_STAT 0x2c
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#define DW_IC_INTR_MASK 0x30
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#define DW_IC_RAW_INTR_STAT 0x34
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#define DW_IC_RX_TL 0x38
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#define DW_IC_TX_TL 0x3c
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#define DW_IC_CLR_INTR 0x40
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#define DW_IC_CLR_RX_UNDER 0x44
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#define DW_IC_CLR_RX_OVER 0x48
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#define DW_IC_CLR_TX_OVER 0x4c
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#define DW_IC_CLR_RD_REQ 0x50
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#define DW_IC_CLR_TX_ABRT 0x54
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#define DW_IC_CLR_RX_DONE 0x58
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#define DW_IC_CLR_ACTIVITY 0x5c
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#define DW_IC_CLR_STOP_DET 0x60
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#define DW_IC_CLR_START_DET 0x64
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#define DW_IC_CLR_GEN_CALL 0x68
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#define DW_IC_ENABLE 0x6c
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#define DW_IC_STATUS 0x70
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#define DW_IC_TXFLR 0x74
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#define DW_IC_RXFLR 0x78
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#define DW_IC_COMP_PARAM_1 0xf4
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#define DW_IC_COMP_TYPE 0xfc
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#define DW_IC_TX_ABRT_SOURCE 0x80
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#define DW_IC_CON_MASTER 0x1
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#define DW_IC_CON_SPEED_STD 0x2
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#define DW_IC_CON_SPEED_FAST 0x4
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#define DW_IC_CON_10BITADDR_MASTER 0x10
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#define DW_IC_CON_RESTART_EN 0x20
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#define DW_IC_CON_SLAVE_DISABLE 0x40
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#define DW_IC_INTR_RX_UNDER 0x001
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#define DW_IC_INTR_RX_OVER 0x002
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#define DW_IC_INTR_RX_FULL 0x004
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#define DW_IC_INTR_TX_OVER 0x008
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#define DW_IC_INTR_TX_EMPTY 0x010
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#define DW_IC_INTR_RD_REQ 0x020
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#define DW_IC_INTR_TX_ABRT 0x040
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#define DW_IC_INTR_RX_DONE 0x080
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#define DW_IC_INTR_ACTIVITY 0x100
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#define DW_IC_INTR_STOP_DET 0x200
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#define DW_IC_INTR_START_DET 0x400
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#define DW_IC_INTR_GEN_CALL 0x800
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#define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
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DW_IC_INTR_TX_EMPTY | \
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DW_IC_INTR_TX_ABRT | \
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DW_IC_INTR_STOP_DET)
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#define DW_IC_STATUS_ACTIVITY 0x1
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#define DW_IC_ERR_TX_ABRT 0x1
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/*
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* status codes
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*/
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#define STATUS_IDLE 0x0
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#define STATUS_WRITE_IN_PROGRESS 0x1
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#define STATUS_READ_IN_PROGRESS 0x2
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#define TIMEOUT 20 /* ms */
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/*
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* hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
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*
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* only expected abort codes are listed here
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* refer to the datasheet for the full list
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*/
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#define ABRT_7B_ADDR_NOACK 0
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#define ABRT_10ADDR1_NOACK 1
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#define ABRT_10ADDR2_NOACK 2
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#define ABRT_TXDATA_NOACK 3
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#define ABRT_GCALL_NOACK 4
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#define ABRT_GCALL_READ 5
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#define ABRT_SBYTE_ACKDET 7
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#define ABRT_SBYTE_NORSTRT 9
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#define ABRT_10B_RD_NORSTRT 10
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#define ABRT_MASTER_DIS 11
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#define ARB_LOST 12
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#define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK)
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#define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK)
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#define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK)
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#define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK)
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#define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK)
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#define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ)
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#define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET)
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#define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT)
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#define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT)
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#define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS)
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#define DW_IC_TX_ARB_LOST (1UL << ARB_LOST)
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#define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
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DW_IC_TX_ABRT_10ADDR1_NOACK | \
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DW_IC_TX_ABRT_10ADDR2_NOACK | \
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DW_IC_TX_ABRT_TXDATA_NOACK | \
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DW_IC_TX_ABRT_GCALL_NOACK)
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#include <linux/delay.h>
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#include "i2c-designware-core.h"
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static char *abort_sources[] = {
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[ABRT_7B_ADDR_NOACK] =
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@ -172,59 +59,7 @@ static char *abort_sources[] = {
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"lost arbitration",
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};
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/**
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* struct dw_i2c_dev - private i2c-designware data
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* @dev: driver model device node
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* @base: IO registers pointer
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* @cmd_complete: tx completion indicator
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* @lock: protect this struct and IO registers
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* @clk: input reference clock
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* @cmd_err: run time hadware error code
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* @msgs: points to an array of messages currently being transferred
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* @msgs_num: the number of elements in msgs
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* @msg_write_idx: the element index of the current tx message in the msgs
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* array
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* @tx_buf_len: the length of the current tx buffer
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* @tx_buf: the current tx buffer
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* @msg_read_idx: the element index of the current rx message in the msgs
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* array
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* @rx_buf_len: the length of the current rx buffer
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* @rx_buf: the current rx buffer
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* @msg_err: error status of the current transfer
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* @status: i2c master status, one of STATUS_*
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* @abort_source: copy of the TX_ABRT_SOURCE register
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* @irq: interrupt number for the i2c master
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* @swab: true if the instantiated IP is of different endianess
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* @adapter: i2c subsystem adapter node
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* @tx_fifo_depth: depth of the hardware tx fifo
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* @rx_fifo_depth: depth of the hardware rx fifo
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*/
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struct dw_i2c_dev {
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struct device *dev;
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void __iomem *base;
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struct completion cmd_complete;
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struct mutex lock;
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struct clk *clk;
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int cmd_err;
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struct i2c_msg *msgs;
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int msgs_num;
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int msg_write_idx;
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u32 tx_buf_len;
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u8 *tx_buf;
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int msg_read_idx;
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u32 rx_buf_len;
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u8 *rx_buf;
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int msg_err;
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unsigned int status;
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u32 abort_source;
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int irq;
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int swab;
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struct i2c_adapter adapter;
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unsigned int tx_fifo_depth;
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unsigned int rx_fifo_depth;
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};
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static u32 dw_readl(struct dw_i2c_dev *dev, int offset)
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u32 dw_readl(struct dw_i2c_dev *dev, int offset)
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{
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u32 value = readl(dev->base + offset);
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@ -234,7 +69,7 @@ static u32 dw_readl(struct dw_i2c_dev *dev, int offset)
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return value;
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}
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static void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
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void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
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{
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if (dev->swab)
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b = swab32(b);
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@ -305,7 +140,7 @@ static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
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* This function is called during I2C init function, and in case of timeout at
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* run time.
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*/
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static int i2c_dw_init(struct dw_i2c_dev *dev)
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int i2c_dw_init(struct dw_i2c_dev *dev)
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{
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u32 input_clock_khz = clk_get_rate(dev->clk) / 1000;
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u32 ic_con, hcnt, lcnt;
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@ -419,7 +254,7 @@ static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
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* messages into the tx buffer. Even if the size of i2c_msg data is
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* longer than the size of the tx buffer, it handles everything.
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*/
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static void
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void
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i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
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{
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struct i2c_msg *msgs = dev->msgs;
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@ -490,7 +325,7 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
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if (dev->msg_err)
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intr_mask = 0;
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dw_writel(dev, intr_mask, DW_IC_INTR_MASK);
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dw_writel(dev, intr_mask, DW_IC_INTR_MASK);
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}
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static void
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@ -555,7 +390,7 @@ static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
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/*
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* Prepare controller for a transaction and call i2c_dw_xfer_msg
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*/
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static int
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int
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i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
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{
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struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
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@ -618,7 +453,7 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
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return ret;
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}
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static u32 i2c_dw_func(struct i2c_adapter *adap)
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u32 i2c_dw_func(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C |
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I2C_FUNC_10BIT_ADDR |
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@ -638,9 +473,9 @@ static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
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* in the IC_RAW_INTR_STAT register.
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*
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* That is,
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* stat = readl(IC_INTR_STAT);
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* stat = dw_readl(IC_INTR_STAT);
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* equals to,
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* stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK);
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* stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
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*
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* The raw version might be useful for debugging purposes.
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*/
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@ -649,7 +484,7 @@ static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
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/*
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* Do not use the IC_CLR_INTR register to clear interrupts, or
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* you'll miss some interrupts, triggered during the period from
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* readl(IC_INTR_STAT) to readl(IC_CLR_INTR).
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* dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
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*
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* Instead, use the separately-prepared IC_CLR_* registers.
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*/
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@ -687,7 +522,7 @@ static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
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* Interrupt service routine. This gets called whenever an I2C interrupt
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* occurs.
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*/
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static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
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irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
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{
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struct dw_i2c_dev *dev = dev_id;
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u32 stat;
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@ -725,163 +560,3 @@ static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
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return IRQ_HANDLED;
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}
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static struct i2c_algorithm i2c_dw_algo = {
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.master_xfer = i2c_dw_xfer,
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.functionality = i2c_dw_func,
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};
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static int __devinit dw_i2c_probe(struct platform_device *pdev)
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{
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struct dw_i2c_dev *dev;
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struct i2c_adapter *adap;
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struct resource *mem, *ioarea;
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int irq, r;
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u32 reg;
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/* NOTE: driver uses the static register mapping */
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!mem) {
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dev_err(&pdev->dev, "no mem resource?\n");
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return -EINVAL;
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}
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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dev_err(&pdev->dev, "no irq resource?\n");
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return irq; /* -ENXIO */
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}
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ioarea = request_mem_region(mem->start, resource_size(mem),
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pdev->name);
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if (!ioarea) {
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dev_err(&pdev->dev, "I2C region already claimed\n");
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return -EBUSY;
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}
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dev = kzalloc(sizeof(struct dw_i2c_dev), GFP_KERNEL);
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if (!dev) {
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r = -ENOMEM;
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goto err_release_region;
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}
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init_completion(&dev->cmd_complete);
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mutex_init(&dev->lock);
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dev->dev = get_device(&pdev->dev);
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dev->irq = irq;
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platform_set_drvdata(pdev, dev);
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dev->clk = clk_get(&pdev->dev, NULL);
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if (IS_ERR(dev->clk)) {
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r = -ENODEV;
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goto err_free_mem;
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}
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clk_enable(dev->clk);
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dev->base = ioremap(mem->start, resource_size(mem));
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if (dev->base == NULL) {
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dev_err(&pdev->dev, "failure mapping io resources\n");
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r = -EBUSY;
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goto err_unuse_clocks;
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}
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r = i2c_dw_init(dev);
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if (r)
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goto err_unuse_clocks;
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reg = dw_readl(dev, DW_IC_COMP_PARAM_1);
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dev->tx_fifo_depth = ((reg >> 16) & 0xff) + 1;
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dev->rx_fifo_depth = ((reg >> 8) & 0xff) + 1;
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dw_writel(dev, 0, DW_IC_INTR_MASK); /* disable IRQ */
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r = request_irq(dev->irq, i2c_dw_isr, IRQF_DISABLED, pdev->name, dev);
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if (r) {
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dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
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goto err_iounmap;
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}
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adap = &dev->adapter;
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i2c_set_adapdata(adap, dev);
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adap->owner = THIS_MODULE;
|
||||
adap->class = I2C_CLASS_HWMON;
|
||||
strlcpy(adap->name, "Synopsys DesignWare I2C adapter",
|
||||
sizeof(adap->name));
|
||||
adap->algo = &i2c_dw_algo;
|
||||
adap->dev.parent = &pdev->dev;
|
||||
|
||||
adap->nr = pdev->id;
|
||||
r = i2c_add_numbered_adapter(adap);
|
||||
if (r) {
|
||||
dev_err(&pdev->dev, "failure adding adapter\n");
|
||||
goto err_free_irq;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_irq:
|
||||
free_irq(dev->irq, dev);
|
||||
err_iounmap:
|
||||
iounmap(dev->base);
|
||||
err_unuse_clocks:
|
||||
clk_disable(dev->clk);
|
||||
clk_put(dev->clk);
|
||||
dev->clk = NULL;
|
||||
err_free_mem:
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
put_device(&pdev->dev);
|
||||
kfree(dev);
|
||||
err_release_region:
|
||||
release_mem_region(mem->start, resource_size(mem));
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static int __devexit dw_i2c_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct dw_i2c_dev *dev = platform_get_drvdata(pdev);
|
||||
struct resource *mem;
|
||||
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
i2c_del_adapter(&dev->adapter);
|
||||
put_device(&pdev->dev);
|
||||
|
||||
clk_disable(dev->clk);
|
||||
clk_put(dev->clk);
|
||||
dev->clk = NULL;
|
||||
|
||||
dw_writel(dev, 0, DW_IC_ENABLE);
|
||||
free_irq(dev->irq, dev);
|
||||
kfree(dev);
|
||||
|
||||
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
release_mem_region(mem->start, resource_size(mem));
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* work with hotplug and coldplug */
|
||||
MODULE_ALIAS("platform:i2c_designware");
|
||||
|
||||
static struct platform_driver dw_i2c_driver = {
|
||||
.remove = __devexit_p(dw_i2c_remove),
|
||||
.driver = {
|
||||
.name = "i2c_designware",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init dw_i2c_init_driver(void)
|
||||
{
|
||||
return platform_driver_probe(&dw_i2c_driver, dw_i2c_probe);
|
||||
}
|
||||
module_init(dw_i2c_init_driver);
|
||||
|
||||
static void __exit dw_i2c_exit_driver(void)
|
||||
{
|
||||
platform_driver_unregister(&dw_i2c_driver);
|
||||
}
|
||||
module_exit(dw_i2c_exit_driver);
|
||||
|
||||
MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
|
||||
MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter");
|
||||
MODULE_LICENSE("GPL");
|
||||
194
drivers/i2c/busses/i2c-designware-core.h
Normal file
194
drivers/i2c/busses/i2c-designware-core.h
Normal file
|
|
@ -0,0 +1,194 @@
|
|||
/*
|
||||
* Synopsys DesignWare I2C adapter driver (master only).
|
||||
*
|
||||
* Based on the TI DAVINCI I2C adapter driver.
|
||||
*
|
||||
* Copyright (C) 2006 Texas Instruments.
|
||||
* Copyright (C) 2007 MontaVista Software Inc.
|
||||
* Copyright (C) 2009 Provigent Ltd.
|
||||
*
|
||||
* ----------------------------------------------------------------------------
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
* ----------------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Registers offset
|
||||
*/
|
||||
#define DW_IC_CON 0x0
|
||||
#define DW_IC_TAR 0x4
|
||||
#define DW_IC_DATA_CMD 0x10
|
||||
#define DW_IC_SS_SCL_HCNT 0x14
|
||||
#define DW_IC_SS_SCL_LCNT 0x18
|
||||
#define DW_IC_FS_SCL_HCNT 0x1c
|
||||
#define DW_IC_FS_SCL_LCNT 0x20
|
||||
#define DW_IC_INTR_STAT 0x2c
|
||||
#define DW_IC_INTR_MASK 0x30
|
||||
#define DW_IC_RAW_INTR_STAT 0x34
|
||||
#define DW_IC_RX_TL 0x38
|
||||
#define DW_IC_TX_TL 0x3c
|
||||
#define DW_IC_CLR_INTR 0x40
|
||||
#define DW_IC_CLR_RX_UNDER 0x44
|
||||
#define DW_IC_CLR_RX_OVER 0x48
|
||||
#define DW_IC_CLR_TX_OVER 0x4c
|
||||
#define DW_IC_CLR_RD_REQ 0x50
|
||||
#define DW_IC_CLR_TX_ABRT 0x54
|
||||
#define DW_IC_CLR_RX_DONE 0x58
|
||||
#define DW_IC_CLR_ACTIVITY 0x5c
|
||||
#define DW_IC_CLR_STOP_DET 0x60
|
||||
#define DW_IC_CLR_START_DET 0x64
|
||||
#define DW_IC_CLR_GEN_CALL 0x68
|
||||
#define DW_IC_ENABLE 0x6c
|
||||
#define DW_IC_STATUS 0x70
|
||||
#define DW_IC_TXFLR 0x74
|
||||
#define DW_IC_RXFLR 0x78
|
||||
#define DW_IC_TX_ABRT_SOURCE 0x80
|
||||
#define DW_IC_COMP_PARAM_1 0xf4
|
||||
#define DW_IC_COMP_TYPE 0xfc
|
||||
#define DW_IC_COMP_TYPE_VALUE 0x44570140
|
||||
|
||||
#define DW_IC_CON_MASTER 0x1
|
||||
#define DW_IC_CON_SPEED_STD 0x2
|
||||
#define DW_IC_CON_SPEED_FAST 0x4
|
||||
#define DW_IC_CON_10BITADDR_MASTER 0x10
|
||||
#define DW_IC_CON_RESTART_EN 0x20
|
||||
#define DW_IC_CON_SLAVE_DISABLE 0x40
|
||||
|
||||
#define DW_IC_INTR_RX_UNDER 0x001
|
||||
#define DW_IC_INTR_RX_OVER 0x002
|
||||
#define DW_IC_INTR_RX_FULL 0x004
|
||||
#define DW_IC_INTR_TX_OVER 0x008
|
||||
#define DW_IC_INTR_TX_EMPTY 0x010
|
||||
#define DW_IC_INTR_RD_REQ 0x020
|
||||
#define DW_IC_INTR_TX_ABRT 0x040
|
||||
#define DW_IC_INTR_RX_DONE 0x080
|
||||
#define DW_IC_INTR_ACTIVITY 0x100
|
||||
#define DW_IC_INTR_STOP_DET 0x200
|
||||
#define DW_IC_INTR_START_DET 0x400
|
||||
#define DW_IC_INTR_GEN_CALL 0x800
|
||||
|
||||
#define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
|
||||
DW_IC_INTR_TX_EMPTY | \
|
||||
DW_IC_INTR_TX_ABRT | \
|
||||
DW_IC_INTR_STOP_DET)
|
||||
|
||||
#define DW_IC_STATUS_ACTIVITY 0x1
|
||||
|
||||
#define DW_IC_ERR_TX_ABRT 0x1
|
||||
|
||||
/*
|
||||
* status codes
|
||||
*/
|
||||
#define STATUS_IDLE 0x0
|
||||
#define STATUS_WRITE_IN_PROGRESS 0x1
|
||||
#define STATUS_READ_IN_PROGRESS 0x2
|
||||
|
||||
#define TIMEOUT 20 /* ms */
|
||||
|
||||
/*
|
||||
* hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
|
||||
*
|
||||
* only expected abort codes are listed here
|
||||
* refer to the datasheet for the full list
|
||||
*/
|
||||
#define ABRT_7B_ADDR_NOACK 0
|
||||
#define ABRT_10ADDR1_NOACK 1
|
||||
#define ABRT_10ADDR2_NOACK 2
|
||||
#define ABRT_TXDATA_NOACK 3
|
||||
#define ABRT_GCALL_NOACK 4
|
||||
#define ABRT_GCALL_READ 5
|
||||
#define ABRT_SBYTE_ACKDET 7
|
||||
#define ABRT_SBYTE_NORSTRT 9
|
||||
#define ABRT_10B_RD_NORSTRT 10
|
||||
#define ABRT_MASTER_DIS 11
|
||||
#define ARB_LOST 12
|
||||
|
||||
#define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK)
|
||||
#define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK)
|
||||
#define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK)
|
||||
#define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK)
|
||||
#define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK)
|
||||
#define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ)
|
||||
#define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET)
|
||||
#define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT)
|
||||
#define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT)
|
||||
#define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS)
|
||||
#define DW_IC_TX_ARB_LOST (1UL << ARB_LOST)
|
||||
|
||||
#define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
|
||||
DW_IC_TX_ABRT_10ADDR1_NOACK | \
|
||||
DW_IC_TX_ABRT_10ADDR2_NOACK | \
|
||||
DW_IC_TX_ABRT_TXDATA_NOACK | \
|
||||
DW_IC_TX_ABRT_GCALL_NOACK)
|
||||
/**
|
||||
* struct dw_i2c_dev - private i2c-designware data
|
||||
* @dev: driver model device node
|
||||
* @base: IO registers pointer
|
||||
* @cmd_complete: tx completion indicator
|
||||
* @lock: protect this struct and IO registers
|
||||
* @clk: input reference clock
|
||||
* @cmd_err: run time hadware error code
|
||||
* @msgs: points to an array of messages currently being transfered
|
||||
* @msgs_num: the number of elements in msgs
|
||||
* @msg_write_idx: the element index of the current tx message in the msgs
|
||||
* array
|
||||
* @tx_buf_len: the length of the current tx buffer
|
||||
* @tx_buf: the current tx buffer
|
||||
* @msg_read_idx: the element index of the current rx message in the msgs
|
||||
* array
|
||||
* @rx_buf_len: the length of the current rx buffer
|
||||
* @rx_buf: the current rx buffer
|
||||
* @msg_err: error status of the current transfer
|
||||
* @status: i2c master status, one of STATUS_*
|
||||
* @abort_source: copy of the TX_ABRT_SOURCE register
|
||||
* @irq: interrupt number for the i2c master
|
||||
* @adapter: i2c subsystem adapter node
|
||||
* @tx_fifo_depth: depth of the hardware tx fifo
|
||||
* @rx_fifo_depth: depth of the hardware rx fifo
|
||||
*/
|
||||
struct dw_i2c_dev {
|
||||
struct device *dev;
|
||||
void __iomem *base;
|
||||
struct completion cmd_complete;
|
||||
struct mutex lock;
|
||||
struct clk *clk;
|
||||
int cmd_err;
|
||||
struct i2c_msg *msgs;
|
||||
int msgs_num;
|
||||
int msg_write_idx;
|
||||
u32 tx_buf_len;
|
||||
u8 *tx_buf;
|
||||
int msg_read_idx;
|
||||
u32 rx_buf_len;
|
||||
u8 *rx_buf;
|
||||
int msg_err;
|
||||
unsigned int status;
|
||||
u32 abort_source;
|
||||
int irq;
|
||||
int swab;
|
||||
struct i2c_adapter adapter;
|
||||
unsigned int tx_fifo_depth;
|
||||
unsigned int rx_fifo_depth;
|
||||
};
|
||||
|
||||
extern u32 dw_readl(struct dw_i2c_dev *dev, int offset);
|
||||
extern void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset);
|
||||
extern int i2c_dw_init(struct dw_i2c_dev *dev);
|
||||
extern int i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
|
||||
int num);
|
||||
extern u32 i2c_dw_func(struct i2c_adapter *adap);
|
||||
extern irqreturn_t i2c_dw_isr(int this_irq, void *dev_id);
|
||||
199
drivers/i2c/busses/i2c-designware-platdrv.c
Normal file
199
drivers/i2c/busses/i2c-designware-platdrv.c
Normal file
|
|
@ -0,0 +1,199 @@
|
|||
/*
|
||||
* Synopsys DesignWare I2C adapter driver (master only).
|
||||
*
|
||||
* Based on the TI DAVINCI I2C adapter driver.
|
||||
*
|
||||
* Copyright (C) 2006 Texas Instruments.
|
||||
* Copyright (C) 2007 MontaVista Software Inc.
|
||||
* Copyright (C) 2009 Provigent Ltd.
|
||||
*
|
||||
* ----------------------------------------------------------------------------
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
* ----------------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/slab.h>
|
||||
#include "i2c-designware-core.h"
|
||||
|
||||
static struct i2c_algorithm i2c_dw_algo = {
|
||||
.master_xfer = i2c_dw_xfer,
|
||||
.functionality = i2c_dw_func,
|
||||
};
|
||||
|
||||
static int __devinit dw_i2c_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct dw_i2c_dev *dev;
|
||||
struct i2c_adapter *adap;
|
||||
struct resource *mem, *ioarea;
|
||||
int irq, r;
|
||||
|
||||
/* NOTE: driver uses the static register mapping */
|
||||
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!mem) {
|
||||
dev_err(&pdev->dev, "no mem resource?\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
dev_err(&pdev->dev, "no irq resource?\n");
|
||||
return irq; /* -ENXIO */
|
||||
}
|
||||
|
||||
ioarea = request_mem_region(mem->start, resource_size(mem),
|
||||
pdev->name);
|
||||
if (!ioarea) {
|
||||
dev_err(&pdev->dev, "I2C region already claimed\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
dev = kzalloc(sizeof(struct dw_i2c_dev), GFP_KERNEL);
|
||||
if (!dev) {
|
||||
r = -ENOMEM;
|
||||
goto err_release_region;
|
||||
}
|
||||
|
||||
init_completion(&dev->cmd_complete);
|
||||
mutex_init(&dev->lock);
|
||||
dev->dev = get_device(&pdev->dev);
|
||||
dev->irq = irq;
|
||||
platform_set_drvdata(pdev, dev);
|
||||
|
||||
dev->clk = clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(dev->clk)) {
|
||||
r = -ENODEV;
|
||||
goto err_free_mem;
|
||||
}
|
||||
clk_enable(dev->clk);
|
||||
|
||||
dev->base = ioremap(mem->start, resource_size(mem));
|
||||
if (dev->base == NULL) {
|
||||
dev_err(&pdev->dev, "failure mapping io resources\n");
|
||||
r = -EBUSY;
|
||||
goto err_unuse_clocks;
|
||||
}
|
||||
{
|
||||
u32 param1 = dw_readl(dev, DW_IC_COMP_PARAM_1);
|
||||
|
||||
dev->tx_fifo_depth = ((param1 >> 16) & 0xff) + 1;
|
||||
dev->rx_fifo_depth = ((param1 >> 8) & 0xff) + 1;
|
||||
}
|
||||
r = i2c_dw_init(dev);
|
||||
if (r)
|
||||
goto err_iounmap;
|
||||
|
||||
dw_writel(dev, 0, DW_IC_INTR_MASK); /* disable IRQ */
|
||||
r = request_irq(dev->irq, i2c_dw_isr, IRQF_DISABLED, pdev->name, dev);
|
||||
if (r) {
|
||||
dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
|
||||
goto err_iounmap;
|
||||
}
|
||||
|
||||
adap = &dev->adapter;
|
||||
i2c_set_adapdata(adap, dev);
|
||||
adap->owner = THIS_MODULE;
|
||||
adap->class = I2C_CLASS_HWMON;
|
||||
strlcpy(adap->name, "Synopsys DesignWare I2C adapter",
|
||||
sizeof(adap->name));
|
||||
adap->algo = &i2c_dw_algo;
|
||||
adap->dev.parent = &pdev->dev;
|
||||
|
||||
adap->nr = pdev->id;
|
||||
r = i2c_add_numbered_adapter(adap);
|
||||
if (r) {
|
||||
dev_err(&pdev->dev, "failure adding adapter\n");
|
||||
goto err_free_irq;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_irq:
|
||||
free_irq(dev->irq, dev);
|
||||
err_iounmap:
|
||||
iounmap(dev->base);
|
||||
err_unuse_clocks:
|
||||
clk_disable(dev->clk);
|
||||
clk_put(dev->clk);
|
||||
dev->clk = NULL;
|
||||
err_free_mem:
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
put_device(&pdev->dev);
|
||||
kfree(dev);
|
||||
err_release_region:
|
||||
release_mem_region(mem->start, resource_size(mem));
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static int __devexit dw_i2c_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct dw_i2c_dev *dev = platform_get_drvdata(pdev);
|
||||
struct resource *mem;
|
||||
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
i2c_del_adapter(&dev->adapter);
|
||||
put_device(&pdev->dev);
|
||||
|
||||
clk_disable(dev->clk);
|
||||
clk_put(dev->clk);
|
||||
dev->clk = NULL;
|
||||
|
||||
dw_writel(dev, 0, DW_IC_ENABLE);
|
||||
free_irq(dev->irq, dev);
|
||||
kfree(dev);
|
||||
|
||||
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
release_mem_region(mem->start, resource_size(mem));
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* work with hotplug and coldplug */
|
||||
MODULE_ALIAS("platform:i2c_designware");
|
||||
|
||||
static struct platform_driver dw_i2c_driver = {
|
||||
.remove = __devexit_p(dw_i2c_remove),
|
||||
.driver = {
|
||||
.name = "i2c_designware",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init dw_i2c_init_driver(void)
|
||||
{
|
||||
return platform_driver_probe(&dw_i2c_driver, dw_i2c_probe);
|
||||
}
|
||||
module_init(dw_i2c_init_driver);
|
||||
|
||||
static void __exit dw_i2c_exit_driver(void)
|
||||
{
|
||||
platform_driver_unregister(&dw_i2c_driver);
|
||||
}
|
||||
module_exit(dw_i2c_exit_driver);
|
||||
|
||||
MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
|
||||
MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue
Block a user