forked from luck/tmp_suning_uos_patched
IB/mlx5: Device memory support in mlx5_ib
This patch adds the mlx5_ib driver implementation for the device memory allocation API. It implements the ib_device callbacks for allocation and deallocation operations as well as a new mmap command support which allows mapping an allocated device memory to a VMA. The change also adds reporting of device memory maximum size and alignment parameters reported in device capabilities. The allocation/deallocation operations are using new firmware commands to allocate MEMIC memory on the device. Signed-off-by: Ariel Levkovich <lariel@mellanox.com> Signed-off-by: Leon Romanovsky <leonro@mellanox.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
This commit is contained in:
Ariel Levkovich
Jason Gunthorpe
parent
e72bd817ae
commit
24da00164f
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@ -66,3 +66,109 @@ int mlx5_cmd_modify_cong_params(struct mlx5_core_dev *dev,
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return mlx5_cmd_exec(dev, in, in_size, out, sizeof(out));
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}
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int mlx5_cmd_alloc_memic(struct mlx5_memic *memic, phys_addr_t *addr,
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u64 length, u32 alignment)
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{
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struct mlx5_core_dev *dev = memic->dev;
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u64 num_memic_hw_pages = MLX5_CAP_DEV_MEM(dev, memic_bar_size)
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>> PAGE_SHIFT;
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u64 hw_start_addr = MLX5_CAP64_DEV_MEM(dev, memic_bar_start_addr);
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u32 max_alignment = MLX5_CAP_DEV_MEM(dev, log_max_memic_addr_alignment);
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u32 num_pages = DIV_ROUND_UP(length, PAGE_SIZE);
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u32 out[MLX5_ST_SZ_DW(alloc_memic_out)] = {};
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u32 in[MLX5_ST_SZ_DW(alloc_memic_in)] = {};
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u32 mlx5_alignment;
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u64 page_idx = 0;
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int ret = 0;
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if (!length || (length & MLX5_MEMIC_ALLOC_SIZE_MASK))
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return -EINVAL;
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/* mlx5 device sets alignment as 64*2^driver_value
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* so normalizing is needed.
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*/
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mlx5_alignment = (alignment < MLX5_MEMIC_BASE_ALIGN) ? 0 :
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alignment - MLX5_MEMIC_BASE_ALIGN;
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if (mlx5_alignment > max_alignment)
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return -EINVAL;
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MLX5_SET(alloc_memic_in, in, opcode, MLX5_CMD_OP_ALLOC_MEMIC);
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MLX5_SET(alloc_memic_in, in, range_size, num_pages * PAGE_SIZE);
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MLX5_SET(alloc_memic_in, in, memic_size, length);
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MLX5_SET(alloc_memic_in, in, log_memic_addr_alignment,
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mlx5_alignment);
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do {
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spin_lock(&memic->memic_lock);
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page_idx = bitmap_find_next_zero_area(memic->memic_alloc_pages,
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num_memic_hw_pages,
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page_idx,
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num_pages, 0);
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if (page_idx + num_pages <= num_memic_hw_pages)
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bitmap_set(memic->memic_alloc_pages,
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page_idx, num_pages);
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else
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ret = -ENOMEM;
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spin_unlock(&memic->memic_lock);
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if (ret)
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return ret;
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MLX5_SET64(alloc_memic_in, in, range_start_addr,
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hw_start_addr + (page_idx * PAGE_SIZE));
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ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
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if (ret) {
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spin_lock(&memic->memic_lock);
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bitmap_clear(memic->memic_alloc_pages,
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page_idx, num_pages);
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spin_unlock(&memic->memic_lock);
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if (ret == -EAGAIN) {
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page_idx++;
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continue;
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}
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return ret;
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}
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*addr = pci_resource_start(dev->pdev, 0) +
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MLX5_GET64(alloc_memic_out, out, memic_start_addr);
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return ret;
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} while (page_idx < num_memic_hw_pages);
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return ret;
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}
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int mlx5_cmd_dealloc_memic(struct mlx5_memic *memic, u64 addr, u64 length)
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{
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struct mlx5_core_dev *dev = memic->dev;
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u64 hw_start_addr = MLX5_CAP64_DEV_MEM(dev, memic_bar_start_addr);
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u32 num_pages = DIV_ROUND_UP(length, PAGE_SIZE);
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u32 out[MLX5_ST_SZ_DW(dealloc_memic_out)] = {0};
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u32 in[MLX5_ST_SZ_DW(dealloc_memic_in)] = {0};
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u64 start_page_idx;
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int err;
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addr -= pci_resource_start(dev->pdev, 0);
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start_page_idx = (addr - hw_start_addr) >> PAGE_SHIFT;
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MLX5_SET(dealloc_memic_in, in, opcode, MLX5_CMD_OP_DEALLOC_MEMIC);
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MLX5_SET64(dealloc_memic_in, in, memic_start_addr, addr);
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MLX5_SET(dealloc_memic_in, in, memic_size, length);
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err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
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if (!err) {
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spin_lock(&memic->memic_lock);
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bitmap_clear(memic->memic_alloc_pages,
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start_page_idx, num_pages);
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spin_unlock(&memic->memic_lock);
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}
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return err;
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}
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@ -33,6 +33,7 @@
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#ifndef MLX5_IB_CMD_H
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#define MLX5_IB_CMD_H
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#include "mlx5_ib.h"
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#include <linux/kernel.h>
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#include <linux/mlx5/driver.h>
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@ -41,4 +42,7 @@ int mlx5_cmd_query_cong_params(struct mlx5_core_dev *dev, int cong_point,
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void *out, int out_size);
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int mlx5_cmd_modify_cong_params(struct mlx5_core_dev *mdev,
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void *in, int in_size);
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int mlx5_cmd_alloc_memic(struct mlx5_memic *memic, phys_addr_t *addr,
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u64 length, u32 alignment);
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int mlx5_cmd_dealloc_memic(struct mlx5_memic *memic, u64 addr, u64 length);
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#endif /* MLX5_IB_CMD_H */
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@ -38,6 +38,7 @@
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#include <linux/pci.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/bitmap.h>
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#if defined(CONFIG_X86)
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#include <asm/pat.h>
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#endif
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@ -891,6 +892,11 @@ static int mlx5_ib_query_device(struct ib_device *ibdev,
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props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
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}
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if (MLX5_CAP_DEV_MEM(mdev, memic)) {
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props->max_dm_size =
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MLX5_CAP_DEV_MEM(mdev, max_memic_size);
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}
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if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
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props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
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@ -2014,6 +2020,8 @@ static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
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return "best effort WC";
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case MLX5_IB_MMAP_NC_PAGE:
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return "NC";
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case MLX5_IB_MMAP_DEVICE_MEM:
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return "Device Memory";
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default:
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return NULL;
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}
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@ -2172,6 +2180,34 @@ static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
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return err;
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}
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static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
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{
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struct mlx5_ib_ucontext *mctx = to_mucontext(context);
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struct mlx5_ib_dev *dev = to_mdev(context->device);
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u16 page_idx = get_extended_index(vma->vm_pgoff);
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size_t map_size = vma->vm_end - vma->vm_start;
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u32 npages = map_size >> PAGE_SHIFT;
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phys_addr_t pfn;
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pgprot_t prot;
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if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
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page_idx + npages)
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return -EINVAL;
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pfn = ((pci_resource_start(dev->mdev->pdev, 0) +
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MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
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PAGE_SHIFT) +
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page_idx;
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prot = pgprot_writecombine(vma->vm_page_prot);
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vma->vm_page_prot = prot;
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if (io_remap_pfn_range(vma, vma->vm_start, pfn, map_size,
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vma->vm_page_prot))
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return -EAGAIN;
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return mlx5_ib_set_vma_data(vma, mctx);
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}
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static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
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{
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struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
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@ -2216,6 +2252,9 @@ static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vm
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case MLX5_IB_MMAP_CLOCK_INFO:
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return mlx5_ib_mmap_clock_info_page(dev, vma, context);
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case MLX5_IB_MMAP_DEVICE_MEM:
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return dm_mmap(ibcontext, vma);
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default:
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return -EINVAL;
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}
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@ -2223,6 +2262,87 @@ static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vm
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return 0;
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}
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struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
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struct ib_ucontext *context,
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struct ib_dm_alloc_attr *attr,
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struct uverbs_attr_bundle *attrs)
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{
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u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
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struct mlx5_memic *memic = &to_mdev(ibdev)->memic;
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phys_addr_t memic_addr;
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struct mlx5_ib_dm *dm;
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u64 start_offset;
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u32 page_idx;
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int err;
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dm = kzalloc(sizeof(*dm), GFP_KERNEL);
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if (!dm)
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return ERR_PTR(-ENOMEM);
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mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n",
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attr->length, act_size, attr->alignment);
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err = mlx5_cmd_alloc_memic(memic, &memic_addr,
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act_size, attr->alignment);
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if (err)
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goto err_free;
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start_offset = memic_addr & ~PAGE_MASK;
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page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) -
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MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
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PAGE_SHIFT;
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err = uverbs_copy_to(attrs,
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MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
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&start_offset, sizeof(start_offset));
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if (err)
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goto err_dealloc;
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err = uverbs_copy_to(attrs,
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MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
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&page_idx, sizeof(page_idx));
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if (err)
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goto err_dealloc;
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bitmap_set(to_mucontext(context)->dm_pages, page_idx,
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DIV_ROUND_UP(act_size, PAGE_SIZE));
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dm->dev_addr = memic_addr;
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return &dm->ibdm;
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err_dealloc:
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mlx5_cmd_dealloc_memic(memic, memic_addr,
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act_size);
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err_free:
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kfree(dm);
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return ERR_PTR(err);
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}
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int mlx5_ib_dealloc_dm(struct ib_dm *ibdm)
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{
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struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic;
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struct mlx5_ib_dm *dm = to_mdm(ibdm);
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u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE);
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u32 page_idx;
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int ret;
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ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size);
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if (ret)
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return ret;
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page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) -
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MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
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PAGE_SHIFT;
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bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages,
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page_idx,
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DIV_ROUND_UP(act_size, PAGE_SIZE));
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kfree(dm);
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return 0;
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}
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static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
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struct ib_ucontext *context,
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struct ib_udata *udata)
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@ -4834,13 +4954,22 @@ static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
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mlx5_nic_vport_disable_roce(dev->mdev);
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}
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ADD_UVERBS_ATTRIBUTES_SIMPLE(mlx5_ib_dm, UVERBS_OBJECT_DM,
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UVERBS_METHOD_DM_ALLOC,
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&UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
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UVERBS_ATTR_TYPE(u64),
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UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)),
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&UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
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UVERBS_ATTR_TYPE(u16),
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UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)));
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ADD_UVERBS_ATTRIBUTES_SIMPLE(mlx5_ib_flow_action, UVERBS_OBJECT_FLOW_ACTION,
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UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
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&UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
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UVERBS_ATTR_TYPE(u64),
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UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)));
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#define NUM_TREES 1
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#define NUM_TREES 2
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static int populate_specs_root(struct mlx5_ib_dev *dev)
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{
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const struct uverbs_object_tree_def *default_root[NUM_TREES + 1] = {
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@ -4851,6 +4980,10 @@ static int populate_specs_root(struct mlx5_ib_dev *dev)
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!WARN_ON(num_trees >= ARRAY_SIZE(default_root)))
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default_root[num_trees++] = &mlx5_ib_flow_action;
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if (MLX5_CAP_DEV_MEM(dev->mdev, memic) &&
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!WARN_ON(num_trees >= ARRAY_SIZE(default_root)))
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default_root[num_trees++] = &mlx5_ib_dm;
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dev->ib_dev.specs_root =
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uverbs_alloc_spec_tree(num_trees, default_root);
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@ -4925,6 +5058,9 @@ int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
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INIT_LIST_HEAD(&dev->qp_list);
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spin_lock_init(&dev->reset_flow_resource_lock);
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spin_lock_init(&dev->memic.memic_lock);
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dev->memic.dev = mdev;
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#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
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err = init_srcu_struct(&dev->mr_srcu);
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if (err)
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@ -5087,6 +5223,11 @@ int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
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(1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
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}
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if (MLX5_CAP_DEV_MEM(mdev, memic)) {
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dev->ib_dev.alloc_dm = mlx5_ib_alloc_dm;
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dev->ib_dev.dealloc_dm = mlx5_ib_dealloc_dm;
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}
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dev->ib_dev.create_flow = mlx5_ib_create_flow;
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dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
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dev->ib_dev.uverbs_ex_cmd_mask |=
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@ -45,6 +45,7 @@
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#include <linux/mlx5/transobj.h>
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#include <rdma/ib_user_verbs.h>
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#include <rdma/mlx5-abi.h>
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#include <rdma/uverbs_ioctl.h>
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#define mlx5_ib_dbg(dev, format, arg...) \
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pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
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@ -108,6 +109,16 @@ enum {
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MLX5_IB_INVALID_BFREG = BIT(31),
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};
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enum {
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MLX5_MAX_MEMIC_PAGES = 0x100,
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MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f,
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};
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enum {
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MLX5_MEMIC_BASE_ALIGN = 6,
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MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN,
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};
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struct mlx5_ib_vma_private_data {
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struct list_head list;
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struct vm_area_struct *vma;
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@ -131,6 +142,7 @@ struct mlx5_ib_ucontext {
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struct mutex vma_private_list_mutex;
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u64 lib_caps;
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DECLARE_BITMAP(dm_pages, MLX5_MAX_MEMIC_PAGES);
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};
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static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
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@ -521,6 +533,11 @@ enum mlx5_ib_mtt_access_flags {
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MLX5_IB_MTT_WRITE = (1 << 1),
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};
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struct mlx5_ib_dm {
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struct ib_dm ibdm;
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phys_addr_t dev_addr;
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};
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#define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE)
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struct mlx5_ib_mr {
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@ -784,6 +801,12 @@ struct mlx5_ib_flow_action {
|
|||
};
|
||||
};
|
||||
|
||||
struct mlx5_memic {
|
||||
struct mlx5_core_dev *dev;
|
||||
spinlock_t memic_lock;
|
||||
DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES);
|
||||
};
|
||||
|
||||
struct mlx5_ib_dev {
|
||||
struct ib_device ib_dev;
|
||||
struct mlx5_core_dev *mdev;
|
||||
|
|
@ -830,6 +853,7 @@ struct mlx5_ib_dev {
|
|||
u8 umr_fence;
|
||||
struct list_head ib_dev_list;
|
||||
u64 sys_image_guid;
|
||||
struct mlx5_memic memic;
|
||||
};
|
||||
|
||||
static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)
|
||||
|
|
@ -897,6 +921,11 @@ static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq)
|
|||
return container_of(msrq, struct mlx5_ib_srq, msrq);
|
||||
}
|
||||
|
||||
static inline struct mlx5_ib_dm *to_mdm(struct ib_dm *ibdm)
|
||||
{
|
||||
return container_of(ibdm, struct mlx5_ib_dm, ibdm);
|
||||
}
|
||||
|
||||
static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr)
|
||||
{
|
||||
return container_of(ibmr, struct mlx5_ib_mr, ibmr);
|
||||
|
|
@ -1041,7 +1070,11 @@ struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
|
|||
struct ib_udata *udata);
|
||||
int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table);
|
||||
bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev);
|
||||
|
||||
struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
|
||||
struct ib_ucontext *context,
|
||||
struct ib_dm_alloc_attr *attr,
|
||||
struct uverbs_attr_bundle *attrs);
|
||||
int mlx5_ib_dealloc_dm(struct ib_dm *ibdm);
|
||||
|
||||
#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
|
||||
void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev);
|
||||
|
|
|
|||
|
|
@ -92,6 +92,8 @@ enum {
|
|||
MLX5_CMD_OP_DESTROY_MKEY = 0x202,
|
||||
MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
|
||||
MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
|
||||
MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
|
||||
MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
|
||||
MLX5_CMD_OP_CREATE_EQ = 0x301,
|
||||
MLX5_CMD_OP_DESTROY_EQ = 0x302,
|
||||
MLX5_CMD_OP_QUERY_EQ = 0x303,
|
||||
|
|
@ -8886,4 +8888,57 @@ struct mlx5_ifc_destroy_vport_lag_in_bits {
|
|||
u8 reserved_at_40[0x40];
|
||||
};
|
||||
|
||||
struct mlx5_ifc_alloc_memic_in_bits {
|
||||
u8 opcode[0x10];
|
||||
u8 reserved_at_10[0x10];
|
||||
|
||||
u8 reserved_at_20[0x10];
|
||||
u8 op_mod[0x10];
|
||||
|
||||
u8 reserved_at_30[0x20];
|
||||
|
||||
u8 reserved_at_40[0x18];
|
||||
u8 log_memic_addr_alignment[0x8];
|
||||
|
||||
u8 range_start_addr[0x40];
|
||||
|
||||
u8 range_size[0x20];
|
||||
|
||||
u8 memic_size[0x20];
|
||||
};
|
||||
|
||||
struct mlx5_ifc_alloc_memic_out_bits {
|
||||
u8 status[0x8];
|
||||
u8 reserved_at_8[0x18];
|
||||
|
||||
u8 syndrome[0x20];
|
||||
|
||||
u8 memic_start_addr[0x40];
|
||||
};
|
||||
|
||||
struct mlx5_ifc_dealloc_memic_in_bits {
|
||||
u8 opcode[0x10];
|
||||
u8 reserved_at_10[0x10];
|
||||
|
||||
u8 reserved_at_20[0x10];
|
||||
u8 op_mod[0x10];
|
||||
|
||||
u8 reserved_at_40[0x40];
|
||||
|
||||
u8 memic_start_addr[0x40];
|
||||
|
||||
u8 memic_size[0x20];
|
||||
|
||||
u8 reserved_at_e0[0x20];
|
||||
};
|
||||
|
||||
struct mlx5_ifc_dealloc_memic_out_bits {
|
||||
u8 status[0x8];
|
||||
u8 reserved_at_8[0x18];
|
||||
|
||||
u8 syndrome[0x20];
|
||||
|
||||
u8 reserved_at_40[0x40];
|
||||
};
|
||||
|
||||
#endif /* MLX5_IFC_H */
|
||||
|
|
|
|||
|
|
@ -430,6 +430,7 @@ enum mlx5_ib_mmap_cmd {
|
|||
MLX5_IB_MMAP_CORE_CLOCK = 5,
|
||||
MLX5_IB_MMAP_ALLOC_WC = 6,
|
||||
MLX5_IB_MMAP_CLOCK_INFO = 7,
|
||||
MLX5_IB_MMAP_DEVICE_MEM = 8,
|
||||
};
|
||||
|
||||
enum {
|
||||
|
|
|
|||
|
|
@ -40,5 +40,9 @@ enum mlx5_ib_create_flow_action_attrs {
|
|||
MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS = (1U << UVERBS_ID_NS_SHIFT),
|
||||
};
|
||||
|
||||
#endif
|
||||
enum mlx5_ib_alloc_dm_attrs {
|
||||
MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET = (1U << UVERBS_ID_NS_SHIFT),
|
||||
MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user