forked from luck/tmp_suning_uos_patched
mmc: s3cmci: moved mach/regs-sdi.h into s3cmci device driver
Since mach/regs-sdi.h is used only for s3cmci.c, so this moves the header file into the driver file, drivers/mmc/host/s3cmci.c file. Cc: Chris Ball <cjb@laptop.org> Tested-by: Sylwester Nawrocki <sylvester.nawrocki@gmail.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Kukjin Kim
parent
6dbe51c251
commit
24fae0fe2c
@ -28,7 +28,6 @@
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#include <plat/regs-ac97.h>
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#include <plat/regs-dma.h>
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#include <mach/regs-lcd.h>
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#include <mach/regs-sdi.h>
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#include <plat/regs-iis.h>
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#include <plat/regs-spi.h>
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@ -28,7 +28,6 @@
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#include <plat/regs-ac97.h>
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#include <plat/regs-dma.h>
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#include <mach/regs-lcd.h>
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#include <mach/regs-sdi.h>
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#include <plat/regs-iis.h>
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#include <plat/regs-spi.h>
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@ -28,7 +28,6 @@
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#include <plat/regs-ac97.h>
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#include <plat/regs-dma.h>
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#include <mach/regs-lcd.h>
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#include <mach/regs-sdi.h>
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#include <plat/regs-iis.h>
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#include <plat/regs-spi.h>
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@ -28,7 +28,6 @@
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#include <plat/regs-ac97.h>
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#include <plat/regs-dma.h>
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#include <mach/regs-lcd.h>
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#include <mach/regs-sdi.h>
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#include <plat/regs-iis.h>
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#include <plat/regs-spi.h>
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@ -1,127 +0,0 @@
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/* arch/arm/mach-s3c2410/include/mach/regs-sdi.h
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*
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* Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
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* http://www.simtec.co.uk/products/SWLINUX/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* S3C2410 MMC/SDIO register definitions
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*/
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#ifndef __ASM_ARM_REGS_SDI
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#define __ASM_ARM_REGS_SDI "regs-sdi.h"
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#define S3C2410_SDICON (0x00)
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#define S3C2410_SDIPRE (0x04)
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#define S3C2410_SDICMDARG (0x08)
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#define S3C2410_SDICMDCON (0x0C)
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#define S3C2410_SDICMDSTAT (0x10)
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#define S3C2410_SDIRSP0 (0x14)
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#define S3C2410_SDIRSP1 (0x18)
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#define S3C2410_SDIRSP2 (0x1C)
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#define S3C2410_SDIRSP3 (0x20)
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#define S3C2410_SDITIMER (0x24)
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#define S3C2410_SDIBSIZE (0x28)
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#define S3C2410_SDIDCON (0x2C)
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#define S3C2410_SDIDCNT (0x30)
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#define S3C2410_SDIDSTA (0x34)
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#define S3C2410_SDIFSTA (0x38)
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#define S3C2410_SDIDATA (0x3C)
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#define S3C2410_SDIIMSK (0x40)
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#define S3C2440_SDIDATA (0x40)
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#define S3C2440_SDIIMSK (0x3C)
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#define S3C2440_SDICON_SDRESET (1<<8)
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#define S3C2440_SDICON_MMCCLOCK (1<<5)
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#define S3C2410_SDICON_BYTEORDER (1<<4)
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#define S3C2410_SDICON_SDIOIRQ (1<<3)
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#define S3C2410_SDICON_RWAITEN (1<<2)
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#define S3C2410_SDICON_FIFORESET (1<<1)
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#define S3C2410_SDICON_CLOCKTYPE (1<<0)
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#define S3C2410_SDICMDCON_ABORT (1<<12)
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#define S3C2410_SDICMDCON_WITHDATA (1<<11)
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#define S3C2410_SDICMDCON_LONGRSP (1<<10)
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#define S3C2410_SDICMDCON_WAITRSP (1<<9)
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#define S3C2410_SDICMDCON_CMDSTART (1<<8)
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#define S3C2410_SDICMDCON_SENDERHOST (1<<6)
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#define S3C2410_SDICMDCON_INDEX (0x3f)
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#define S3C2410_SDICMDSTAT_CRCFAIL (1<<12)
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#define S3C2410_SDICMDSTAT_CMDSENT (1<<11)
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#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1<<10)
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#define S3C2410_SDICMDSTAT_RSPFIN (1<<9)
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#define S3C2410_SDICMDSTAT_XFERING (1<<8)
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#define S3C2410_SDICMDSTAT_INDEX (0xff)
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#define S3C2440_SDIDCON_DS_BYTE (0<<22)
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#define S3C2440_SDIDCON_DS_HALFWORD (1<<22)
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#define S3C2440_SDIDCON_DS_WORD (2<<22)
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#define S3C2410_SDIDCON_IRQPERIOD (1<<21)
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#define S3C2410_SDIDCON_TXAFTERRESP (1<<20)
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#define S3C2410_SDIDCON_RXAFTERCMD (1<<19)
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#define S3C2410_SDIDCON_BUSYAFTERCMD (1<<18)
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#define S3C2410_SDIDCON_BLOCKMODE (1<<17)
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#define S3C2410_SDIDCON_WIDEBUS (1<<16)
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#define S3C2410_SDIDCON_DMAEN (1<<15)
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#define S3C2410_SDIDCON_STOP (1<<14)
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#define S3C2440_SDIDCON_DATSTART (1<<14)
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#define S3C2410_SDIDCON_DATMODE (3<<12)
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#define S3C2410_SDIDCON_BLKNUM (0x7ff)
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/* constants for S3C2410_SDIDCON_DATMODE */
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#define S3C2410_SDIDCON_XFER_READY (0<<12)
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#define S3C2410_SDIDCON_XFER_CHKSTART (1<<12)
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#define S3C2410_SDIDCON_XFER_RXSTART (2<<12)
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#define S3C2410_SDIDCON_XFER_TXSTART (3<<12)
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#define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF)
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#define S3C2410_SDIDCNT_BLKNUM_SHIFT (12)
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#define S3C2410_SDIDSTA_RDYWAITREQ (1<<10)
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#define S3C2410_SDIDSTA_SDIOIRQDETECT (1<<9)
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#define S3C2410_SDIDSTA_FIFOFAIL (1<<8) /* reserved on 2440 */
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#define S3C2410_SDIDSTA_CRCFAIL (1<<7)
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#define S3C2410_SDIDSTA_RXCRCFAIL (1<<6)
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#define S3C2410_SDIDSTA_DATATIMEOUT (1<<5)
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#define S3C2410_SDIDSTA_XFERFINISH (1<<4)
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#define S3C2410_SDIDSTA_BUSYFINISH (1<<3)
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#define S3C2410_SDIDSTA_SBITERR (1<<2) /* reserved on 2410a/2440 */
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#define S3C2410_SDIDSTA_TXDATAON (1<<1)
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#define S3C2410_SDIDSTA_RXDATAON (1<<0)
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#define S3C2440_SDIFSTA_FIFORESET (1<<16)
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#define S3C2440_SDIFSTA_FIFOFAIL (3<<14) /* 3 is correct (2 bits) */
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#define S3C2410_SDIFSTA_TFDET (1<<13)
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#define S3C2410_SDIFSTA_RFDET (1<<12)
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#define S3C2410_SDIFSTA_TFHALF (1<<11)
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#define S3C2410_SDIFSTA_TFEMPTY (1<<10)
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#define S3C2410_SDIFSTA_RFLAST (1<<9)
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#define S3C2410_SDIFSTA_RFFULL (1<<8)
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#define S3C2410_SDIFSTA_RFHALF (1<<7)
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#define S3C2410_SDIFSTA_COUNTMASK (0x7f)
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#define S3C2410_SDIIMSK_RESPONSECRC (1<<17)
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#define S3C2410_SDIIMSK_CMDSENT (1<<16)
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#define S3C2410_SDIIMSK_CMDTIMEOUT (1<<15)
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#define S3C2410_SDIIMSK_RESPONSEND (1<<14)
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#define S3C2410_SDIIMSK_READWAIT (1<<13)
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#define S3C2410_SDIIMSK_SDIOIRQ (1<<12)
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#define S3C2410_SDIIMSK_FIFOFAIL (1<<11)
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#define S3C2410_SDIIMSK_CRCSTATUS (1<<10)
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#define S3C2410_SDIIMSK_DATACRC (1<<9)
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#define S3C2410_SDIIMSK_DATATIMEOUT (1<<8)
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#define S3C2410_SDIIMSK_DATAFINISH (1<<7)
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#define S3C2410_SDIIMSK_BUSYFINISH (1<<6)
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#define S3C2410_SDIIMSK_SBITERR (1<<5) /* reserved 2440/2410a */
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#define S3C2410_SDIIMSK_TXFIFOHALF (1<<4)
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#define S3C2410_SDIIMSK_TXFIFOEMPTY (1<<3)
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#define S3C2410_SDIIMSK_RXFIFOLAST (1<<2)
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#define S3C2410_SDIIMSK_RXFIFOFULL (1<<1)
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#define S3C2410_SDIIMSK_RXFIFOHALF (1<<0)
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#endif /* __ASM_ARM_REGS_SDI */
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@ -25,14 +25,93 @@
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#include <mach/dma.h>
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#include <mach/regs-sdi.h>
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#include <linux/platform_data/mmc-s3cmci.h>
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#include "s3cmci.h"
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#define DRIVER_NAME "s3c-mci"
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#define S3C2410_SDICON (0x00)
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#define S3C2410_SDIPRE (0x04)
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#define S3C2410_SDICMDARG (0x08)
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#define S3C2410_SDICMDCON (0x0C)
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#define S3C2410_SDICMDSTAT (0x10)
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#define S3C2410_SDIRSP0 (0x14)
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#define S3C2410_SDIRSP1 (0x18)
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#define S3C2410_SDIRSP2 (0x1C)
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#define S3C2410_SDIRSP3 (0x20)
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#define S3C2410_SDITIMER (0x24)
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#define S3C2410_SDIBSIZE (0x28)
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#define S3C2410_SDIDCON (0x2C)
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#define S3C2410_SDIDCNT (0x30)
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#define S3C2410_SDIDSTA (0x34)
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#define S3C2410_SDIFSTA (0x38)
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#define S3C2410_SDIDATA (0x3C)
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#define S3C2410_SDIIMSK (0x40)
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#define S3C2440_SDIDATA (0x40)
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#define S3C2440_SDIIMSK (0x3C)
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#define S3C2440_SDICON_SDRESET (1 << 8)
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#define S3C2410_SDICON_SDIOIRQ (1 << 3)
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#define S3C2410_SDICON_FIFORESET (1 << 1)
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#define S3C2410_SDICON_CLOCKTYPE (1 << 0)
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#define S3C2410_SDICMDCON_LONGRSP (1 << 10)
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#define S3C2410_SDICMDCON_WAITRSP (1 << 9)
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#define S3C2410_SDICMDCON_CMDSTART (1 << 8)
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#define S3C2410_SDICMDCON_SENDERHOST (1 << 6)
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#define S3C2410_SDICMDCON_INDEX (0x3f)
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#define S3C2410_SDICMDSTAT_CRCFAIL (1 << 12)
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#define S3C2410_SDICMDSTAT_CMDSENT (1 << 11)
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#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1 << 10)
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#define S3C2410_SDICMDSTAT_RSPFIN (1 << 9)
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#define S3C2440_SDIDCON_DS_WORD (2 << 22)
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#define S3C2410_SDIDCON_TXAFTERRESP (1 << 20)
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#define S3C2410_SDIDCON_RXAFTERCMD (1 << 19)
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#define S3C2410_SDIDCON_BLOCKMODE (1 << 17)
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#define S3C2410_SDIDCON_WIDEBUS (1 << 16)
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#define S3C2410_SDIDCON_DMAEN (1 << 15)
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#define S3C2410_SDIDCON_STOP (1 << 14)
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#define S3C2440_SDIDCON_DATSTART (1 << 14)
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#define S3C2410_SDIDCON_XFER_RXSTART (2 << 12)
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#define S3C2410_SDIDCON_XFER_TXSTART (3 << 12)
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#define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF)
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#define S3C2410_SDIDSTA_SDIOIRQDETECT (1 << 9)
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#define S3C2410_SDIDSTA_FIFOFAIL (1 << 8)
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#define S3C2410_SDIDSTA_CRCFAIL (1 << 7)
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#define S3C2410_SDIDSTA_RXCRCFAIL (1 << 6)
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#define S3C2410_SDIDSTA_DATATIMEOUT (1 << 5)
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#define S3C2410_SDIDSTA_XFERFINISH (1 << 4)
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#define S3C2410_SDIDSTA_TXDATAON (1 << 1)
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#define S3C2410_SDIDSTA_RXDATAON (1 << 0)
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#define S3C2440_SDIFSTA_FIFORESET (1 << 16)
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#define S3C2440_SDIFSTA_FIFOFAIL (3 << 14)
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#define S3C2410_SDIFSTA_TFDET (1 << 13)
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#define S3C2410_SDIFSTA_RFDET (1 << 12)
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#define S3C2410_SDIFSTA_COUNTMASK (0x7f)
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#define S3C2410_SDIIMSK_RESPONSECRC (1 << 17)
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#define S3C2410_SDIIMSK_CMDSENT (1 << 16)
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#define S3C2410_SDIIMSK_CMDTIMEOUT (1 << 15)
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#define S3C2410_SDIIMSK_RESPONSEND (1 << 14)
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#define S3C2410_SDIIMSK_SDIOIRQ (1 << 12)
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#define S3C2410_SDIIMSK_FIFOFAIL (1 << 11)
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#define S3C2410_SDIIMSK_CRCSTATUS (1 << 10)
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#define S3C2410_SDIIMSK_DATACRC (1 << 9)
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#define S3C2410_SDIIMSK_DATATIMEOUT (1 << 8)
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#define S3C2410_SDIIMSK_DATAFINISH (1 << 7)
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#define S3C2410_SDIIMSK_TXFIFOHALF (1 << 4)
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#define S3C2410_SDIIMSK_RXFIFOLAST (1 << 2)
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#define S3C2410_SDIIMSK_RXFIFOHALF (1 << 0)
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enum dbg_channels {
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dbg_err = (1 << 0),
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dbg_debug = (1 << 1),
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