forked from luck/tmp_suning_uos_patched
perf/x86: disable PEBS on a guest entry.
If PMU counter has PEBS enabled it is not enough to disable counter on a guest entry since PEBS memory write can overshoot guest entry and corrupt guest memory. Disabling PEBS during guest entry solves the problem. Tested-by: David Ahern <dsahern@gmail.com> Signed-off-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/20120809085234.GI3341@redhat.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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@ -1522,8 +1522,16 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
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arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
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arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
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arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
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/*
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* If PMU counter has PEBS enabled it is not enough to disable counter
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* on a guest entry since PEBS memory write can overshoot guest entry
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* and corrupt guest memory. Disabling PEBS solves the problem.
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*/
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arr[1].msr = MSR_IA32_PEBS_ENABLE;
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arr[1].host = cpuc->pebs_enabled;
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arr[1].guest = 0;
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*nr = 1;
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*nr = 2;
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return arr;
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}
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