forked from luck/tmp_suning_uos_patched
[BNX2]: Add support for 5709 Serdes.
Add PCI ID and code to support the 5709 Serdes PHY. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Michael Chan
David S. Miller
parent
605a9e20aa
commit
27a005b883
@ -84,6 +84,7 @@ typedef enum {
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BCM5708,
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BCM5708S,
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BCM5709,
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BCM5709S,
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} board_t;
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/* indexed by board_t, above */
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@ -98,6 +99,7 @@ static const struct {
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{ "Broadcom NetXtreme II BCM5708 1000Base-T" },
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{ "Broadcom NetXtreme II BCM5708 1000Base-SX" },
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{ "Broadcom NetXtreme II BCM5709 1000Base-T" },
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{ "Broadcom NetXtreme II BCM5709 1000Base-SX" },
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};
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static struct pci_device_id bnx2_pci_tbl[] = {
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@ -117,6 +119,8 @@ static struct pci_device_id bnx2_pci_tbl[] = {
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
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{ 0, }
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};
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@ -699,6 +703,45 @@ bnx2_resolve_flow_ctrl(struct bnx2 *bp)
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}
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}
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static int
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bnx2_5709s_linkup(struct bnx2 *bp)
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{
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u32 val, speed;
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bp->link_up = 1;
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bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
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bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
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bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
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if ((bp->autoneg & AUTONEG_SPEED) == 0) {
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bp->line_speed = bp->req_line_speed;
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bp->duplex = bp->req_duplex;
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return 0;
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}
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speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
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switch (speed) {
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case MII_BNX2_GP_TOP_AN_SPEED_10:
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bp->line_speed = SPEED_10;
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break;
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case MII_BNX2_GP_TOP_AN_SPEED_100:
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bp->line_speed = SPEED_100;
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break;
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case MII_BNX2_GP_TOP_AN_SPEED_1G:
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case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
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bp->line_speed = SPEED_1000;
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break;
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case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
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bp->line_speed = SPEED_2500;
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break;
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}
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if (val & MII_BNX2_GP_TOP_AN_FD)
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bp->duplex = DUPLEX_FULL;
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else
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bp->duplex = DUPLEX_HALF;
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return 0;
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}
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static int
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bnx2_5708s_linkup(struct bnx2 *bp)
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{
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@ -898,6 +941,24 @@ bnx2_set_mac_link(struct bnx2 *bp)
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return 0;
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}
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static void
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bnx2_enable_bmsr1(struct bnx2 *bp)
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{
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if ((bp->phy_flags & PHY_SERDES_FLAG) &&
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(CHIP_NUM(bp) == CHIP_NUM_5709))
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bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
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MII_BNX2_BLK_ADDR_GP_STATUS);
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}
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static void
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bnx2_disable_bmsr1(struct bnx2 *bp)
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{
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if ((bp->phy_flags & PHY_SERDES_FLAG) &&
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(CHIP_NUM(bp) == CHIP_NUM_5709))
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bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
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MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
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}
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static int
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bnx2_test_and_enable_2g5(struct bnx2 *bp)
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{
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@ -910,6 +971,9 @@ bnx2_test_and_enable_2g5(struct bnx2 *bp)
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if (bp->autoneg & AUTONEG_SPEED)
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bp->advertising |= ADVERTISED_2500baseX_Full;
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if (CHIP_NUM(bp) == CHIP_NUM_5709)
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bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
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bnx2_read_phy(bp, bp->mii_up1, &up1);
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if (!(up1 & BCM5708S_UP1_2G5)) {
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up1 |= BCM5708S_UP1_2G5;
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@ -917,6 +981,10 @@ bnx2_test_and_enable_2g5(struct bnx2 *bp)
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ret = 0;
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}
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if (CHIP_NUM(bp) == CHIP_NUM_5709)
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bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
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MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
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return ret;
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}
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@ -929,6 +997,9 @@ bnx2_test_and_disable_2g5(struct bnx2 *bp)
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if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
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return 0;
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if (CHIP_NUM(bp) == CHIP_NUM_5709)
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bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
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bnx2_read_phy(bp, bp->mii_up1, &up1);
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if (up1 & BCM5708S_UP1_2G5) {
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up1 &= ~BCM5708S_UP1_2G5;
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@ -936,6 +1007,10 @@ bnx2_test_and_disable_2g5(struct bnx2 *bp)
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ret = 1;
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}
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if (CHIP_NUM(bp) == CHIP_NUM_5709)
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bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
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MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
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return ret;
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}
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@ -947,7 +1022,21 @@ bnx2_enable_forced_2g5(struct bnx2 *bp)
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if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
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return;
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if (CHIP_NUM(bp) == CHIP_NUM_5708) {
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if (CHIP_NUM(bp) == CHIP_NUM_5709) {
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u32 val;
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bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
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MII_BNX2_BLK_ADDR_SERDES_DIG);
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bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
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val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
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val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
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bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
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bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
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MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
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bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
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} else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
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bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
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bmcr |= BCM5708S_BMCR_FORCE_2500;
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}
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@ -968,7 +1057,20 @@ bnx2_disable_forced_2g5(struct bnx2 *bp)
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if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
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return;
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if (CHIP_NUM(bp) == CHIP_NUM_5708) {
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if (CHIP_NUM(bp) == CHIP_NUM_5709) {
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u32 val;
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bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
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MII_BNX2_BLK_ADDR_SERDES_DIG);
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bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
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val &= ~MII_BNX2_SD_MISC1_FORCE;
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bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
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bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
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MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
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bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
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} else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
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bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
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bmcr &= ~BCM5708S_BMCR_FORCE_2500;
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}
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@ -991,8 +1093,10 @@ bnx2_set_link(struct bnx2 *bp)
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link_up = bp->link_up;
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bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
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bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
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bnx2_enable_bmsr1(bp);
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bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
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bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
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bnx2_disable_bmsr1(bp);
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if ((bp->phy_flags & PHY_SERDES_FLAG) &&
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(CHIP_NUM(bp) == CHIP_NUM_5706)) {
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@ -1013,6 +1117,8 @@ bnx2_set_link(struct bnx2 *bp)
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bnx2_5706s_linkup(bp);
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else if (CHIP_NUM(bp) == CHIP_NUM_5708)
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bnx2_5708s_linkup(bp);
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else if (CHIP_NUM(bp) == CHIP_NUM_5709)
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bnx2_5709s_linkup(bp);
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}
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else {
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bnx2_copper_linkup(bp);
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@ -1119,7 +1225,15 @@ bnx2_setup_serdes_phy(struct bnx2 *bp)
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new_bmcr = bmcr & ~BMCR_ANENABLE;
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new_bmcr |= BMCR_SPEED1000;
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if (CHIP_NUM(bp) == CHIP_NUM_5708) {
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if (CHIP_NUM(bp) == CHIP_NUM_5709) {
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if (bp->req_line_speed == SPEED_2500)
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bnx2_enable_forced_2g5(bp);
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else if (bp->req_line_speed == SPEED_1000) {
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bnx2_disable_forced_2g5(bp);
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new_bmcr &= ~0x2000;
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}
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} else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
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if (bp->req_line_speed == SPEED_2500)
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new_bmcr |= BCM5708S_BMCR_FORCE_2500;
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else
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@ -1302,6 +1416,9 @@ bnx2_setup_copper_phy(struct bnx2 *bp)
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bnx2_resolve_flow_ctrl(bp);
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bnx2_set_mac_link(bp);
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}
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} else {
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bnx2_resolve_flow_ctrl(bp);
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bnx2_set_mac_link(bp);
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}
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return 0;
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}
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@ -1320,11 +1437,64 @@ bnx2_setup_phy(struct bnx2 *bp)
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}
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}
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static int
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bnx2_init_5709s_phy(struct bnx2 *bp)
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{
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u32 val;
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bp->mii_bmcr = MII_BMCR + 0x10;
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bp->mii_bmsr = MII_BMSR + 0x10;
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bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
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bp->mii_adv = MII_ADVERTISE + 0x10;
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bp->mii_lpa = MII_LPA + 0x10;
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bp->mii_up1 = MII_BNX2_OVER1G_UP1;
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bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
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bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
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bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
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bnx2_reset_phy(bp);
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bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
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bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
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val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
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val |= MII_BNX2_SD_1000XCTL1_FIBER;
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bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
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bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
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bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
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if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)
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val |= BCM5708S_UP1_2G5;
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else
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val &= ~BCM5708S_UP1_2G5;
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bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
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bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
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bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
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val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
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bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
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bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
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val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
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MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
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bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
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bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
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return 0;
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}
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static int
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bnx2_init_5708s_phy(struct bnx2 *bp)
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{
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u32 val;
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bnx2_reset_phy(bp);
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bp->mii_up1 = BCM5708S_UP1;
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bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
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bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
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bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
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@ -1377,6 +1547,8 @@ bnx2_init_5708s_phy(struct bnx2 *bp)
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static int
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bnx2_init_5706s_phy(struct bnx2 *bp)
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{
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bnx2_reset_phy(bp);
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bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
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if (CHIP_NUM(bp) == CHIP_NUM_5706)
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@ -1414,6 +1586,8 @@ bnx2_init_copper_phy(struct bnx2 *bp)
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{
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u32 val;
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bnx2_reset_phy(bp);
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if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
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bnx2_write_phy(bp, 0x18, 0x0c00);
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bnx2_write_phy(bp, 0x17, 0x000a);
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@ -1470,13 +1644,12 @@ bnx2_init_phy(struct bnx2 *bp)
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bp->mii_bmcr = MII_BMCR;
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bp->mii_bmsr = MII_BMSR;
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bp->mii_bmsr1 = MII_BMSR;
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bp->mii_adv = MII_ADVERTISE;
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bp->mii_lpa = MII_LPA;
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REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
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bnx2_reset_phy(bp);
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bnx2_read_phy(bp, MII_PHYSID1, &val);
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bp->phy_id = val << 16;
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bnx2_read_phy(bp, MII_PHYSID2, &val);
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@ -1487,6 +1660,8 @@ bnx2_init_phy(struct bnx2 *bp)
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rc = bnx2_init_5706s_phy(bp);
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else if (CHIP_NUM(bp) == CHIP_NUM_5708)
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rc = bnx2_init_5708s_phy(bp);
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else if (CHIP_NUM(bp) == CHIP_NUM_5709)
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rc = bnx2_init_5709s_phy(bp);
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}
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else {
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rc = bnx2_init_copper_phy(bp);
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@ -4262,8 +4437,10 @@ bnx2_test_link(struct bnx2 *bp)
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u32 bmsr;
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spin_lock_bh(&bp->phy_lock);
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bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
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bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
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bnx2_enable_bmsr1(bp);
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bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
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bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
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bnx2_disable_bmsr1(bp);
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spin_unlock_bh(&bp->phy_lock);
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if (bmsr & BMSR_LSTATUS) {
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@ -4407,7 +4584,7 @@ bnx2_timer(unsigned long data)
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if (bp->phy_flags & PHY_SERDES_FLAG) {
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if (CHIP_NUM(bp) == CHIP_NUM_5706)
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bnx2_5706_serdes_timer(bp);
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else if (CHIP_NUM(bp) == CHIP_NUM_5708)
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else
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bnx2_5708_serdes_timer(bp);
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}
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@ -4910,8 +5087,10 @@ bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
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advertising = cmd->advertising;
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}
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else if (cmd->advertising == ADVERTISED_1000baseT_Full) {
|
||||
} else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
|
||||
if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
|
||||
return -EINVAL;
|
||||
} else if (cmd->advertising == ADVERTISED_1000baseT_Full) {
|
||||
advertising = cmd->advertising;
|
||||
}
|
||||
else if (cmd->advertising == ADVERTISED_1000baseT_Half) {
|
||||
|
||||
@ -6296,6 +6296,41 @@ struct l2_fhdr {
|
||||
#define MII_BNX2_DSP_ADDRESS 0x17
|
||||
#define MII_BNX2_DSP_EXPAND_REG 0x0f00
|
||||
|
||||
#define MII_BNX2_BLK_ADDR 0x1f
|
||||
#define MII_BNX2_BLK_ADDR_IEEE0 0x0000
|
||||
#define MII_BNX2_BLK_ADDR_GP_STATUS 0x8120
|
||||
#define MII_BNX2_GP_TOP_AN_STATUS1 0x1b
|
||||
#define MII_BNX2_GP_TOP_AN_SPEED_MSK 0x3f00
|
||||
#define MII_BNX2_GP_TOP_AN_SPEED_10 0x0000
|
||||
#define MII_BNX2_GP_TOP_AN_SPEED_100 0x0100
|
||||
#define MII_BNX2_GP_TOP_AN_SPEED_1G 0x0200
|
||||
#define MII_BNX2_GP_TOP_AN_SPEED_2_5G 0x0300
|
||||
#define MII_BNX2_GP_TOP_AN_SPEED_1GKV 0x0d00
|
||||
#define MII_BNX2_GP_TOP_AN_FD 0x8
|
||||
#define MII_BNX2_BLK_ADDR_SERDES_DIG 0x8300
|
||||
#define MII_BNX2_SERDES_DIG_1000XCTL1 0x10
|
||||
#define MII_BNX2_SD_1000XCTL1_FIBER 0x01
|
||||
#define MII_BNX2_SD_1000XCTL1_AUTODET 0x10
|
||||
#define MII_BNX2_SERDES_DIG_MISC1 0x18
|
||||
#define MII_BNX2_SD_MISC1_FORCE_MSK 0xf
|
||||
#define MII_BNX2_SD_MISC1_FORCE_2_5G 0x0
|
||||
#define MII_BNX2_SD_MISC1_FORCE 0x10
|
||||
#define MII_BNX2_BLK_ADDR_OVER1G 0x8320
|
||||
#define MII_BNX2_OVER1G_UP1 0x19
|
||||
#define MII_BNX2_BLK_ADDR_BAM_NXTPG 0x8350
|
||||
#define MII_BNX2_BAM_NXTPG_CTL 0x10
|
||||
#define MII_BNX2_NXTPG_CTL_BAM 0x1
|
||||
#define MII_BNX2_NXTPG_CTL_T2 0x2
|
||||
#define MII_BNX2_BLK_ADDR_CL73_USERB0 0x8370
|
||||
#define MII_BNX2_CL73_BAM_CTL1 0x12
|
||||
#define MII_BNX2_CL73_BAM_EN 0x8000
|
||||
#define MII_BNX2_CL73_BAM_STA_MGR_EN 0x4000
|
||||
#define MII_BNX2_CL73_BAM_NP_AFT_BP_EN 0x2000
|
||||
#define MII_BNX2_BLK_ADDR_AER 0xffd0
|
||||
#define MII_BNX2_AER_AER 0x1e
|
||||
#define MII_BNX2_AER_AER_AN_MMD 0x3800
|
||||
#define MII_BNX2_BLK_ADDR_COMBO_IEEEB0 0xffe0
|
||||
|
||||
#define MIN_ETHERNET_PACKET_SIZE 60
|
||||
#define MAX_ETHERNET_PACKET_SIZE 1514
|
||||
#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9014
|
||||
@ -6500,6 +6535,7 @@ struct bnx2 {
|
||||
|
||||
u32 mii_bmcr;
|
||||
u32 mii_bmsr;
|
||||
u32 mii_bmsr1;
|
||||
u32 mii_adv;
|
||||
u32 mii_lpa;
|
||||
u32 mii_up1;
|
||||
|
||||
@ -1924,6 +1924,7 @@
|
||||
#define PCI_DEVICE_ID_TIGON3_5752 0x1600
|
||||
#define PCI_DEVICE_ID_TIGON3_5752M 0x1601
|
||||
#define PCI_DEVICE_ID_NX2_5709 0x1639
|
||||
#define PCI_DEVICE_ID_NX2_5709S 0x163a
|
||||
#define PCI_DEVICE_ID_TIGON3_5700 0x1644
|
||||
#define PCI_DEVICE_ID_TIGON3_5701 0x1645
|
||||
#define PCI_DEVICE_ID_TIGON3_5702 0x1646
|
||||
|
||||
Loading…
Reference in New Issue
Block a user