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MIPS: Enable Read Inhibit/eXecute Inhibit for Octeon+ CPUs

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Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/955/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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David Daney 2010-02-10 15:12:49 -08:00 committed by Ralf Baechle
parent 6f329468f3
commit 27a5bd6457
1 changed files with 3 additions and 0 deletions
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arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
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@ -58,6 +58,9 @@
#define cpu_has_vint 0
#define cpu_has_veic 0
#define cpu_hwrena_impl_bits 0xc0000000
#define kernel_uses_smartmips_rixi (cpu_data[0].cputype == CPU_CAVIUM_OCTEON_PLUS)
#define ARCH_HAS_READ_CURRENT_TIMER 1
#define ARCH_HAS_IRQ_PER_CPU 1
#define ARCH_HAS_SPINLOCK_PREFETCH 1