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davinci: misc cleanups from sparse

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- Convert data/functions to static
- include headers for missing declarations
- pointer cleanups:  struct foo *__iomem f --> struct foo __iomem *f;

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This commit is contained in:
Kevin Hilman 2010-02-25 15:36:38 -08:00
parent 66f41d4c5c
commit 28552c2eae
13 changed files with 31 additions and 26 deletions
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2
arch/arm/mach-davinci/board-dm644x-evm.c
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@ -111,7 +111,7 @@ static struct platform_device davinci_evm_norflash_device = {
* It may used instead of the (default) NOR chip to boot, using TI's
* tools to install the secondary boot loader (UBL) and U-Boot.
*/
struct mtd_partition davinci_evm_nandflash_partition[] = {
static struct mtd_partition davinci_evm_nandflash_partition[] = {
/* Bootloader layout depends on whose u-boot is installed, but we
* can hide all the details.
* - block 0 for u-boot environment ... in mainline u-boot

2
arch/arm/mach-davinci/board-neuros-osd2.c
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@ -60,7 +60,7 @@
#define NAND_BLOCK_SIZE SZ_128K
struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
static struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
{
/* UBL (a few copies) plus U-Boot */
.name = "bootloader",

2
arch/arm/mach-davinci/board-sffsdr.c
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@ -48,7 +48,7 @@
#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
static struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
/* U-Boot Environment: Block 0
* UBL: Block 1
* U-Boot: Blocks 6-7 (256 kb)

1
arch/arm/mach-davinci/cdce949.c
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@ -19,6 +19,7 @@
#include <linux/i2c.h>
#include <mach/clock.h>
#include <mach/cdce949.h>
#include "clock.h"

1
arch/arm/mach-davinci/clock.c
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@ -22,6 +22,7 @@
#include <mach/hardware.h>
#include <mach/clock.h>
#include <mach/psc.h>
#include <mach/cputype.h>
#include "clock.h"

2
arch/arm/mach-davinci/devices.c
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@ -23,6 +23,8 @@
#include <mach/mmc.h>
#include <mach/time.h>
#include "clock.h"
#define DAVINCI_I2C_BASE 0x01C21000
#define DAVINCI_MMCSD0_BASE 0x01E10000
#define DM355_MMCSD0_BASE 0x01E11000

2
arch/arm/mach-davinci/dm355.c
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@ -798,7 +798,7 @@ static void __iomem *dm355_psc_bases[] = {
* T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
* T1_TOP: Timer 1, top : <unused>
*/
struct davinci_timer_info dm355_timer_info = {
static struct davinci_timer_info dm355_timer_info = {
.timers = davinci_timer_instance,
.clockevent_id = T0_BOT,
.clocksource_id = T0_TOP,

2
arch/arm/mach-davinci/dm365.c
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@ -1010,7 +1010,7 @@ static void __iomem *dm365_psc_bases[] = {
IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
};
struct davinci_timer_info dm365_timer_info = {
static struct davinci_timer_info dm365_timer_info = {
.timers = davinci_timer_instance,
.clockevent_id = T0_BOT,
.clocksource_id = T0_TOP,

4
arch/arm/mach-davinci/dm644x.c
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@ -277,7 +277,7 @@ static struct clk timer2_clk = {
.usecount = 1, /* REVISIT: why cant' this be disabled? */
};
struct clk_lookup dm644x_clks[] = {
static struct clk_lookup dm644x_clks[] = {
CLK(NULL, "ref", &ref_clk),
CLK(NULL, "pll1", &pll1_clk),
CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
@ -687,7 +687,7 @@ static void __iomem *dm644x_psc_bases[] = {
* T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
* T1_TOP: Timer 1, top : <unused>
*/
struct davinci_timer_info dm644x_timer_info = {
static struct davinci_timer_info dm644x_timer_info = {
.timers = davinci_timer_instance,
.clockevent_id = T0_BOT,
.clocksource_id = T0_TOP,

6
arch/arm/mach-davinci/dm646x.c
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@ -311,7 +311,7 @@ static struct clk vpif1_clk = {
.flags = ALWAYS_ENABLED,
};
struct clk_lookup dm646x_clks[] = {
static struct clk_lookup dm646x_clks[] = {
CLK(NULL, "ref", &ref_clk),
CLK(NULL, "aux", &aux_clkin),
CLK(NULL, "pll1", &pll1_clk),
@ -797,7 +797,7 @@ static void __iomem *dm646x_psc_bases[] = {
* T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
* T1_TOP: Timer 1, top : <unused>
*/
struct davinci_timer_info dm646x_timer_info = {
static struct davinci_timer_info dm646x_timer_info = {
.timers = davinci_timer_instance,
.clockevent_id = T0_BOT,
.clocksource_id = T0_TOP,
@ -867,7 +867,7 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
.sram_len = SZ_32K,
};
void __init dm646x_init_ide()
void __init dm646x_init_ide(void)
{
davinci_cfg_reg(DM646X_ATAEN);
platform_device_register(&ide_dev);

24
arch/arm/mach-davinci/gpio.c
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@ -24,14 +24,14 @@ static DEFINE_SPINLOCK(gpio_lock);
struct davinci_gpio {
struct gpio_chip chip;
struct gpio_controller *__iomem regs;
struct gpio_controller __iomem *regs;
int irq_base;
};
static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
/* create a non-inlined version */
static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio)
static struct gpio_controller __iomem __init *gpio2controller(unsigned gpio)
{
return __gpio_to_controller(gpio);
}
@ -48,7 +48,7 @@ static int __init davinci_gpio_irq_setup(void);
static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
{
struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
struct gpio_controller *__iomem g = d->regs;
struct gpio_controller __iomem *g = d->regs;
u32 temp;
spin_lock(&gpio_lock);
@ -70,7 +70,7 @@ static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
struct gpio_controller *__iomem g = d->regs;
struct gpio_controller __iomem *g = d->regs;
return (1 << offset) & __raw_readl(&g->in_data);
}
@ -79,7 +79,7 @@ static int
davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
{
struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
struct gpio_controller *__iomem g = d->regs;
struct gpio_controller __iomem *g = d->regs;
u32 temp;
u32 mask = 1 << offset;
@ -99,7 +99,7 @@ static void
davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
struct gpio_controller *__iomem g = d->regs;
struct gpio_controller __iomem *g = d->regs;
__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
}
@ -161,7 +161,7 @@ pure_initcall(davinci_gpio_setup);
static void gpio_irq_disable(unsigned irq)
{
struct gpio_controller *__iomem g = get_irq_chip_data(irq);
struct gpio_controller __iomem *g = get_irq_chip_data(irq);
u32 mask = (u32) get_irq_data(irq);
__raw_writel(mask, &g->clr_falling);
@ -170,7 +170,7 @@ static void gpio_irq_disable(unsigned irq)
static void gpio_irq_enable(unsigned irq)
{
struct gpio_controller *__iomem g = get_irq_chip_data(irq);
struct gpio_controller __iomem *g = get_irq_chip_data(irq);
u32 mask = (u32) get_irq_data(irq);
unsigned status = irq_desc[irq].status;
@ -186,7 +186,7 @@ static void gpio_irq_enable(unsigned irq)
static int gpio_irq_type(unsigned irq, unsigned trigger)
{
struct gpio_controller *__iomem g = get_irq_chip_data(irq);
struct gpio_controller __iomem *g = get_irq_chip_data(irq);
u32 mask = (u32) get_irq_data(irq);
if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@ -215,7 +215,7 @@ static struct irq_chip gpio_irqchip = {
static void
gpio_irq_handler(unsigned irq, struct irq_desc *desc)
{
struct gpio_controller *__iomem g = get_irq_chip_data(irq);
struct gpio_controller __iomem *g = get_irq_chip_data(irq);
u32 mask = 0xffff;
/* we only care about one bank */
@ -276,7 +276,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger)
{
struct gpio_controller *__iomem g = get_irq_chip_data(irq);
struct gpio_controller __iomem *g = get_irq_chip_data(irq);
u32 mask = (u32) get_irq_data(irq);
if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@ -305,7 +305,7 @@ static int __init davinci_gpio_irq_setup(void)
u32 binten = 0;
unsigned ngpio, bank_irq;
struct davinci_soc_info *soc_info = &davinci_soc_info;
struct gpio_controller *__iomem g;
struct gpio_controller __iomem *g;
ngpio = soc_info->gpio_num;

8
arch/arm/mach-davinci/include/mach/gpio.h
View File

@ -67,10 +67,10 @@ struct gpio_controller {
*
* These are NOT part of the cross-platform GPIO interface
*/
static inline struct gpio_controller *__iomem
static inline struct gpio_controller __iomem *
__gpio_to_controller(unsigned gpio)
{
void *__iomem ptr;
void __iomem *ptr;
void __iomem *base = davinci_soc_info.gpio_base;
if (gpio < 32 * 1)
@ -102,7 +102,7 @@ static inline u32 __gpio_mask(unsigned gpio)
static inline void gpio_set_value(unsigned gpio, int value)
{
if (__builtin_constant_p(value) && gpio < DAVINCI_N_GPIO) {
struct gpio_controller *__iomem g;
struct gpio_controller __iomem *g;
u32 mask;
g = __gpio_to_controller(gpio);
@ -128,7 +128,7 @@ static inline void gpio_set_value(unsigned gpio, int value)
*/
static inline int gpio_get_value(unsigned gpio)
{
struct gpio_controller *__iomem g;
struct gpio_controller __iomem *g;
if (!__builtin_constant_p(gpio) || gpio >= DAVINCI_N_GPIO)
return __gpio_get_value(gpio);

1
arch/arm/mach-davinci/mux.c
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@ -21,6 +21,7 @@
#include <mach/mux.h>
#include <mach/common.h>
#include <mach/da8xx.h>
/*
* Sets the DAVINCI MUX register based on the table