forked from luck/tmp_suning_uos_patched
pinctrl: cherryview: Re-use data structures from pinctrl-intel.h (part 3)
We have some data structures duplicated across the drivers. Let's deduplicate them by using struct intel_pinctrl_soc_data, struct intel_community and struct intel_pinctrl_context that are being provided by pinctrl-intel.h. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
This commit is contained in:
Andy Shevchenko
parent
c8f8f65ea8
commit
293428f932
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@ -2,7 +2,7 @@
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/*
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* Cherryview/Braswell pinctrl driver
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*
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* Copyright (C) 2014, Intel Corporation
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* Copyright (C) 2014, 2020 Intel Corporation
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* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
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*
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* This driver is based on the original Cherryview GPIO driver by
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@ -67,35 +67,7 @@
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#define CHV_PADCTRL1_INTWAKECFG_BOTH 3
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#define CHV_PADCTRL1_INTWAKECFG_LEVEL 4
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/**
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* struct chv_community - A community specific configuration
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* @uid: ACPI _UID used to match the community
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* @pins: All pins in this community
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* @npins: Number of pins
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* @groups: All groups in this community
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* @ngroups: Number of groups
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* @functions: All functions in this community
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* @nfunctions: Number of functions
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* @gpps: Pad groups
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* @ngpps: Number of pad groups in this community
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* @nirqs: Total number of IRQs this community can generate
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* @acpi_space_id: An address space ID for ACPI OpRegion handler
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*/
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struct chv_community {
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const char *uid;
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const struct pinctrl_pin_desc *pins;
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size_t npins;
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const struct intel_pingroup *groups;
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size_t ngroups;
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const struct intel_function *functions;
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size_t nfunctions;
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const struct intel_padgroup *gpps;
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size_t ngpps;
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size_t nirqs;
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acpi_adr_space_type acpi_space_id;
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};
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struct chv_pin_context {
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struct intel_pad_context {
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u32 padctrl0;
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u32 padctrl1;
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};
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@ -107,13 +79,13 @@ struct chv_pin_context {
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* @pctldev: Pointer to the pin controller device
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* @chip: GPIO chip in this pin controller
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* @irqchip: IRQ chip in this pin controller
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* @regs: MMIO registers
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* @soc: Community specific pin configuration data
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* @communities: All communities in this pin controller
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* @ncommunities: Number of communities in this pin controller
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* @context: Configuration saved over system sleep
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* @irq: Our parent irq
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* @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO
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* offset (in GPIO number space)
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* @community: Community this pinctrl instance represents
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* @intr_lines: Mapping between 16 HW interrupt wires and GPIO offset (in GPIO number space)
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* @saved_intmask: Interrupt mask saved for system sleep
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* @saved_pin_context: Pointer to a context of the pins saved for system sleep
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*
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* The first group in @groups is expected to contain all pins that can be
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* used as GPIOs.
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@ -124,24 +96,34 @@ struct chv_pinctrl {
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struct pinctrl_dev *pctldev;
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struct gpio_chip chip;
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struct irq_chip irqchip;
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void __iomem *regs;
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unsigned int irq;
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const struct intel_pinctrl_soc_data *soc;
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struct intel_community *communities;
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size_t ncommunities;
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struct intel_pinctrl_context context;
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int irq;
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unsigned int intr_lines[16];
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const struct chv_community *community;
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u32 saved_intmask;
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struct chv_pin_context *saved_pin_context;
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};
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#define PINMODE_INVERT_OE BIT(15)
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#define PINMODE(m, i) ((m) | ((i) * PINMODE_INVERT_OE))
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#define CHV_GPP(start, end) \
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#define CHV_GPP(start, end) \
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{ \
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.base = (start), \
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.size = (end) - (start) + 1, \
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}
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#define CHV_COMMUNITY(g, i, a) \
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{ \
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.gpps = (g), \
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.ngpps = ARRAY_SIZE(g), \
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.nirqs = (i), \
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.acpi_space_id = (a), \
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}
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static const struct pinctrl_pin_desc southwest_pins[] = {
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PINCTRL_PIN(0, "FST_SPI_D2"),
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PINCTRL_PIN(1, "FST_SPI_D0"),
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@ -303,7 +285,15 @@ static const struct intel_padgroup southwest_gpps[] = {
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CHV_GPP(90, 97),
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};
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static const struct chv_community southwest_community = {
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/*
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* Southwest community can generate GPIO interrupts only for the first 8
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* interrupts. The upper half (8-15) can only be used to trigger GPEs.
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*/
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static const struct intel_community southwest_communities[] = {
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CHV_COMMUNITY(southwest_gpps, 8, 0x91),
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};
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static const struct intel_pinctrl_soc_data southwest_soc_data = {
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.uid = "1",
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.pins = southwest_pins,
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.npins = ARRAY_SIZE(southwest_pins),
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@ -311,15 +301,8 @@ static const struct chv_community southwest_community = {
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.ngroups = ARRAY_SIZE(southwest_groups),
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.functions = southwest_functions,
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.nfunctions = ARRAY_SIZE(southwest_functions),
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.gpps = southwest_gpps,
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.ngpps = ARRAY_SIZE(southwest_gpps),
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/*
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* Southwest community can generate GPIO interrupts only for the
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* first 8 interrupts. The upper half (8-15) can only be used to
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* trigger GPEs.
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*/
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.nirqs = 8,
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.acpi_space_id = 0x91,
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.communities = southwest_communities,
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.ncommunities = ARRAY_SIZE(southwest_communities),
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};
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static const struct pinctrl_pin_desc north_pins[] = {
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@ -396,19 +379,20 @@ static const struct intel_padgroup north_gpps[] = {
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CHV_GPP(60, 72),
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};
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static const struct chv_community north_community = {
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/*
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* North community can generate GPIO interrupts only for the first 8
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* interrupts. The upper half (8-15) can only be used to trigger GPEs.
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*/
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static const struct intel_community north_communities[] = {
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CHV_COMMUNITY(north_gpps, 8, 0x92),
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};
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static const struct intel_pinctrl_soc_data north_soc_data = {
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.uid = "2",
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.pins = north_pins,
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.npins = ARRAY_SIZE(north_pins),
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.gpps = north_gpps,
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.ngpps = ARRAY_SIZE(north_gpps),
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/*
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* North community can generate GPIO interrupts only for the first
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* 8 interrupts. The upper half (8-15) can only be used to trigger
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* GPEs.
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*/
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.nirqs = 8,
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.acpi_space_id = 0x92,
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.communities = north_communities,
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.ncommunities = ARRAY_SIZE(north_communities),
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};
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static const struct pinctrl_pin_desc east_pins[] = {
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@ -444,14 +428,16 @@ static const struct intel_padgroup east_gpps[] = {
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CHV_GPP(15, 26),
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};
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static const struct chv_community east_community = {
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static const struct intel_community east_communities[] = {
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CHV_COMMUNITY(east_gpps, 16, 0x93),
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};
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static const struct intel_pinctrl_soc_data east_soc_data = {
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.uid = "3",
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.pins = east_pins,
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.npins = ARRAY_SIZE(east_pins),
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.gpps = east_gpps,
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.ngpps = ARRAY_SIZE(east_gpps),
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.nirqs = 16,
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.acpi_space_id = 0x93,
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.communities = east_communities,
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.ncommunities = ARRAY_SIZE(east_communities),
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};
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static const struct pinctrl_pin_desc southeast_pins[] = {
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@ -566,7 +552,11 @@ static const struct intel_padgroup southeast_gpps[] = {
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CHV_GPP(75, 85),
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};
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static const struct chv_community southeast_community = {
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static const struct intel_community southeast_communities[] = {
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CHV_COMMUNITY(southeast_gpps, 16, 0x94),
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};
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static const struct intel_pinctrl_soc_data southeast_soc_data = {
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.uid = "4",
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.pins = southeast_pins,
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.npins = ARRAY_SIZE(southeast_pins),
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@ -574,17 +564,16 @@ static const struct chv_community southeast_community = {
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.ngroups = ARRAY_SIZE(southeast_groups),
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.functions = southeast_functions,
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.nfunctions = ARRAY_SIZE(southeast_functions),
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.gpps = southeast_gpps,
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.ngpps = ARRAY_SIZE(southeast_gpps),
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.nirqs = 16,
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.acpi_space_id = 0x94,
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.communities = southeast_communities,
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.ncommunities = ARRAY_SIZE(southeast_communities),
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};
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static const struct chv_community *chv_communities[] = {
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&southwest_community,
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&north_community,
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&east_community,
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&southeast_community,
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static const struct intel_pinctrl_soc_data *chv_soc_data[] = {
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&southwest_soc_data,
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&north_soc_data,
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&east_soc_data,
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&southeast_soc_data,
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NULL
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};
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/*
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@ -600,12 +589,15 @@ static DEFINE_RAW_SPINLOCK(chv_lock);
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static u32 chv_pctrl_readl(struct chv_pinctrl *pctrl, unsigned int offset)
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{
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return readl(pctrl->regs + offset);
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const struct intel_community *community = &pctrl->communities[0];
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return readl(community->regs + offset);
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}
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static void chv_pctrl_writel(struct chv_pinctrl *pctrl, unsigned int offset, u32 value)
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{
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void __iomem *reg = pctrl->regs + offset;
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const struct intel_community *community = &pctrl->communities[0];
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void __iomem *reg = community->regs + offset;
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/* Write and simple read back to confirm the bus transferring done */
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writel(value, reg);
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@ -615,13 +607,13 @@ static void chv_pctrl_writel(struct chv_pinctrl *pctrl, unsigned int offset, u32
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static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned int offset,
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unsigned int reg)
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{
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const struct intel_community *community = &pctrl->communities[0];
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unsigned int family_no = offset / MAX_FAMILY_PAD_GPIO_NO;
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unsigned int pad_no = offset % MAX_FAMILY_PAD_GPIO_NO;
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offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no +
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GPIO_REGS_SIZE * pad_no;
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offset = FAMILY_PAD_REGS_SIZE * family_no + GPIO_REGS_SIZE * pad_no;
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return pctrl->regs + offset + reg;
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return community->pad_regs + offset + reg;
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}
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static u32 chv_readl(struct chv_pinctrl *pctrl, unsigned int pin, unsigned int offset)
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@ -648,7 +640,7 @@ static int chv_get_groups_count(struct pinctrl_dev *pctldev)
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{
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struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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return pctrl->community->ngroups;
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return pctrl->soc->ngroups;
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}
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static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
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@ -656,7 +648,7 @@ static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
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{
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struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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return pctrl->community->groups[group].name;
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return pctrl->soc->groups[group].name;
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}
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static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
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@ -664,8 +656,8 @@ static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
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{
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struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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*pins = pctrl->community->groups[group].pins;
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*npins = pctrl->community->groups[group].npins;
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*pins = pctrl->soc->groups[group].pins;
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*npins = pctrl->soc->groups[group].npins;
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return 0;
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}
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@ -713,7 +705,7 @@ static int chv_get_functions_count(struct pinctrl_dev *pctldev)
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{
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struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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return pctrl->community->nfunctions;
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return pctrl->soc->nfunctions;
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}
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static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
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@ -721,7 +713,7 @@ static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
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{
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struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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return pctrl->community->functions[function].name;
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return pctrl->soc->functions[function].name;
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}
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static int chv_get_function_groups(struct pinctrl_dev *pctldev,
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@ -731,8 +723,8 @@ static int chv_get_function_groups(struct pinctrl_dev *pctldev,
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{
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struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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*groups = pctrl->community->functions[function].groups;
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*ngroups = pctrl->community->functions[function].ngroups;
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*groups = pctrl->soc->functions[function].groups;
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*ngroups = pctrl->soc->functions[function].ngroups;
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return 0;
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}
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@ -744,7 +736,7 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
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unsigned long flags;
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int i;
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grp = &pctrl->community->groups[group];
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grp = &pctrl->soc->groups[group];
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raw_spin_lock_irqsave(&chv_lock, flags);
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@ -1412,6 +1404,7 @@ static void chv_gpio_irq_handler(struct irq_desc *desc)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
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const struct intel_community *community = &pctrl->communities[0];
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned long pending;
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unsigned long flags;
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@ -1423,7 +1416,7 @@ static void chv_gpio_irq_handler(struct irq_desc *desc)
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pending = chv_pctrl_readl(pctrl, CHV_INTSTAT);
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) {
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for_each_set_bit(intr_line, &pending, community->nirqs) {
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unsigned int irq, offset;
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offset = pctrl->intr_lines[intr_line];
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@ -1480,15 +1473,15 @@ static void chv_init_irq_valid_mask(struct gpio_chip *chip,
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unsigned int ngpios)
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{
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struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
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const struct chv_community *community = pctrl->community;
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const struct intel_community *community = &pctrl->communities[0];
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int i;
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/* Do not add GPIOs that can only generate GPEs to the IRQ domain */
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for (i = 0; i < community->npins; i++) {
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for (i = 0; i < pctrl->soc->npins; i++) {
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const struct pinctrl_pin_desc *desc;
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u32 intsel;
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desc = &community->pins[i];
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desc = &pctrl->soc->pins[i];
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intsel = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
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intsel &= CHV_PADCTRL0_INTSEL_MASK;
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@ -1502,6 +1495,7 @@ static void chv_init_irq_valid_mask(struct gpio_chip *chip,
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static int chv_gpio_irq_init_hw(struct gpio_chip *chip)
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{
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struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
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const struct intel_community *community = &pctrl->communities[0];
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/*
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* The same set of machines in chv_no_valid_mask[] have incorrectly
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@ -1515,7 +1509,7 @@ static int chv_gpio_irq_init_hw(struct gpio_chip *chip)
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* Mask all interrupts the community is able to generate
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* but leave the ones that can only generate GPEs unmasked.
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*/
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chv_pctrl_writel(pctrl, CHV_INTMASK, GENMASK(31, pctrl->community->nirqs));
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chv_pctrl_writel(pctrl, CHV_INTMASK, GENMASK(31, community->nirqs));
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}
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/* Clear all interrupts */
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@ -1527,7 +1521,7 @@ static int chv_gpio_irq_init_hw(struct gpio_chip *chip)
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static int chv_gpio_add_pin_ranges(struct gpio_chip *chip)
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{
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struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
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const struct chv_community *community = pctrl->community;
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const struct intel_community *community = &pctrl->communities[0];
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const struct intel_padgroup *gpp;
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int ret, i;
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@ -1547,15 +1541,15 @@ static int chv_gpio_add_pin_ranges(struct gpio_chip *chip)
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static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
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{
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const struct intel_community *community = &pctrl->communities[0];
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const struct intel_padgroup *gpp;
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struct gpio_chip *chip = &pctrl->chip;
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bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
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const struct chv_community *community = pctrl->community;
|
||||
int ret, i, irq_base;
|
||||
|
||||
*chip = chv_gpio_chip;
|
||||
|
||||
chip->ngpio = community->pins[community->npins - 1].number + 1;
|
||||
chip->ngpio = pctrl->soc->pins[pctrl->soc->npins - 1].number + 1;
|
||||
chip->label = dev_name(pctrl->dev);
|
||||
chip->add_pin_ranges = chv_gpio_add_pin_ranges;
|
||||
chip->parent = pctrl->dev;
|
||||
|
|
@ -1581,7 +1575,7 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
|
|||
chip->irq.init_valid_mask = chv_init_irq_valid_mask;
|
||||
} else {
|
||||
irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
|
||||
community->npins, NUMA_NO_NODE);
|
||||
pctrl->soc->npins, NUMA_NO_NODE);
|
||||
if (irq_base < 0) {
|
||||
dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n");
|
||||
return irq_base;
|
||||
|
|
@ -1631,6 +1625,10 @@ static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
|
|||
|
||||
static int chv_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct intel_pinctrl_soc_data *soc_data = NULL;
|
||||
const struct intel_pinctrl_soc_data **soc_table;
|
||||
struct intel_community *community;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct chv_pinctrl *pctrl;
|
||||
struct acpi_device *adev;
|
||||
acpi_status status;
|
||||
|
|
@ -1640,40 +1638,53 @@ static int chv_pinctrl_probe(struct platform_device *pdev)
|
|||
if (!adev)
|
||||
return -ENODEV;
|
||||
|
||||
pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
|
||||
soc_table = (const struct intel_pinctrl_soc_data **)device_get_match_data(dev);
|
||||
for (i = 0; soc_table[i]; i++) {
|
||||
if (!strcmp(adev->pnp.unique_id, soc_table[i]->uid)) {
|
||||
soc_data = soc_table[i];
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!soc_data)
|
||||
return -ENODEV;
|
||||
|
||||
pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
|
||||
if (!pctrl)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(chv_communities); i++)
|
||||
if (!strcmp(adev->pnp.unique_id, chv_communities[i]->uid)) {
|
||||
pctrl->community = chv_communities[i];
|
||||
break;
|
||||
}
|
||||
if (i == ARRAY_SIZE(chv_communities))
|
||||
return -ENODEV;
|
||||
|
||||
pctrl->dev = &pdev->dev;
|
||||
pctrl->soc = soc_data;
|
||||
|
||||
pctrl->ncommunities = pctrl->soc->ncommunities;
|
||||
pctrl->communities = devm_kmemdup(dev, pctrl->soc->communities,
|
||||
pctrl->ncommunities * sizeof(*pctrl->communities),
|
||||
GFP_KERNEL);
|
||||
if (!pctrl->communities)
|
||||
return -ENOMEM;
|
||||
|
||||
community = &pctrl->communities[0];
|
||||
community->regs = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(community->regs))
|
||||
return PTR_ERR(community->regs);
|
||||
|
||||
community->pad_regs = community->regs + FAMILY_PAD_REGS_OFF;
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
pctrl->saved_pin_context = devm_kcalloc(pctrl->dev,
|
||||
pctrl->community->npins, sizeof(*pctrl->saved_pin_context),
|
||||
GFP_KERNEL);
|
||||
if (!pctrl->saved_pin_context)
|
||||
pctrl->context.pads = devm_kcalloc(dev, pctrl->soc->npins,
|
||||
sizeof(*pctrl->context.pads),
|
||||
GFP_KERNEL);
|
||||
if (!pctrl->context.pads)
|
||||
return -ENOMEM;
|
||||
#endif
|
||||
|
||||
pctrl->regs = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(pctrl->regs))
|
||||
return PTR_ERR(pctrl->regs);
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0)
|
||||
return irq;
|
||||
|
||||
pctrl->pctldesc = chv_pinctrl_desc;
|
||||
pctrl->pctldesc.name = dev_name(&pdev->dev);
|
||||
pctrl->pctldesc.pins = pctrl->community->pins;
|
||||
pctrl->pctldesc.npins = pctrl->community->npins;
|
||||
pctrl->pctldesc.pins = pctrl->soc->pins;
|
||||
pctrl->pctldesc.npins = pctrl->soc->npins;
|
||||
|
||||
pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
|
||||
pctrl);
|
||||
|
|
@ -1687,7 +1698,7 @@ static int chv_pinctrl_probe(struct platform_device *pdev)
|
|||
return ret;
|
||||
|
||||
status = acpi_install_address_space_handler(adev->handle,
|
||||
pctrl->community->acpi_space_id,
|
||||
community->acpi_space_id,
|
||||
chv_pinctrl_mmio_access_handler,
|
||||
NULL, pctrl);
|
||||
if (ACPI_FAILURE(status))
|
||||
|
|
@ -1701,9 +1712,10 @@ static int chv_pinctrl_probe(struct platform_device *pdev)
|
|||
static int chv_pinctrl_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
|
||||
const struct intel_community *community = &pctrl->communities[0];
|
||||
|
||||
acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev),
|
||||
pctrl->community->acpi_space_id,
|
||||
community->acpi_space_id,
|
||||
chv_pinctrl_mmio_access_handler);
|
||||
|
||||
return 0;
|
||||
|
|
@ -1720,16 +1732,14 @@ static int chv_pinctrl_suspend_noirq(struct device *dev)
|
|||
|
||||
pctrl->saved_intmask = chv_pctrl_readl(pctrl, CHV_INTMASK);
|
||||
|
||||
for (i = 0; i < pctrl->community->npins; i++) {
|
||||
for (i = 0; i < pctrl->soc->npins; i++) {
|
||||
const struct pinctrl_pin_desc *desc;
|
||||
struct chv_pin_context *ctx;
|
||||
struct intel_pad_context *ctx = &pctrl->context.pads[i];
|
||||
|
||||
desc = &pctrl->community->pins[i];
|
||||
desc = &pctrl->soc->pins[i];
|
||||
if (chv_pad_locked(pctrl, desc->number))
|
||||
continue;
|
||||
|
||||
ctx = &pctrl->saved_pin_context[i];
|
||||
|
||||
ctx->padctrl0 = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
|
||||
ctx->padctrl0 &= ~CHV_PADCTRL0_GPIORXSTATE;
|
||||
|
||||
|
|
@ -1756,17 +1766,15 @@ static int chv_pinctrl_resume_noirq(struct device *dev)
|
|||
*/
|
||||
chv_pctrl_writel(pctrl, CHV_INTMASK, 0x0000);
|
||||
|
||||
for (i = 0; i < pctrl->community->npins; i++) {
|
||||
for (i = 0; i < pctrl->soc->npins; i++) {
|
||||
const struct pinctrl_pin_desc *desc;
|
||||
const struct chv_pin_context *ctx;
|
||||
struct intel_pad_context *ctx = &pctrl->context.pads[i];
|
||||
u32 val;
|
||||
|
||||
desc = &pctrl->community->pins[i];
|
||||
desc = &pctrl->soc->pins[i];
|
||||
if (chv_pad_locked(pctrl, desc->number))
|
||||
continue;
|
||||
|
||||
ctx = &pctrl->saved_pin_context[i];
|
||||
|
||||
/* Only restore if our saved state differs from the current */
|
||||
val = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
|
||||
val &= ~CHV_PADCTRL0_GPIORXSTATE;
|
||||
|
|
@ -1803,7 +1811,7 @@ static const struct dev_pm_ops chv_pinctrl_pm_ops = {
|
|||
};
|
||||
|
||||
static const struct acpi_device_id chv_pinctrl_acpi_match[] = {
|
||||
{ "INT33FF" },
|
||||
{ "INT33FF", (kernel_ulong_t)chv_soc_data },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user