forked from luck/tmp_suning_uos_patched
gpio: Add APM X-Gene SoC GPIO controller support
Add APM X-Gene SoC gpio controller driver. Signed-off-by: Feng Kan <fkan@apm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Feng Kan
Linus Walleij
parent
e8126753a9
commit
29cbf4589f
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@ -334,6 +334,15 @@ config GPIO_TZ1090_PDC
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help
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Say yes here to support Toumaz Xenif TZ1090 PDC GPIOs.
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config GPIO_XGENE
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bool "APM X-Gene GPIO controller support"
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depends on ARM64 && OF_GPIO
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help
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This driver is to support the GPIO block within the APM X-Gene SoC
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platform's generic flash controller. The GPIO pins are muxed with
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the generic flash controller's address and data pins. Say yes
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here to enable the GFC GPIO functionality.
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config GPIO_XILINX
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bool "Xilinx GPIO support"
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depends on PPC_OF || MICROBLAZE || ARCH_ZYNQ
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@ -101,6 +101,7 @@ obj-$(CONFIG_GPIO_VX855) += gpio-vx855.o
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obj-$(CONFIG_GPIO_WM831X) += gpio-wm831x.o
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obj-$(CONFIG_GPIO_WM8350) += gpio-wm8350.o
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obj-$(CONFIG_GPIO_WM8994) += gpio-wm8994.o
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obj-$(CONFIG_GPIO_XGENE) += gpio-xgene.o
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obj-$(CONFIG_GPIO_XILINX) += gpio-xilinx.o
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obj-$(CONFIG_GPIO_XTENSA) += gpio-xtensa.o
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obj-$(CONFIG_GPIO_ZEVIO) += gpio-zevio.o
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250
drivers/gpio/gpio-xgene.c
Normal file
250
drivers/gpio/gpio-xgene.c
Normal file
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@ -0,0 +1,250 @@
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/*
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* AppliedMicro X-Gene SoC GPIO Driver
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*
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* Copyright (c) 2014, Applied Micro Circuits Corporation
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* Author: Feng Kan <fkan@apm.com>.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <linux/platform_device.h>
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#include <linux/gpio/driver.h>
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#include <linux/types.h>
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#include <linux/bitops.h>
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#define GPIO_SET_DR_OFFSET 0x0C
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#define GPIO_DATA_OFFSET 0x14
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#define GPIO_BANK_STRIDE 0x0C
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#define XGENE_GPIOS_PER_BANK 16
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#define XGENE_MAX_GPIO_BANKS 3
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#define XGENE_MAX_GPIOS (XGENE_GPIOS_PER_BANK * XGENE_MAX_GPIO_BANKS)
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#define GPIO_BIT_OFFSET(x) (x % XGENE_GPIOS_PER_BANK)
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#define GPIO_BANK_OFFSET(x) ((x / XGENE_GPIOS_PER_BANK) * GPIO_BANK_STRIDE)
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struct xgene_gpio;
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struct xgene_gpio {
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struct gpio_chip chip;
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void __iomem *base;
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spinlock_t lock;
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#ifdef CONFIG_PM
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u32 set_dr_val[XGENE_MAX_GPIO_BANKS];
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#endif
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};
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static inline struct xgene_gpio *to_xgene_gpio(struct gpio_chip *chip)
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{
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return container_of(chip, struct xgene_gpio, chip);
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}
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static int xgene_gpio_get(struct gpio_chip *gc, unsigned int offset)
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{
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struct xgene_gpio *chip = to_xgene_gpio(gc);
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unsigned long bank_offset;
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u32 bit_offset;
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bank_offset = GPIO_DATA_OFFSET + GPIO_BANK_OFFSET(offset);
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bit_offset = GPIO_BIT_OFFSET(offset);
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return !!(ioread32(chip->base + bank_offset) & BIT(bit_offset));
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}
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static void __xgene_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
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{
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struct xgene_gpio *chip = to_xgene_gpio(gc);
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unsigned long bank_offset;
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u32 setval, bit_offset;
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bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
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bit_offset = GPIO_BIT_OFFSET(offset) + XGENE_GPIOS_PER_BANK;
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setval = ioread32(chip->base + bank_offset);
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if (val)
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setval |= BIT(bit_offset);
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else
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setval &= ~BIT(bit_offset);
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iowrite32(setval, chip->base + bank_offset);
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}
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static void xgene_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
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{
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struct xgene_gpio *chip = to_xgene_gpio(gc);
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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__xgene_gpio_set(gc, offset, val);
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spin_unlock_irqrestore(&chip->lock, flags);
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}
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static int xgene_gpio_dir_in(struct gpio_chip *gc, unsigned int offset)
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{
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struct xgene_gpio *chip = to_xgene_gpio(gc);
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unsigned long flags, bank_offset;
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u32 dirval, bit_offset;
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bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
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bit_offset = GPIO_BIT_OFFSET(offset);
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spin_lock_irqsave(&chip->lock, flags);
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dirval = ioread32(chip->base + bank_offset);
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dirval |= BIT(bit_offset);
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iowrite32(dirval, chip->base + bank_offset);
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spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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static int xgene_gpio_dir_out(struct gpio_chip *gc,
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unsigned int offset, int val)
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{
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struct xgene_gpio *chip = to_xgene_gpio(gc);
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unsigned long flags, bank_offset;
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u32 dirval, bit_offset;
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bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
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bit_offset = GPIO_BIT_OFFSET(offset);
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spin_lock_irqsave(&chip->lock, flags);
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dirval = ioread32(chip->base + bank_offset);
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dirval &= ~BIT(bit_offset);
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iowrite32(dirval, chip->base + bank_offset);
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__xgene_gpio_set(gc, offset, val);
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spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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#ifdef CONFIG_PM
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static int xgene_gpio_suspend(struct device *dev)
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{
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struct xgene_gpio *gpio = dev_get_drvdata(dev);
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unsigned long bank_offset;
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unsigned int bank;
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for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank++) {
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bank_offset = GPIO_SET_DR_OFFSET + bank * GPIO_BANK_STRIDE;
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gpio->set_dr_val[bank] = ioread32(gpio->base + bank_offset);
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}
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return 0;
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}
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static int xgene_gpio_resume(struct device *dev)
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{
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struct xgene_gpio *gpio = dev_get_drvdata(dev);
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unsigned long bank_offset;
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unsigned int bank;
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for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank++) {
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bank_offset = GPIO_SET_DR_OFFSET + bank * GPIO_BANK_STRIDE;
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iowrite32(gpio->set_dr_val[bank], gpio->base + bank_offset);
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}
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return 0;
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}
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static SIMPLE_DEV_PM_OPS(xgene_gpio_pm, xgene_gpio_suspend, xgene_gpio_resume);
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#define XGENE_GPIO_PM_OPS (&xgene_gpio_pm)
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#else
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#define XGENE_GPIO_PM_OPS NULL
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#endif
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static int xgene_gpio_probe(struct platform_device *pdev)
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{
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struct resource *res;
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struct xgene_gpio *gpio;
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int err = 0;
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gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
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if (!gpio) {
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err = -ENOMEM;
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goto err;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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gpio->base = devm_ioremap_nocache(&pdev->dev, res->start,
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resource_size(res));
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if (IS_ERR(gpio->base)) {
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err = PTR_ERR(gpio->base);
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goto err;
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}
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gpio->chip.ngpio = XGENE_MAX_GPIOS;
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gpio->chip.dev = &pdev->dev;
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gpio->chip.direction_input = xgene_gpio_dir_in;
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gpio->chip.direction_output = xgene_gpio_dir_out;
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gpio->chip.get = xgene_gpio_get;
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gpio->chip.set = xgene_gpio_set;
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gpio->chip.label = dev_name(&pdev->dev);
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gpio->chip.base = -1;
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platform_set_drvdata(pdev, gpio);
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err = gpiochip_add(&gpio->chip);
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if (err) {
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dev_err(&pdev->dev,
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"failed to register gpiochip.\n");
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goto err;
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}
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dev_info(&pdev->dev, "X-Gene GPIO driver registered.\n");
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return 0;
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err:
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dev_err(&pdev->dev, "X-Gene GPIO driver registration failed.\n");
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return err;
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}
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static int xgene_gpio_remove(struct platform_device *pdev)
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{
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struct xgene_gpio *gpio = platform_get_drvdata(pdev);
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int ret = 0;
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ret = gpiochip_remove(&gpio->chip);
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if (ret)
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dev_err(&pdev->dev, "unable to remove gpio_chip.\n");
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return ret;
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}
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#ifdef CONFIG_OF
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static const struct of_device_id xgene_gpio_of_match[] = {
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{ .compatible = "apm,xgene-gpio", },
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{},
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};
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MODULE_DEVICE_TABLE(of, xgene_gpio_of_match);
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#endif
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static struct platform_driver xgene_gpio_driver = {
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.driver = {
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.name = "xgene-gpio",
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.owner = THIS_MODULE,
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.of_match_table = xgene_gpio_of_match,
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.pm = XGENE_GPIO_PM_OPS,
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},
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.probe = xgene_gpio_probe,
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.remove = xgene_gpio_remove,
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};
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module_platform_driver(xgene_gpio_driver);
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MODULE_AUTHOR("Feng Kan <fkan@apm.com>");
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MODULE_DESCRIPTION("APM X-Gene GPIO driver");
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MODULE_LICENSE("GPL");
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