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ARM: dts: dir685: Drop spi-cpol from the display

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The D-Link DIR-685 had its clock polarity set as active
low using the special SPI "spi-cpol" property.

This is not correct: the datasheet clearly states:
"Fix SCL to GND level when not in use" which is
indicative that this line is active high.

After a recent fix making the GPIO-based SPI driver
force the clock line de-asserted at the beginning of
each SPI transaction this reared its ugly head: now
de-asserted was taken to mean the line should be
driven high, but it should be driven low.

Fix this up in the DTS file and the display works again.

Link: https://lore.kernel.org/r/20190915135444.11066-1-linus.walleij@linaro.org
Cc: Mark Brown <broonie@kernel.org>
Fixes: 2922d1cc16 ("spi: gpio: Add SPI_MASTER_GPIO_SS flag")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Linus Walleij 2019-09-15 15:54:44 +02:00 committed by Arnd Bergmann
parent 375a7baddb
commit 2a7326caab
1 changed files with 0 additions and 1 deletions
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arch/arm/boot/dts/gemini-dlink-dir-685.dts
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@ -72,7 +72,6 @@ panel: display@0 {
reg = <0>;
/* 50 ns min period = 20 MHz */
spi-max-frequency = <20000000>;
spi-cpol; /* Clock active low */
vcc-supply = <&vdisp>;
iovcc-supply = <&vdisp>;
vci-supply = <&vdisp>;