forked from luck/tmp_suning_uos_patched
ARM: Orion: Add clocks using the generic clk infrastructure.
Add tclk as a fixed rate clock for all platforms. In addition, on kirkwood, add a gated clock for most of the clocks which can be gated. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jamie Lentin <jm@lentin.co.uk> [mturquette@linaro.org: removed redundant CLKDEV_LOOKUP from Kconfig] [mturquette@linaro.org: removed redundant clk.h from mach-dove/common.c] Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Andrew Lunn
Mike Turquette
parent
f0948f59db
commit
2f129bf4aa
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@ -1139,6 +1139,7 @@ config PLAT_ORION
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bool
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select CLKSRC_MMIO
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select GENERIC_IRQ_CHIP
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select COMMON_CLK
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config PLAT_PXA
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bool
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@ -13,7 +13,7 @@
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/pci.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/ata_platform.h>
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#include <linux/gpio.h>
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#include <asm/page.h>
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@ -67,6 +67,17 @@ void __init dove_map_io(void)
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iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
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}
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/*****************************************************************************
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* CLK tree
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****************************************************************************/
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static struct clk *tclk;
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static void __init clk_init(void)
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{
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tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
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get_tclk());
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}
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/*****************************************************************************
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* EHCI0
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****************************************************************************/
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@ -272,18 +283,17 @@ void __init dove_sdio1_init(void)
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void __init dove_init(void)
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{
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int tclk;
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tclk = get_tclk();
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printk(KERN_INFO "Dove 88AP510 SoC, ");
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printk(KERN_INFO "TCLK = %dMHz\n", (tclk + 499999) / 1000000);
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printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
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#ifdef CONFIG_CACHE_TAUROS2
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tauros2_init();
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#endif
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dove_setup_cpu_mbus();
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/* Setup root of clk tree */
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clk_init();
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/* internal devices that every board has */
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dove_rtc_init();
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dove_xor0_init();
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@ -42,6 +42,9 @@ static void __init kirkwood_dt_init(void)
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kirkwood_l2_init();
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#endif
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/* Setup root of clk tree */
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kirkwood_clk_init();
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/* internal devices that every board has */
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kirkwood_wdt_init();
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kirkwood_xor0_init();
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@ -15,6 +15,8 @@
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#include <linux/ata_platform.h>
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#include <linux/mtd/nand.h>
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#include <linux/dma-mapping.h>
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#include <linux/clk-provider.h>
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#include <linux/spinlock.h>
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#include <net/dsa.h>
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#include <asm/page.h>
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#include <asm/timex.h>
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@ -31,6 +33,7 @@
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#include <plat/common.h>
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#include <plat/time.h>
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#include <plat/addr-map.h>
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#include <plat/mv_xor.h>
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#include "common.h"
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/*****************************************************************************
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@ -68,6 +71,41 @@ void __init kirkwood_map_io(void)
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unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
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/*****************************************************************************
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* CLK tree
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****************************************************************************/
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static DEFINE_SPINLOCK(gating_lock);
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static struct clk *tclk;
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static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx)
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{
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return clk_register_gate(NULL, name, "tclk", CLK_IGNORE_UNUSED,
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(void __iomem *)CLOCK_GATING_CTRL,
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bit_idx, 0, &gating_lock);
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}
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void __init kirkwood_clk_init(void)
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{
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tclk = clk_register_fixed_rate(NULL, "tclk", NULL,
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CLK_IS_ROOT, kirkwood_tclk);
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kirkwood_register_gate("runit", CGC_BIT_RUNIT);
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kirkwood_register_gate("ge0", CGC_BIT_GE0);
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kirkwood_register_gate("ge1", CGC_BIT_GE1);
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kirkwood_register_gate("sata0", CGC_BIT_SATA0);
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kirkwood_register_gate("sata1", CGC_BIT_SATA1);
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kirkwood_register_gate("usb0", CGC_BIT_USB0);
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kirkwood_register_gate("sdio", CGC_BIT_SDIO);
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kirkwood_register_gate("crypto", CGC_BIT_CRYPTO);
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kirkwood_register_gate("xor0", CGC_BIT_XOR0);
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kirkwood_register_gate("xor1", CGC_BIT_XOR1);
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kirkwood_register_gate("pex0", CGC_BIT_PEX0);
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kirkwood_register_gate("pex1", CGC_BIT_PEX1);
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kirkwood_register_gate("audio", CGC_BIT_AUDIO);
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kirkwood_register_gate("tdm", CGC_BIT_TDM);
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kirkwood_register_gate("tsu", CGC_BIT_TSU);
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}
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/*****************************************************************************
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* EHCI0
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****************************************************************************/
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@ -465,6 +503,9 @@ void __init kirkwood_init(void)
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kirkwood_l2_init();
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#endif
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/* Setup root of clk tree */
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kirkwood_clk_init();
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/* internal devices that every board has */
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kirkwood_rtc_init();
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kirkwood_wdt_init();
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@ -50,6 +50,7 @@ void kirkwood_nand_init(struct mtd_partition *parts, int nr_parts, int delay);
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void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, int (*dev_ready)(struct mtd_info *));
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void kirkwood_audio_init(void);
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void kirkwood_restart(char, const char *);
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void kirkwood_clk_init(void);
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/* board init functions for boards not fully converted to fdt */
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#ifdef CONFIG_MACH_DREAMPLUG_DT
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@ -43,6 +43,22 @@
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#define L2_WRITETHROUGH 0x00000010
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#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE | 0x11c)
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#define CGC_BIT_GE0 (0)
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#define CGC_BIT_PEX0 (2)
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#define CGC_BIT_USB0 (3)
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#define CGC_BIT_SDIO (4)
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#define CGC_BIT_TSU (5)
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#define CGC_BIT_DUNIT (6)
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#define CGC_BIT_RUNIT (7)
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#define CGC_BIT_XOR0 (8)
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#define CGC_BIT_AUDIO (9)
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#define CGC_BIT_SATA0 (14)
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#define CGC_BIT_SATA1 (15)
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#define CGC_BIT_XOR1 (16)
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#define CGC_BIT_CRYPTO (17)
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#define CGC_BIT_PEX1 (18)
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#define CGC_BIT_GE1 (19)
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#define CGC_BIT_TDM (20)
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#define CGC_GE0 (1 << 0)
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#define CGC_PEX0 (1 << 2)
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#define CGC_USB0 (1 << 3)
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@ -13,6 +13,7 @@
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#include <linux/platform_device.h>
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#include <linux/serial_8250.h>
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#include <linux/ata_platform.h>
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#include <linux/clk-provider.h>
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#include <linux/ethtool.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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@ -103,24 +104,24 @@ static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk)
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static int get_tclk(void)
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{
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int tclk;
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int tclk_freq;
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/*
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* TCLK tick rate is configured by DEV_A[2:0] strap pins.
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*/
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switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
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case 1:
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tclk = 166666667;
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tclk_freq = 166666667;
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break;
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case 3:
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tclk = 200000000;
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tclk_freq = 200000000;
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break;
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default:
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panic("unknown TCLK PLL setting: %.8x\n",
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readl(SAMPLE_AT_RESET_HIGH));
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}
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return tclk;
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return tclk_freq;
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}
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@ -165,6 +166,17 @@ void __init mv78xx0_map_io(void)
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}
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/*****************************************************************************
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* CLK tree
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****************************************************************************/
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static struct clk *tclk;
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static void __init clk_init(void)
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{
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tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
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get_tclk());
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}
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/*****************************************************************************
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* EHCI
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****************************************************************************/
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@ -378,25 +390,26 @@ void __init mv78xx0_init(void)
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int hclk;
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int pclk;
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int l2clk;
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int tclk;
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core_index = mv78xx0_core_index();
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hclk = get_hclk();
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get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
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tclk = get_tclk();
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printk(KERN_INFO "%s ", mv78xx0_id());
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printk("core #%d, ", core_index);
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printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
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printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
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printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
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printk("TCLK = %dMHz\n", (tclk + 499999) / 1000000);
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printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
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mv78xx0_setup_cpu_mbus();
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#ifdef CONFIG_CACHE_FEROCEON_L2
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feroceon_l2_init(is_l2_writethrough());
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#endif
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/* Setup root of clk tree */
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clk_init();
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}
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void mv78xx0_restart(char mode, const char *cmd)
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@ -18,6 +18,7 @@
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#include <linux/mv643xx_i2c.h>
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#include <linux/ata_platform.h>
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#include <linux/delay.h>
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#include <linux/clk-provider.h>
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#include <net/dsa.h>
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#include <asm/page.h>
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#include <asm/setup.h>
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@ -69,6 +70,17 @@ void __init orion5x_map_io(void)
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}
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/*****************************************************************************
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* CLK tree
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****************************************************************************/
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static struct clk *tclk;
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static void __init clk_init(void)
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{
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tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
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orion5x_tclk);
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}
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/*****************************************************************************
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* EHCI0
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****************************************************************************/
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@ -276,6 +288,9 @@ void __init orion5x_init(void)
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*/
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orion5x_setup_cpu_mbus_bridge();
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/* Setup root of clk tree */
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clk_init();
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/*
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* Don't issue "Wait for Interrupt" instruction if we are
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* running on D0 5281 silicon.
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@ -14,6 +14,8 @@
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#include <linux/dma-mapping.h>
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#include <linux/serial_8250.h>
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#include <linux/ata_platform.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/mv643xx_eth.h>
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#include <linux/mv643xx_i2c.h>
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#include <net/dsa.h>
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