forked from luck/tmp_suning_uos_patched
dt-bindings: iio: adc: Add DT binding document for PMIC5 ADC
PMIC5 ADC has support for clients to measure voltage and current on inputs connected to the PMIC. Clients include reading voltage phone power and on board system thermistors for thermal management. ADC5 on certain PMIC has support to read battery current. This change adds documentation. Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Siddartha Mohanadoss
Jonathan Cameron
parent
5e45729608
commit
2fca585502
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@ -1,7 +1,9 @@
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Qualcomm's SPMI PMIC voltage ADC
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Qualcomm's SPMI PMIC ADC
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SPMI PMIC voltage ADC (VADC) provides interface to clients to read
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voltage. The VADC is a 15-bit sigma-delta ADC.
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- SPMI PMIC voltage ADC (VADC) provides interface to clients to read
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voltage. The VADC is a 15-bit sigma-delta ADC.
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- SPMI PMIC5 voltage ADC (ADC) provides interface to clients to read
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voltage. The VADC is a 16-bit sigma-delta ADC.
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VADC node:
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@ -9,6 +11,8 @@ VADC node:
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Usage: required
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Value type: <string>
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Definition: Should contain "qcom,spmi-vadc".
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Should contain "qcom,spmi-adc5" for PMIC5 ADC driver.
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Should contain "qcom,spmi-adc-rev2" for PMIC rev2 ADC driver.
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- reg:
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Usage: required
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@ -45,13 +49,26 @@ Channel node properties:
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Definition: ADC channel number.
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See include/dt-bindings/iio/qcom,spmi-vadc.h
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- label:
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Usage: required for "qcom,spmi-adc5" and "qcom,spmi-adc-rev2"
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Value type: <empty>
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Definition: ADC input of the platform as seen in the schematics.
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For thermistor inputs connected to generic AMUX or GPIO inputs
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these can vary across platform for the same pins. Hence select
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the platform schematics name for this channel.
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- qcom,decimation:
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Usage: optional
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Value type: <u32>
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Definition: This parameter is used to decrease ADC sampling rate.
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Quicker measurements can be made by reducing decimation ratio.
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Valid values are 512, 1024, 2048, 4096.
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If property is not found, default value of 512 will be used.
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- For compatible property "qcom,spmi-vadc", valid values are
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512, 1024, 2048, 4096. If property is not found, default value
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of 512 will be used.
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- For compatible property "qcom,spmi-adc5", valid values are 250, 420
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and 840. If property is not found, default value of 840 is used.
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- For compatible property "qcom,spmi-adc-rev2", valid values are 256,
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512 and 1024. If property is not present, default value is 1024.
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- qcom,pre-scaling:
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Usage: optional
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@ -66,21 +83,38 @@ Channel node properties:
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- qcom,ratiometric:
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Usage: optional
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Value type: <empty>
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Definition: Channel calibration type. If this property is specified
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VADC will use the VDD reference (1.8V) and GND for channel
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calibration. If property is not found, channel will be
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calibrated with 0.625V and 1.25V reference channels, also
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known as absolute calibration.
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Definition: Channel calibration type.
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- For compatible property "qcom,spmi-vadc", if this property is
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specified VADC will use the VDD reference (1.8V) and GND for
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channel calibration. If property is not found, channel will be
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calibrated with 0.625V and 1.25V reference channels, also
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known as absolute calibration.
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- For compatible property "qcom,spmi-adc5" and "qcom,spmi-adc-rev2",
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if this property is specified VADC will use the VDD reference
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(1.875V) and GND for channel calibration. If property is not found,
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channel will be calibrated with 0V and 1.25V reference channels,
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also known as absolute calibration.
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- qcom,hw-settle-time:
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Usage: optional
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Value type: <u32>
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Definition: Time between AMUX getting configured and the ADC starting
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conversion. Delay = 100us * (value) for value < 11, and
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2ms * (value - 10) otherwise.
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Valid values are: 0, 100, 200, 300, 400, 500, 600, 700, 800,
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900 us and 1, 2, 4, 6, 8, 10 ms
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If property is not found, channel will use 0us.
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conversion. The 'hw_settle_time' is an index used from valid values
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and programmed in hardware to achieve the hardware settling delay.
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- For compatible property "qcom,spmi-vadc" and "qcom,spmi-adc-rev2",
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Delay = 100us * (hw_settle_time) for hw_settle_time < 11,
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and 2ms * (hw_settle_time - 10) otherwise.
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Valid values are: 0, 100, 200, 300, 400, 500, 600, 700, 800,
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900 us and 1, 2, 4, 6, 8, 10 ms.
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If property is not found, channel will use 0us.
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- For compatible property "qcom,spmi-adc5", delay = 15us for
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value 0, 100us * (value) for values < 11,
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and 2ms * (value - 10) otherwise.
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Valid values are: 15, 100, 200, 300, 400, 500, 600, 700, 800,
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900 us and 1, 2, 4, 6, 8, 10 ms
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Certain controller digital versions have valid values of
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15, 100, 200, 300, 400, 500, 600, 700, 1, 2, 4, 8, 16, 32, 64, 128 ms
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If property is not found, channel will use 15us.
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- qcom,avg-samples:
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Usage: optional
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@ -89,13 +123,18 @@ Channel node properties:
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Averaging provides the option to obtain a single measurement
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from the ADC that is an average of multiple samples. The value
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selected is 2^(value).
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Valid values are: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512
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If property is not found, 1 sample will be used.
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- For compatible property "qcom,spmi-vadc", valid values
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are: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512
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If property is not found, 1 sample will be used.
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- For compatible property "qcom,spmi-adc5" and "qcom,spmi-adc-rev2",
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valid values are: 1, 2, 4, 8, 16
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If property is not found, 1 sample will be used.
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NOTE:
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Following channels, also known as reference point channels, are used for
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result calibration and their channel configuration nodes should be defined:
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For compatible property "qcom,spmi-vadc" following channels, also known as
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reference point channels, are used for result calibration and their channel
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configuration nodes should be defined:
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VADC_REF_625MV and/or VADC_SPARE1(based on PMIC version) VADC_REF_1250MV,
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VADC_GND_REF and VADC_VDD_VADC.
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
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* Copyright (c) 2012-2014,2018 The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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@ -116,4 +116,117 @@
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#define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9
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#define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc
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/* ADC channels for SPMI PMIC5 */
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#define ADC5_REF_GND 0x00
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#define ADC5_1P25VREF 0x01
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#define ADC5_VREF_VADC 0x02
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#define ADC5_VREF_VADC5_DIV_3 0x82
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#define ADC5_VPH_PWR 0x83
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#define ADC5_VBAT_SNS 0x84
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#define ADC5_VCOIN 0x85
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#define ADC5_DIE_TEMP 0x06
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#define ADC5_USB_IN_I 0x07
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#define ADC5_USB_IN_V_16 0x08
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#define ADC5_CHG_TEMP 0x09
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#define ADC5_BAT_THERM 0x0a
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#define ADC5_BAT_ID 0x0b
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#define ADC5_XO_THERM 0x0c
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#define ADC5_AMUX_THM1 0x0d
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#define ADC5_AMUX_THM2 0x0e
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#define ADC5_AMUX_THM3 0x0f
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#define ADC5_AMUX_THM4 0x10
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#define ADC5_AMUX_THM5 0x11
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#define ADC5_GPIO1 0x12
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#define ADC5_GPIO2 0x13
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#define ADC5_GPIO3 0x14
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#define ADC5_GPIO4 0x15
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#define ADC5_GPIO5 0x16
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#define ADC5_GPIO6 0x17
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#define ADC5_GPIO7 0x18
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#define ADC5_SBUx 0x99
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#define ADC5_MID_CHG_DIV6 0x1e
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#define ADC5_OFF 0xff
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/* 30k pull-up1 */
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#define ADC5_BAT_THERM_30K_PU 0x2a
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#define ADC5_BAT_ID_30K_PU 0x2b
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#define ADC5_XO_THERM_30K_PU 0x2c
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#define ADC5_AMUX_THM1_30K_PU 0x2d
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#define ADC5_AMUX_THM2_30K_PU 0x2e
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#define ADC5_AMUX_THM3_30K_PU 0x2f
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#define ADC5_AMUX_THM4_30K_PU 0x30
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#define ADC5_AMUX_THM5_30K_PU 0x31
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#define ADC5_GPIO1_30K_PU 0x32
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#define ADC5_GPIO2_30K_PU 0x33
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#define ADC5_GPIO3_30K_PU 0x34
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#define ADC5_GPIO4_30K_PU 0x35
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#define ADC5_GPIO5_30K_PU 0x36
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#define ADC5_GPIO6_30K_PU 0x37
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#define ADC5_GPIO7_30K_PU 0x38
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#define ADC5_SBUx_30K_PU 0x39
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/* 100k pull-up2 */
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#define ADC5_BAT_THERM_100K_PU 0x4a
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#define ADC5_BAT_ID_100K_PU 0x4b
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#define ADC5_XO_THERM_100K_PU 0x4c
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#define ADC5_AMUX_THM1_100K_PU 0x4d
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#define ADC5_AMUX_THM2_100K_PU 0x4e
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#define ADC5_AMUX_THM3_100K_PU 0x4f
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#define ADC5_AMUX_THM4_100K_PU 0x50
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#define ADC5_AMUX_THM5_100K_PU 0x51
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#define ADC5_GPIO1_100K_PU 0x52
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#define ADC5_GPIO2_100K_PU 0x53
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#define ADC5_GPIO3_100K_PU 0x54
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#define ADC5_GPIO4_100K_PU 0x55
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#define ADC5_GPIO5_100K_PU 0x56
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#define ADC5_GPIO6_100K_PU 0x57
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#define ADC5_GPIO7_100K_PU 0x58
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#define ADC5_SBUx_100K_PU 0x59
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/* 400k pull-up3 */
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#define ADC5_BAT_THERM_400K_PU 0x6a
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#define ADC5_BAT_ID_400K_PU 0x6b
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#define ADC5_XO_THERM_400K_PU 0x6c
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#define ADC5_AMUX_THM1_400K_PU 0x6d
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#define ADC5_AMUX_THM2_400K_PU 0x6e
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#define ADC5_AMUX_THM3_400K_PU 0x6f
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#define ADC5_AMUX_THM4_400K_PU 0x70
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#define ADC5_AMUX_THM5_400K_PU 0x71
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#define ADC5_GPIO1_400K_PU 0x72
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#define ADC5_GPIO2_400K_PU 0x73
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#define ADC5_GPIO3_400K_PU 0x74
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#define ADC5_GPIO4_400K_PU 0x75
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#define ADC5_GPIO5_400K_PU 0x76
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#define ADC5_GPIO6_400K_PU 0x77
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#define ADC5_GPIO7_400K_PU 0x78
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#define ADC5_SBUx_400K_PU 0x79
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/* 1/3 Divider */
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#define ADC5_GPIO1_DIV3 0x92
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#define ADC5_GPIO2_DIV3 0x93
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#define ADC5_GPIO3_DIV3 0x94
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#define ADC5_GPIO4_DIV3 0x95
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#define ADC5_GPIO5_DIV3 0x96
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#define ADC5_GPIO6_DIV3 0x97
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#define ADC5_GPIO7_DIV3 0x98
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#define ADC5_SBUx_DIV3 0x99
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/* Current and combined current/voltage channels */
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#define ADC5_INT_EXT_ISENSE 0xa1
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#define ADC5_PARALLEL_ISENSE 0xa5
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#define ADC5_CUR_REPLICA_VDS 0xa7
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#define ADC5_CUR_SENS_BATFET_VDS_OFFSET 0xa9
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#define ADC5_CUR_SENS_REPLICA_VDS_OFFSET 0xab
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#define ADC5_EXT_SENS_OFFSET 0xad
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#define ADC5_INT_EXT_ISENSE_VBAT_VDATA 0xb0
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#define ADC5_INT_EXT_ISENSE_VBAT_IDATA 0xb1
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#define ADC5_EXT_ISENSE_VBAT_VDATA 0xb2
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#define ADC5_EXT_ISENSE_VBAT_IDATA 0xb3
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#define ADC5_PARALLEL_ISENSE_VBAT_VDATA 0xb4
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#define ADC5_PARALLEL_ISENSE_VBAT_IDATA 0xb5
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#define ADC5_MAX_CHANNEL 0xc0
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#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */
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