forked from luck/tmp_suning_uos_patched
[POWERPC] cell: use ppc_md->power_save instead of cbe_idle_loop
This moves the cell idle function to use the default cpu_idle with a special power_save callback, like all other platforms except iSeries already do. It also makes it possible to disable this power_save function with a new powerpc-specific boot option "powersave=off". Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
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b3d7dc1967
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302eca184f
@ -39,6 +39,13 @@
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#define cpu_should_die() 0
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#define cpu_should_die() 0
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#endif
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#endif
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static int __init powersave_off(char *arg)
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{
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ppc_md.power_save = NULL;
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return 0;
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}
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__setup("powersave=off", powersave_off);
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/*
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/*
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* The body of the idle task.
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* The body of the idle task.
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*/
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*/
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@ -38,32 +38,16 @@
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#include "pervasive.h"
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#include "pervasive.h"
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#include "cbe_regs.h"
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#include "cbe_regs.h"
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static DEFINE_SPINLOCK(cbe_pervasive_lock);
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static void cbe_power_save(void)
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static void __init cbe_enable_pause_zero(void)
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{
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{
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unsigned long thread_switch_control;
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unsigned long ctrl, thread_switch_control;
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unsigned long temp_register;
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ctrl = mfspr(SPRN_CTRLF);
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struct cbe_pmd_regs __iomem *pregs;
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spin_lock_irq(&cbe_pervasive_lock);
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pregs = cbe_get_cpu_pmd_regs(smp_processor_id());
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if (pregs == NULL)
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goto out;
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pr_debug("Power Management: CPU %d\n", smp_processor_id());
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/* Enable Pause(0) control bit */
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temp_register = in_be64(&pregs->pmcr);
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out_be64(&pregs->pmcr,
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temp_register | CBE_PMD_PAUSE_ZERO_CONTROL);
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/* Enable DEC and EE interrupt request */
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/* Enable DEC and EE interrupt request */
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thread_switch_control = mfspr(SPRN_TSC_CELL);
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thread_switch_control = mfspr(SPRN_TSC_CELL);
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thread_switch_control |= TSC_CELL_EE_ENABLE | TSC_CELL_EE_BOOST;
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thread_switch_control |= TSC_CELL_EE_ENABLE | TSC_CELL_EE_BOOST;
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switch ((mfspr(SPRN_CTRLF) & CTRL_CT)) {
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switch (ctrl & CTRL_CT) {
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case CTRL_CT0:
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case CTRL_CT0:
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thread_switch_control |= TSC_CELL_DEC_ENABLE_0;
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thread_switch_control |= TSC_CELL_DEC_ENABLE_0;
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break;
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break;
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@ -75,58 +59,21 @@ static void __init cbe_enable_pause_zero(void)
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__FUNCTION__);
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__FUNCTION__);
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break;
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break;
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}
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}
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mtspr(SPRN_TSC_CELL, thread_switch_control);
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mtspr(SPRN_TSC_CELL, thread_switch_control);
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out:
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/*
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spin_unlock_irq(&cbe_pervasive_lock);
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* go into low thread priority, medium priority will be
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}
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* restored for us after wake-up.
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static void cbe_idle(void)
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{
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unsigned long ctrl;
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/* Why do we do that on every idle ? Couldn't that be done once for
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* all or do we lose the state some way ? Also, the pmcr
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* register setting, that can't be set once at boot ? We really want
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* to move that away in order to implement a simple powersave
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*/
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*/
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cbe_enable_pause_zero();
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HMT_low();
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while (1) {
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/*
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if (!need_resched()) {
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* atomically disable thread execution and runlatch.
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local_irq_disable();
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* External and Decrementer exceptions are still handled when the
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while (!need_resched()) {
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* thread is disabled but now enter in cbe_system_reset_exception()
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/* go into low thread priority */
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*/
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HMT_low();
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ctrl &= ~(CTRL_RUNLATCH | CTRL_TE);
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mtspr(SPRN_CTRLT, ctrl);
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/*
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* atomically disable thread execution
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* and runlatch.
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* External and Decrementer exceptions
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* are still handled when the thread
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* is disabled but now enter in
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* cbe_system_reset_exception()
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*/
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ctrl = mfspr(SPRN_CTRLF);
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ctrl &= ~(CTRL_RUNLATCH | CTRL_TE);
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mtspr(SPRN_CTRLT, ctrl);
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}
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/* restore thread prio */
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HMT_medium();
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local_irq_enable();
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}
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/*
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* turn runlatch on again before scheduling the
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* process we just woke up
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*/
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ppc64_runlatch_on();
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preempt_enable_no_resched();
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schedule();
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preempt_disable();
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}
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}
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}
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static int cbe_system_reset_exception(struct pt_regs *regs)
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static int cbe_system_reset_exception(struct pt_regs *regs)
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@ -158,9 +105,20 @@ static int cbe_system_reset_exception(struct pt_regs *regs)
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void __init cbe_pervasive_init(void)
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void __init cbe_pervasive_init(void)
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{
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{
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int cpu;
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if (!cpu_has_feature(CPU_FTR_PAUSE_ZERO))
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if (!cpu_has_feature(CPU_FTR_PAUSE_ZERO))
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return;
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return;
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ppc_md.idle_loop = cbe_idle;
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for_each_possible_cpu(cpu) {
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struct cbe_pmd_regs __iomem *regs = cbe_get_cpu_pmd_regs(cpu);
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if (!regs)
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continue;
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/* Enable Pause(0) control bit */
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out_be64(®s->pmcr, in_be64(®s->pmcr) |
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CBE_PMD_PAUSE_ZERO_CONTROL);
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}
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ppc_md.power_save = cbe_power_save;
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ppc_md.system_reset_exception = cbe_system_reset_exception;
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ppc_md.system_reset_exception = cbe_system_reset_exception;
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}
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}
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