forked from luck/tmp_suning_uos_patched
Merge branch 'pci/enumeration'
- add decoding for 16 GT/s link speed (Jay Fang)
- add interfaces to get max link speed and width (Tal Gilboa)
- add pcie_bandwidth_capable() to compute max supported link bandwidth
(Tal Gilboa)
- add pcie_bandwidth_available() to compute bandwidth available to device
(Tal Gilboa)
- add pcie_print_link_status() to log link speed and whether it's limited
(Tal Gilboa)
- use PCI core interfaces to report when device performance may be
limited by its slot instead of doing it in each driver (Tal Gilboa)
* pci/enumeration:
fm10k: Report PCIe link properties with pcie_print_link_status()
net/mlx5e: Use pcie_bandwidth_available() to compute bandwidth
net/mlx5: Report PCIe link properties with pcie_print_link_status()
net/mlx4_core: Report PCIe link properties with pcie_print_link_status()
PCI: Add pcie_print_link_status() to log link speed and whether it's limited
PCI: Add pcie_bandwidth_available() to compute bandwidth available to device
PCI: Add pcie_bandwidth_capable() to compute max supported link bandwidth
PCI: Add pcie_get_width_cap() to find max supported link width
PCI: Add pcie_get_speed_cap() to find max supported link speed
PCI: Add decoding for 16 GT/s link speed
This commit is contained in:
Bjorn Helgaas
Bjorn Helgaas
commit
315271b0ff
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@ -2120,91 +2120,6 @@ static int fm10k_sw_init(struct fm10k_intfc *interface,
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return 0;
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}
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static void fm10k_slot_warn(struct fm10k_intfc *interface)
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{
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enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
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enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
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struct fm10k_hw *hw = &interface->hw;
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int max_gts = 0, expected_gts = 0;
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if (pcie_get_minimum_link(interface->pdev, &speed, &width) ||
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speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
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dev_warn(&interface->pdev->dev,
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"Unable to determine PCI Express bandwidth.\n");
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return;
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}
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switch (speed) {
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case PCIE_SPEED_2_5GT:
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/* 8b/10b encoding reduces max throughput by 20% */
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max_gts = 2 * width;
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break;
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case PCIE_SPEED_5_0GT:
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/* 8b/10b encoding reduces max throughput by 20% */
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max_gts = 4 * width;
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break;
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case PCIE_SPEED_8_0GT:
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/* 128b/130b encoding has less than 2% impact on throughput */
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max_gts = 8 * width;
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break;
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default:
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dev_warn(&interface->pdev->dev,
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"Unable to determine PCI Express bandwidth.\n");
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return;
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}
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dev_info(&interface->pdev->dev,
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"PCI Express bandwidth of %dGT/s available\n",
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max_gts);
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dev_info(&interface->pdev->dev,
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"(Speed:%s, Width: x%d, Encoding Loss:%s, Payload:%s)\n",
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(speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
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speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
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speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
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"Unknown"),
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hw->bus.width,
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(speed == PCIE_SPEED_2_5GT ? "20%" :
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speed == PCIE_SPEED_5_0GT ? "20%" :
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speed == PCIE_SPEED_8_0GT ? "<2%" :
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"Unknown"),
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(hw->bus.payload == fm10k_bus_payload_128 ? "128B" :
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hw->bus.payload == fm10k_bus_payload_256 ? "256B" :
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hw->bus.payload == fm10k_bus_payload_512 ? "512B" :
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"Unknown"));
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switch (hw->bus_caps.speed) {
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case fm10k_bus_speed_2500:
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/* 8b/10b encoding reduces max throughput by 20% */
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expected_gts = 2 * hw->bus_caps.width;
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break;
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case fm10k_bus_speed_5000:
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/* 8b/10b encoding reduces max throughput by 20% */
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expected_gts = 4 * hw->bus_caps.width;
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break;
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case fm10k_bus_speed_8000:
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/* 128b/130b encoding has less than 2% impact on throughput */
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expected_gts = 8 * hw->bus_caps.width;
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break;
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default:
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dev_warn(&interface->pdev->dev,
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"Unable to determine expected PCI Express bandwidth.\n");
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return;
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}
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if (max_gts >= expected_gts)
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return;
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dev_warn(&interface->pdev->dev,
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"This device requires %dGT/s of bandwidth for optimal performance.\n",
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expected_gts);
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dev_warn(&interface->pdev->dev,
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"A %sslot with x%d lanes is suggested.\n",
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(hw->bus_caps.speed == fm10k_bus_speed_2500 ? "2.5GT/s " :
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hw->bus_caps.speed == fm10k_bus_speed_5000 ? "5.0GT/s " :
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hw->bus_caps.speed == fm10k_bus_speed_8000 ? "8.0GT/s " : ""),
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hw->bus_caps.width);
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}
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/**
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* fm10k_probe - Device Initialization Routine
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* @pdev: PCI device information struct
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@ -2326,7 +2241,7 @@ static int fm10k_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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mod_timer(&interface->service_timer, (HZ * 2) + jiffies);
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/* print warning for non-optimal configurations */
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fm10k_slot_warn(interface);
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pcie_print_link_status(interface->pdev);
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/* report MAC address for logging */
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dev_info(&pdev->dev, "%pM\n", netdev->dev_addr);
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@ -623,85 +623,6 @@ static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
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return 0;
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}
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static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
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enum pci_bus_speed *speed,
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enum pcie_link_width *width)
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{
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u32 lnkcap1, lnkcap2;
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int err1, err2;
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#define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
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*speed = PCI_SPEED_UNKNOWN;
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*width = PCIE_LNK_WIDTH_UNKNOWN;
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err1 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP,
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&lnkcap1);
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err2 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP2,
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&lnkcap2);
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if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
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if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
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*speed = PCIE_SPEED_8_0GT;
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else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
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*speed = PCIE_SPEED_5_0GT;
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else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
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*speed = PCIE_SPEED_2_5GT;
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}
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if (!err1) {
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*width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
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if (!lnkcap2) { /* pre-r3.0 */
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if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
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*speed = PCIE_SPEED_5_0GT;
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else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
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*speed = PCIE_SPEED_2_5GT;
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}
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}
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if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
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return err1 ? err1 :
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err2 ? err2 : -EINVAL;
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}
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return 0;
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}
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static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
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{
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enum pcie_link_width width, width_cap;
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enum pci_bus_speed speed, speed_cap;
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int err;
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#define PCIE_SPEED_STR(speed) \
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(speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
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speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
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speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
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"Unknown")
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err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
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if (err) {
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mlx4_warn(dev,
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"Unable to determine PCIe device BW capabilities\n");
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return;
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}
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err = pcie_get_minimum_link(dev->persist->pdev, &speed, &width);
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if (err || speed == PCI_SPEED_UNKNOWN ||
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width == PCIE_LNK_WIDTH_UNKNOWN) {
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mlx4_warn(dev,
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"Unable to determine PCI device chain minimum BW\n");
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return;
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}
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if (width != width_cap || speed != speed_cap)
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mlx4_warn(dev,
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"PCIe BW is different than device's capability\n");
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mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
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PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
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mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
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width, width_cap);
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return;
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}
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/*The function checks if there are live vf, return the num of them*/
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static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
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{
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@ -3475,7 +3396,7 @@ static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data,
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* express device capabilities are under-satisfied by the bus.
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*/
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if (!mlx4_is_slave(dev))
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mlx4_check_pcie_caps(dev);
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pcie_print_link_status(dev->persist->pdev);
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/* In master functions, the communication channel must be initialized
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* after obtaining its address from fw */
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@ -3864,36 +3864,6 @@ void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
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indirection_rqt[i] = i % num_channels;
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}
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static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
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{
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enum pcie_link_width width;
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enum pci_bus_speed speed;
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int err = 0;
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err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
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if (err)
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return err;
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if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
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return -EINVAL;
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switch (speed) {
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case PCIE_SPEED_2_5GT:
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*pci_bw = 2500 * width;
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break;
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case PCIE_SPEED_5_0GT:
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*pci_bw = 5000 * width;
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break;
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case PCIE_SPEED_8_0GT:
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*pci_bw = 8000 * width;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
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{
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return (link_speed && pci_bw &&
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@ -3979,7 +3949,7 @@ void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
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params->num_tc = 1;
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mlx5e_get_max_linkspeed(mdev, &link_speed);
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mlx5e_get_pci_bw(mdev, &pci_bw);
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pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
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mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
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link_speed, pci_bw);
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@ -1043,6 +1043,10 @@ static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
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dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
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fw_rev_min(dev), fw_rev_sub(dev));
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/* Only PFs hold the relevant PCIe information for this query */
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if (mlx5_core_is_pf(dev))
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pcie_print_link_status(dev->pdev);
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/* on load removing any previous indication of internal error, device is
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* up
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*/
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@ -158,45 +158,18 @@ static DEVICE_ATTR_RO(resource);
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static ssize_t max_link_speed_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct pci_dev *pci_dev = to_pci_dev(dev);
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u32 linkcap;
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int err;
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const char *speed;
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struct pci_dev *pdev = to_pci_dev(dev);
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err = pcie_capability_read_dword(pci_dev, PCI_EXP_LNKCAP, &linkcap);
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if (err)
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return -EINVAL;
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switch (linkcap & PCI_EXP_LNKCAP_SLS) {
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case PCI_EXP_LNKCAP_SLS_8_0GB:
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speed = "8 GT/s";
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break;
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case PCI_EXP_LNKCAP_SLS_5_0GB:
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speed = "5 GT/s";
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break;
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case PCI_EXP_LNKCAP_SLS_2_5GB:
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speed = "2.5 GT/s";
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break;
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default:
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speed = "Unknown speed";
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}
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return sprintf(buf, "%s\n", speed);
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return sprintf(buf, "%s\n", PCIE_SPEED2STR(pcie_get_speed_cap(pdev)));
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}
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static DEVICE_ATTR_RO(max_link_speed);
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static ssize_t max_link_width_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct pci_dev *pci_dev = to_pci_dev(dev);
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u32 linkcap;
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int err;
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struct pci_dev *pdev = to_pci_dev(dev);
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err = pcie_capability_read_dword(pci_dev, PCI_EXP_LNKCAP, &linkcap);
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if (err)
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return -EINVAL;
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return sprintf(buf, "%u\n", (linkcap & PCI_EXP_LNKCAP_MLW) >> 4);
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return sprintf(buf, "%u\n", pcie_get_width_cap(pdev));
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}
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static DEVICE_ATTR_RO(max_link_width);
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@ -213,6 +186,9 @@ static ssize_t current_link_speed_show(struct device *dev,
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return -EINVAL;
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switch (linkstat & PCI_EXP_LNKSTA_CLS) {
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case PCI_EXP_LNKSTA_CLS_16_0GB:
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speed = "16 GT/s";
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break;
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case PCI_EXP_LNKSTA_CLS_8_0GB:
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speed = "8 GT/s";
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break;
|
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|
|
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|
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@ -5146,6 +5146,180 @@ int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
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}
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EXPORT_SYMBOL(pcie_get_minimum_link);
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|
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/**
|
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* pcie_bandwidth_available - determine minimum link settings of a PCIe
|
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* device and its bandwidth limitation
|
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* @dev: PCI device to query
|
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* @limiting_dev: storage for device causing the bandwidth limitation
|
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* @speed: storage for speed of limiting device
|
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* @width: storage for width of limiting device
|
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*
|
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* Walk up the PCI device chain and find the point where the minimum
|
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* bandwidth is available. Return the bandwidth available there and (if
|
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* limiting_dev, speed, and width pointers are supplied) information about
|
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* that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
|
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* raw bandwidth.
|
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*/
|
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u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
|
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enum pci_bus_speed *speed,
|
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enum pcie_link_width *width)
|
||||
{
|
||||
u16 lnksta;
|
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enum pci_bus_speed next_speed;
|
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enum pcie_link_width next_width;
|
||||
u32 bw, next_bw;
|
||||
|
||||
if (speed)
|
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*speed = PCI_SPEED_UNKNOWN;
|
||||
if (width)
|
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*width = PCIE_LNK_WIDTH_UNKNOWN;
|
||||
|
||||
bw = 0;
|
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|
||||
while (dev) {
|
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pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
|
||||
|
||||
next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
|
||||
next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
|
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PCI_EXP_LNKSTA_NLW_SHIFT;
|
||||
|
||||
next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
|
||||
|
||||
/* Check if current device limits the total bandwidth */
|
||||
if (!bw || next_bw <= bw) {
|
||||
bw = next_bw;
|
||||
|
||||
if (limiting_dev)
|
||||
*limiting_dev = dev;
|
||||
if (speed)
|
||||
*speed = next_speed;
|
||||
if (width)
|
||||
*width = next_width;
|
||||
}
|
||||
|
||||
dev = pci_upstream_bridge(dev);
|
||||
}
|
||||
|
||||
return bw;
|
||||
}
|
||||
EXPORT_SYMBOL(pcie_bandwidth_available);
|
||||
|
||||
/**
|
||||
* pcie_get_speed_cap - query for the PCI device's link speed capability
|
||||
* @dev: PCI device to query
|
||||
*
|
||||
* Query the PCI device speed capability. Return the maximum link speed
|
||||
* supported by the device.
|
||||
*/
|
||||
enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
|
||||
{
|
||||
u32 lnkcap2, lnkcap;
|
||||
|
||||
/*
|
||||
* PCIe r4.0 sec 7.5.3.18 recommends using the Supported Link
|
||||
* Speeds Vector in Link Capabilities 2 when supported, falling
|
||||
* back to Max Link Speed in Link Capabilities otherwise.
|
||||
*/
|
||||
pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
|
||||
if (lnkcap2) { /* PCIe r3.0-compliant */
|
||||
if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
|
||||
return PCIE_SPEED_16_0GT;
|
||||
else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
|
||||
return PCIE_SPEED_8_0GT;
|
||||
else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
|
||||
return PCIE_SPEED_5_0GT;
|
||||
else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
|
||||
return PCIE_SPEED_2_5GT;
|
||||
return PCI_SPEED_UNKNOWN;
|
||||
}
|
||||
|
||||
pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
|
||||
if (lnkcap) {
|
||||
if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB)
|
||||
return PCIE_SPEED_16_0GT;
|
||||
else if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB)
|
||||
return PCIE_SPEED_8_0GT;
|
||||
else if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB)
|
||||
return PCIE_SPEED_5_0GT;
|
||||
else if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB)
|
||||
return PCIE_SPEED_2_5GT;
|
||||
}
|
||||
|
||||
return PCI_SPEED_UNKNOWN;
|
||||
}
|
||||
|
||||
/**
|
||||
* pcie_get_width_cap - query for the PCI device's link width capability
|
||||
* @dev: PCI device to query
|
||||
*
|
||||
* Query the PCI device width capability. Return the maximum link width
|
||||
* supported by the device.
|
||||
*/
|
||||
enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
|
||||
{
|
||||
u32 lnkcap;
|
||||
|
||||
pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
|
||||
if (lnkcap)
|
||||
return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
|
||||
|
||||
return PCIE_LNK_WIDTH_UNKNOWN;
|
||||
}
|
||||
|
||||
/**
|
||||
* pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
|
||||
* @dev: PCI device
|
||||
* @speed: storage for link speed
|
||||
* @width: storage for link width
|
||||
*
|
||||
* Calculate a PCI device's link bandwidth by querying for its link speed
|
||||
* and width, multiplying them, and applying encoding overhead. The result
|
||||
* is in Mb/s, i.e., megabits/second of raw bandwidth.
|
||||
*/
|
||||
u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
|
||||
enum pcie_link_width *width)
|
||||
{
|
||||
*speed = pcie_get_speed_cap(dev);
|
||||
*width = pcie_get_width_cap(dev);
|
||||
|
||||
if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
|
||||
return 0;
|
||||
|
||||
return *width * PCIE_SPEED2MBS_ENC(*speed);
|
||||
}
|
||||
|
||||
/**
|
||||
* pcie_print_link_status - Report the PCI device's link speed and width
|
||||
* @dev: PCI device to query
|
||||
*
|
||||
* Report the available bandwidth at the device. If this is less than the
|
||||
* device is capable of, report the device's maximum possible bandwidth and
|
||||
* the upstream link that limits its performance to less than that.
|
||||
*/
|
||||
void pcie_print_link_status(struct pci_dev *dev)
|
||||
{
|
||||
enum pcie_link_width width, width_cap;
|
||||
enum pci_bus_speed speed, speed_cap;
|
||||
struct pci_dev *limiting_dev = NULL;
|
||||
u32 bw_avail, bw_cap;
|
||||
|
||||
bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
|
||||
bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
|
||||
|
||||
if (bw_avail >= bw_cap)
|
||||
pci_info(dev, "%u.%03u Gb/s available bandwidth (%s x%d link)\n",
|
||||
bw_cap / 1000, bw_cap % 1000,
|
||||
PCIE_SPEED2STR(speed_cap), width_cap);
|
||||
else
|
||||
pci_info(dev, "%u.%03u Gb/s available bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
|
||||
bw_avail / 1000, bw_avail % 1000,
|
||||
PCIE_SPEED2STR(speed), width,
|
||||
limiting_dev ? pci_name(limiting_dev) : "<unknown>",
|
||||
bw_cap / 1000, bw_cap % 1000,
|
||||
PCIE_SPEED2STR(speed_cap), width_cap);
|
||||
}
|
||||
EXPORT_SYMBOL(pcie_print_link_status);
|
||||
|
||||
/**
|
||||
* pci_select_bars - Make BAR mask from the type of resource
|
||||
* @dev: the PCI device for which BAR mask is made
|
||||
|
|
|
|||
|
|
@ -253,6 +253,27 @@ bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
|
|||
void pci_reassigndev_resource_alignment(struct pci_dev *dev);
|
||||
void pci_disable_bridge_window(struct pci_dev *dev);
|
||||
|
||||
/* PCIe link information */
|
||||
#define PCIE_SPEED2STR(speed) \
|
||||
((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \
|
||||
(speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \
|
||||
(speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \
|
||||
(speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \
|
||||
"Unknown speed")
|
||||
|
||||
/* PCIe speed to Mb/s reduced by encoding overhead */
|
||||
#define PCIE_SPEED2MBS_ENC(speed) \
|
||||
((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
|
||||
(speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
|
||||
(speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
|
||||
(speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
|
||||
0)
|
||||
|
||||
enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
|
||||
enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
|
||||
u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
|
||||
enum pcie_link_width *width);
|
||||
|
||||
/* Single Root I/O Virtualization */
|
||||
struct pci_sriov {
|
||||
int pos; /* Capability position */
|
||||
|
|
|
|||
|
|
@ -592,7 +592,7 @@ const unsigned char pcie_link_speed[] = {
|
|||
PCIE_SPEED_2_5GT, /* 1 */
|
||||
PCIE_SPEED_5_0GT, /* 2 */
|
||||
PCIE_SPEED_8_0GT, /* 3 */
|
||||
PCI_SPEED_UNKNOWN, /* 4 */
|
||||
PCIE_SPEED_16_0GT, /* 4 */
|
||||
PCI_SPEED_UNKNOWN, /* 5 */
|
||||
PCI_SPEED_UNKNOWN, /* 6 */
|
||||
PCI_SPEED_UNKNOWN, /* 7 */
|
||||
|
|
|
|||
|
|
@ -76,6 +76,7 @@ static const char *pci_bus_speed_strings[] = {
|
|||
"2.5 GT/s PCIe", /* 0x14 */
|
||||
"5.0 GT/s PCIe", /* 0x15 */
|
||||
"8.0 GT/s PCIe", /* 0x16 */
|
||||
"16.0 GT/s PCIe", /* 0x17 */
|
||||
};
|
||||
|
||||
static ssize_t bus_speed_read(enum pci_bus_speed speed, char *buf)
|
||||
|
|
|
|||
|
|
@ -256,6 +256,7 @@ enum pci_bus_speed {
|
|||
PCIE_SPEED_2_5GT = 0x14,
|
||||
PCIE_SPEED_5_0GT = 0x15,
|
||||
PCIE_SPEED_8_0GT = 0x16,
|
||||
PCIE_SPEED_16_0GT = 0x17,
|
||||
PCI_SPEED_UNKNOWN = 0xff,
|
||||
};
|
||||
|
||||
|
|
@ -1077,6 +1078,10 @@ int pcie_get_mps(struct pci_dev *dev);
|
|||
int pcie_set_mps(struct pci_dev *dev, int mps);
|
||||
int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
|
||||
enum pcie_link_width *width);
|
||||
u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
|
||||
enum pci_bus_speed *speed,
|
||||
enum pcie_link_width *width);
|
||||
void pcie_print_link_status(struct pci_dev *dev);
|
||||
void pcie_flr(struct pci_dev *dev);
|
||||
int __pci_reset_function_locked(struct pci_dev *dev);
|
||||
int pci_reset_function(struct pci_dev *dev);
|
||||
|
|
|
|||
|
|
@ -520,6 +520,7 @@
|
|||
#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */
|
||||
#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */
|
||||
#define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */
|
||||
#define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */
|
||||
#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
|
||||
#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */
|
||||
#define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */
|
||||
|
|
@ -547,6 +548,7 @@
|
|||
#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
|
||||
#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
|
||||
#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
|
||||
#define PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */
|
||||
#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */
|
||||
#define PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */
|
||||
#define PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */
|
||||
|
|
@ -648,8 +650,9 @@
|
|||
#define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints without link end here */
|
||||
#define PCI_EXP_LNKCAP2 44 /* Link Capabilities 2 */
|
||||
#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 /* Supported Speed 2.5GT/s */
|
||||
#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5.0GT/s */
|
||||
#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8.0GT/s */
|
||||
#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5GT/s */
|
||||
#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */
|
||||
#define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */
|
||||
#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */
|
||||
#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
|
||||
#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user