forked from luck/tmp_suning_uos_patched
bnx2x: Minor code improvements
Minor code improvements Small changes to make the code a little bit more efficient and mostly more readable: - Using unified macros for EMAC_RD/WR which looks like normal REG_RD/WR - Removing the NIG_WR since it did nothing and was only confusing - On bnx2x_panic_dump, print only the used parts of the rings - define parameters only on the branch they are needed and not at the beginning of the function - using NETIF_MSG_INTR and not private BNX2X_MSG_SP for debug prints Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Eilon Greenstein
David S. Miller
parent
f0e53a847a
commit
3196a88a85
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@ -121,16 +121,7 @@
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#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
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#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
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#define NIG_WR(reg, val) REG_WR(bp, reg, val)
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#define EMAC_WR(reg, val) REG_WR(bp, emac_base + reg, val)
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#define BMAC_WR(reg, val) REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val)
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#define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)
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#define for_each_nondefault_queue(bp, var) \
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for (var = 1; var < bp->num_queues; var++)
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#define is_multi(bp) (bp->num_queues > 1)
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#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
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/* fast path */
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@ -815,9 +806,6 @@ struct bnx2x {
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#define BP_FUNC(bp) (bp->func)
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#define BP_E1HVN(bp) (bp->func >> 1)
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#define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
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/* assorted E1HVN */
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#define IS_E1HMF(bp) (bp->e1hmf != 0)
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#define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16)
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int pm_cap;
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int pcie_cap;
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@ -842,6 +830,7 @@ struct bnx2x {
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u32 mf_config;
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u16 e1hov;
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u8 e1hmf;
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#define IS_E1HMF(bp) (bp->e1hmf != 0)
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u8 wol;
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@ -872,6 +861,7 @@ struct bnx2x {
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#define BNX2X_STATE_ERROR 0xf000
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int num_queues;
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#define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16)
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u32 rx_mode;
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#define BNX2X_RX_MODE_NONE 0
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@ -922,6 +912,13 @@ struct bnx2x {
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};
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#define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)
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#define for_each_nondefault_queue(bp, var) \
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for (var = 1; var < bp->num_queues; var++)
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#define is_multi(bp) (bp->num_queues > 1)
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void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
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void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
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u32 len32);
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@ -31,7 +31,7 @@
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/********************************************************/
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#define SUPPORT_CL73 0 /* Currently no */
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#define ETH_HLEN 14
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#define ETH_HLEN 14
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#define ETH_OVREHEAD (ETH_HLEN + 8)/* 8 for CRC + VLAN*/
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#define ETH_MIN_PACKET_SIZE 60
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#define ETH_MAX_PACKET_SIZE 1500
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@ -40,7 +40,7 @@
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#define BMAC_CONTROL_RX_ENABLE 2
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/***********************************************************/
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/* Shortcut definitions */
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/* Shortcut definitions */
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/***********************************************************/
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#define NIG_STATUS_XGXS0_LINK10G \
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@ -79,12 +79,12 @@
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#define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
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#define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
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#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
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#define AUTONEG_PARALLEL \
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#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
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#define AUTONEG_PARALLEL \
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SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
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#define AUTONEG_SGMII_FIBER_AUTODET \
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#define AUTONEG_SGMII_FIBER_AUTODET \
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SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
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#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
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#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
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#define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
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MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
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@ -201,11 +201,10 @@ static void bnx2x_emac_init(struct link_params *params,
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/* init emac - use read-modify-write */
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/* self clear reset */
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val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
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EMAC_WR(EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
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EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
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timeout = 200;
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do
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{
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do {
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val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
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DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
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if (!timeout) {
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@ -213,18 +212,18 @@ static void bnx2x_emac_init(struct link_params *params,
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return;
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}
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timeout--;
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}while (val & EMAC_MODE_RESET);
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} while (val & EMAC_MODE_RESET);
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/* Set mac address */
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val = ((params->mac_addr[0] << 8) |
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params->mac_addr[1]);
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EMAC_WR(EMAC_REG_EMAC_MAC_MATCH, val);
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EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
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val = ((params->mac_addr[2] << 24) |
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(params->mac_addr[3] << 16) |
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(params->mac_addr[4] << 8) |
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params->mac_addr[5]);
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EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + 4, val);
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EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
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}
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static u8 bnx2x_emac_enable(struct link_params *params,
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@ -285,7 +284,7 @@ static u8 bnx2x_emac_enable(struct link_params *params,
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if (CHIP_REV_IS_SLOW(bp)) {
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/* config GMII mode */
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val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
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EMAC_WR(EMAC_REG_EMAC_MODE,
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EMAC_WR(bp, EMAC_REG_EMAC_MODE,
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(val | EMAC_MODE_PORT_GMII));
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} else { /* ASIC */
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/* pause enable/disable */
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@ -309,7 +308,7 @@ static u8 bnx2x_emac_enable(struct link_params *params,
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/* KEEP_VLAN_TAG, promiscuous */
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val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
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val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
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EMAC_WR(EMAC_REG_EMAC_RX_MODE, val);
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EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
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/* Set Loopback */
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val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
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@ -317,10 +316,10 @@ static u8 bnx2x_emac_enable(struct link_params *params,
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val |= 0x810;
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else
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val &= ~0x810;
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EMAC_WR(EMAC_REG_EMAC_MODE, val);
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EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
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/* enable emac for jumbo packets */
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EMAC_WR(EMAC_REG_EMAC_RX_MTU_SIZE,
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EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
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(EMAC_RX_MTU_SIZE_JUMBO_ENA |
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(ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
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@ -646,7 +645,7 @@ static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
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u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
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NIG_REG_INGRESS_BMAC0_MEM;
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u32 wb_data[2];
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u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
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u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
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/* Only if the bmac is out of reset */
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if (REG_RD(bp, MISC_REG_RESET_REG_2) &
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@ -1036,7 +1035,7 @@ static void bnx2x_set_swap_lanes(struct link_params *params)
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}
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static void bnx2x_set_parallel_detection(struct link_params *params,
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u8 phy_flags)
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u8 phy_flags)
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{
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struct bnx2x *bp = params->bp;
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u16 control2;
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@ -1489,8 +1488,8 @@ static u8 bnx2x_ext_phy_resove_fc(struct link_params *params,
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{
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struct bnx2x *bp = params->bp;
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u8 ext_phy_addr;
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u16 ld_pause; /* local */
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u16 lp_pause; /* link partner */
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u16 ld_pause; /* local */
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u16 lp_pause; /* link partner */
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u16 an_complete; /* AN complete */
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u16 pause_result;
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u8 ret = 0;
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@ -1565,8 +1564,8 @@ static void bnx2x_flow_ctrl_resolve(struct link_params *params,
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u32 gp_status)
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{
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struct bnx2x *bp = params->bp;
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u16 ld_pause; /* local driver */
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u16 lp_pause; /* link partner */
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u16 ld_pause; /* local driver */
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u16 lp_pause; /* link partner */
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u16 pause_result;
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vars->flow_ctrl = FLOW_CTRL_NONE;
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@ -1611,6 +1610,7 @@ static u8 bnx2x_link_settings_status(struct link_params *params,
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u32 gp_status)
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{
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struct bnx2x *bp = params->bp;
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u8 rc = 0;
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vars->link_status = 0;
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@ -3303,7 +3303,7 @@ static void bnx2x_link_int_enable(struct link_params *params)
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* link management
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*/
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static void bnx2x_link_int_ack(struct link_params *params,
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struct link_vars *vars, u16 is_10g)
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struct link_vars *vars, u8 is_10g)
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{
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struct bnx2x *bp = params->bp;
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u8 port = params->port;
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@ -3781,7 +3781,7 @@ u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
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SHARED_HW_CFG_LED_MAC1);
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tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
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EMAC_WR(EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
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EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
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break;
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case LED_MODE_OPER:
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@ -3794,7 +3794,7 @@ u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
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REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
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port*4, 1);
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tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
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EMAC_WR(EMAC_REG_EMAC_LED,
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EMAC_WR(bp, EMAC_REG_EMAC_LED,
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(tmp & (~EMAC_LED_OVERRIDE)));
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if (!CHIP_IS_E1H(bp) &&
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@ -3917,7 +3917,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
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struct bnx2x *bp = params->bp;
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u32 val;
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DP(NETIF_MSG_LINK, "Phy Initialization started\n");
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DP(NETIF_MSG_LINK, "Phy Initialization started \n");
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DP(NETIF_MSG_LINK, "req_speed = %d, req_flowctrl=%d\n",
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params->req_line_speed, params->req_flow_ctrl);
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vars->link_status = 0;
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@ -3933,6 +3933,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
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else
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vars->phy_flags = PHY_XGXS_FLAG;
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/* disable attentions */
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bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
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(NIG_MASK_XGXS0_LINK_STATUS |
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@ -4542,7 +4543,7 @@ static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port,
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size = MAX_APP_SIZE+HEADER_SIZE;
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}
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DP(NETIF_MSG_LINK, "File version is %c%c\n", data[0x14e], data[0x14f]);
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DP(NETIF_MSG_LINK, " %c%c\n", data[0x150], data[0x151]);
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DP(NETIF_MSG_LINK, " %c%c\n", data[0x150], data[0x151]);
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/* Put the DSP in download mode by setting FLASH_CFG[2] to 1
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and issuing a reset.*/
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@ -4824,7 +4825,7 @@ static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port,
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MDIO_PMA_REG_7101_VER2,
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&image_revision2);
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if (data[0x14e] != (image_revision2&0xFF) ||
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if (data[0x14e] != (image_revision2&0xFF) ||
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data[0x14f] != ((image_revision2&0xFF00)>>8) ||
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data[0x150] != (image_revision1&0xFF) ||
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data[0x151] != ((image_revision1&0xFF00)>>8)) {
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@ -555,8 +555,8 @@ static void bnx2x_panic_dump(struct bnx2x *bp)
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j, rx_bd[1], rx_bd[0], sw_bd->skb);
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}
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start = 0;
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end = RX_SGE_CNT*NUM_RX_SGE_PAGES;
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start = RX_SGE(fp->rx_sge_prod);
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end = RX_SGE(fp->last_max_sge);
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for (j = start; j < end; j++) {
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u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
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struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
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@ -885,6 +885,7 @@ static void bnx2x_tx_int(struct bnx2x_fastpath *fp, int work)
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}
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}
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static void bnx2x_sp_event(struct bnx2x_fastpath *fp,
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union eth_rx_cqe *rr_cqe)
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{
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@ -940,6 +941,7 @@ static void bnx2x_sp_event(struct bnx2x_fastpath *fp,
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bnx2x_fp(bp, cid, state) = BNX2X_FP_STATE_CLOSED;
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break;
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case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN):
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case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DIAG):
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DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
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@ -1370,7 +1372,6 @@ static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
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u16 bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
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u16 hw_comp_cons, sw_comp_cons, sw_comp_prod;
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int rx_pkt = 0;
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u16 queue;
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#ifdef BNX2X_STOP_ON_ERROR
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if (unlikely(bp->panic))
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@ -1436,7 +1437,7 @@ static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
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if ((!fp->disable_tpa) &&
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(TPA_TYPE(cqe_fp_flags) !=
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(TPA_TYPE_START | TPA_TYPE_END))) {
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queue = cqe->fast_path_cqe.queue_index;
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u16 queue = cqe->fast_path_cqe.queue_index;
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if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_START) {
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DP(NETIF_MSG_RX_STATUS,
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@ -1635,17 +1636,17 @@ static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
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}
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DP(NETIF_MSG_INTR, "got an interrupt status %u\n", status);
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#ifdef BNX2X_STOP_ON_ERROR
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if (unlikely(bp->panic))
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return IRQ_HANDLED;
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#endif
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/* Return here if interrupt is disabled */
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if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
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DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
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return IRQ_HANDLED;
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}
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#ifdef BNX2X_STOP_ON_ERROR
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if (unlikely(bp->panic))
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return IRQ_HANDLED;
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#endif
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mask = 0x2 << bp->fp[0].sb_id;
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if (status & mask) {
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struct bnx2x_fastpath *fp = &bp->fp[0];
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@ -2827,7 +2828,7 @@ static void bnx2x_sp_task(struct work_struct *work)
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/* Return here if interrupt is disabled */
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if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
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DP(BNX2X_MSG_SP, "called but intr_sem not 0, returning\n");
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DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
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return;
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}
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@ -2835,7 +2836,7 @@ static void bnx2x_sp_task(struct work_struct *work)
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/* if (status == 0) */
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/* BNX2X_ERR("spurious slowpath interrupt!\n"); */
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DP(BNX2X_MSG_SP, "got a slowpath interrupt (updated %x)\n", status);
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DP(NETIF_MSG_INTR, "got a slowpath interrupt (updated %x)\n", status);
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/* HW attentions */
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if (status & 0x1)
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|
|
@ -2865,7 +2866,7 @@ static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
|
|||
|
||||
/* Return here if interrupt is disabled */
|
||||
if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
|
||||
DP(BNX2X_MSG_SP, "called but intr_sem not 0, returning\n");
|
||||
DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
|
|
@ -4563,7 +4564,7 @@ static void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
|
|||
int func = BP_FUNC(bp);
|
||||
int i;
|
||||
|
||||
DP(NETIF_MSG_RX_STATUS, "rx mode is %d\n", mode);
|
||||
DP(NETIF_MSG_IFUP, "rx mode %d mask 0x%x\n", mode, mask);
|
||||
|
||||
switch (mode) {
|
||||
case BNX2X_RX_MODE_NONE: /* no Rx */
|
||||
|
|
@ -4922,7 +4923,7 @@ static int bnx2x_int_mem_test(struct bnx2x *bp)
|
|||
REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
|
||||
REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
|
||||
REG_WR(bp, CFC_REG_DEBUG0, 0x1);
|
||||
NIG_WR(NIG_REG_PRS_REQ_IN_EN, 0x0);
|
||||
REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
|
||||
|
||||
/* Write 0 to parser credits for CFC search request */
|
||||
REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
|
||||
|
|
@ -4977,7 +4978,7 @@ static int bnx2x_int_mem_test(struct bnx2x *bp)
|
|||
REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
|
||||
REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
|
||||
REG_WR(bp, CFC_REG_DEBUG0, 0x1);
|
||||
NIG_WR(NIG_REG_PRS_REQ_IN_EN, 0x0);
|
||||
REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
|
||||
|
||||
/* Write 0 to parser credits for CFC search request */
|
||||
REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
|
||||
|
|
@ -5044,7 +5045,7 @@ static int bnx2x_int_mem_test(struct bnx2x *bp)
|
|||
REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
|
||||
REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
|
||||
REG_WR(bp, CFC_REG_DEBUG0, 0x0);
|
||||
NIG_WR(NIG_REG_PRS_REQ_IN_EN, 0x1);
|
||||
REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
|
||||
|
||||
DP(NETIF_MSG_HW, "done\n");
|
||||
|
||||
|
|
@ -5133,11 +5134,6 @@ static int bnx2x_init_common(struct bnx2x *bp)
|
|||
REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
|
||||
#endif
|
||||
|
||||
#ifndef BCM_ISCSI
|
||||
/* set NIC mode */
|
||||
REG_WR(bp, PRS_REG_NIC_MODE, 1);
|
||||
#endif
|
||||
|
||||
REG_WR(bp, PXP2_REG_RQ_CDU_P_SIZE, 2);
|
||||
#ifdef BCM_ISCSI
|
||||
REG_WR(bp, PXP2_REG_RQ_TM_P_SIZE, 5);
|
||||
|
|
@ -5207,6 +5203,8 @@ static int bnx2x_init_common(struct bnx2x *bp)
|
|||
}
|
||||
|
||||
bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
|
||||
/* set NIC mode */
|
||||
REG_WR(bp, PRS_REG_NIC_MODE, 1);
|
||||
if (CHIP_IS_E1H(bp))
|
||||
REG_WR(bp, PRS_REG_E1HOV_MODE, IS_E1HMF(bp));
|
||||
|
||||
|
|
@ -6034,8 +6032,8 @@ static int bnx2x_req_msix_irqs(struct bnx2x *bp)
|
|||
bnx2x_msix_fp_int, 0,
|
||||
bp->dev->name, &bp->fp[i]);
|
||||
if (rc) {
|
||||
BNX2X_ERR("request fp #%d irq failed rc %d\n",
|
||||
i + offset, rc);
|
||||
BNX2X_ERR("request fp #%d irq failed rc -%d\n",
|
||||
i + offset, -rc);
|
||||
bnx2x_free_msix_irqs(bp);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
|
@ -6237,7 +6235,6 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
|
|||
{
|
||||
u32 load_code;
|
||||
int i, rc;
|
||||
|
||||
#ifdef BNX2X_STOP_ON_ERROR
|
||||
if (unlikely(bp->panic))
|
||||
return -EPERM;
|
||||
|
|
@ -6444,8 +6441,7 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
|
|||
/* Free SKBs, SGEs, TPA pool and driver internals */
|
||||
bnx2x_free_skbs(bp);
|
||||
for_each_queue(bp, i)
|
||||
bnx2x_free_rx_sge_range(bp, bp->fp + i,
|
||||
RX_SGE_CNT*NUM_RX_SGE_PAGES);
|
||||
bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
|
||||
load_error:
|
||||
bnx2x_free_mem(bp);
|
||||
|
||||
|
|
@ -6683,11 +6679,11 @@ static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
|
|||
u8 entry = (BP_E1HVN(bp) + 1)*8;
|
||||
|
||||
val = (mac_addr[0] << 8) | mac_addr[1];
|
||||
EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + entry, val);
|
||||
EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
|
||||
|
||||
val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
|
||||
(mac_addr[4] << 8) | mac_addr[5];
|
||||
EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
|
||||
EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
|
||||
|
||||
reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
|
||||
|
||||
|
|
@ -6773,8 +6769,7 @@ static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
|
|||
/* Free SKBs, SGEs, TPA pool and driver internals */
|
||||
bnx2x_free_skbs(bp);
|
||||
for_each_queue(bp, i)
|
||||
bnx2x_free_rx_sge_range(bp, bp->fp + i,
|
||||
RX_SGE_CNT*NUM_RX_SGE_PAGES);
|
||||
bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
|
||||
bnx2x_free_mem(bp);
|
||||
|
||||
bp->state = BNX2X_STATE_CLOSED;
|
||||
|
|
@ -7411,9 +7406,8 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
|
|||
bp->mf_config =
|
||||
SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
|
||||
|
||||
val =
|
||||
(SHMEM_RD(bp, mf_cfg.func_mf_config[func].e1hov_tag) &
|
||||
FUNC_MF_CFG_E1HOV_TAG_MASK);
|
||||
val = (SHMEM_RD(bp, mf_cfg.func_mf_config[func].e1hov_tag) &
|
||||
FUNC_MF_CFG_E1HOV_TAG_MASK);
|
||||
if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
|
||||
|
||||
bp->e1hov = val;
|
||||
|
|
@ -8368,7 +8362,7 @@ static int bnx2x_set_pauseparam(struct net_device *dev,
|
|||
|
||||
if (epause->autoneg) {
|
||||
if (!(bp->port.supported & SUPPORTED_Autoneg)) {
|
||||
DP(NETIF_MSG_LINK, "Autoneg not supported\n");
|
||||
DP(NETIF_MSG_LINK, "autoneg not supported\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
|
@ -9536,7 +9530,8 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
|
|||
tx_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
|
||||
tx_bd->general_data = (UNICAST_ADDRESS <<
|
||||
ETH_TX_BD_ETH_ADDR_TYPE_SHIFT);
|
||||
tx_bd->general_data |= 1; /* header nbd */
|
||||
/* header nbd */
|
||||
tx_bd->general_data |= (1 << ETH_TX_BD_HDR_NBDS_SHIFT);
|
||||
|
||||
/* remember the first BD of the packet */
|
||||
tx_buf->first_bd = fp->tx_bd_prod;
|
||||
|
|
@ -9898,6 +9893,7 @@ static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
|
|||
{
|
||||
struct mii_ioctl_data *data = if_mii(ifr);
|
||||
struct bnx2x *bp = netdev_priv(dev);
|
||||
int port = BP_PORT(bp);
|
||||
int err;
|
||||
|
||||
switch (cmd) {
|
||||
|
|
@ -9913,7 +9909,7 @@ static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
|
|||
return -EAGAIN;
|
||||
|
||||
mutex_lock(&bp->port.phy_mutex);
|
||||
err = bnx2x_cl45_read(bp, BP_PORT(bp), 0, bp->port.phy_addr,
|
||||
err = bnx2x_cl45_read(bp, port, 0, bp->port.phy_addr,
|
||||
DEFAULT_PHY_DEV_ADDR,
|
||||
(data->reg_num & 0x1f), &mii_regval);
|
||||
data->val_out = mii_regval;
|
||||
|
|
@ -9929,7 +9925,7 @@ static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
|
|||
return -EAGAIN;
|
||||
|
||||
mutex_lock(&bp->port.phy_mutex);
|
||||
err = bnx2x_cl45_write(bp, BP_PORT(bp), 0, bp->port.phy_addr,
|
||||
err = bnx2x_cl45_write(bp, port, 0, bp->port.phy_addr,
|
||||
DEFAULT_PHY_DEV_ADDR,
|
||||
(data->reg_num & 0x1f), data->val_in);
|
||||
mutex_unlock(&bp->port.phy_mutex);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user