AcoSail/kernel_optimize_test
8
0
Fork 0
forked from luck/tmp_suning_uos_patched
Code Pull Requests Activity

ARM: S5PV310: Bug fix on uclk1 and sclk_pwm

Browse Source 
This patch fixes on enable and ctrlbit of uclk1 and sclk_pwm.

Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Jongpill Lee 2010-08-27 17:53:26 +09:00 committed by Kukjin Kim
parent 5a847b4af8
commit 3297c2e6d7
2 changed files with 15 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
arch/arm/mach-s5pv310/clock.c
View File

@ -30,6 +30,11 @@ static struct clk clk_sclk_hdmi27m = {
.rate = 27000000, .rate = 27000000,
}; };
static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
}
static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable) static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
{ {
return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable); return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
@ -397,7 +402,7 @@ static struct clksrc_clk clksrcs[] = {
.clk = { .clk = {
.name = "uclk1", .name = "uclk1",
.id = 0, .id = 0,
.enable = s5pv310_clk_ip_peril_ctrl, .enable = s5pv310_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, },
.sources = &clkset_group, .sources = &clkset_group,
@ -407,8 +412,8 @@ static struct clksrc_clk clksrcs[] = {
.clk = { .clk = {
.name = "uclk1", .name = "uclk1",
.id = 1, .id = 1,
.enable = s5pv310_clk_ip_peril_ctrl, .enable = s5pv310_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 4),
}, },
.sources = &clkset_group, .sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 }, .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
@ -417,8 +422,8 @@ static struct clksrc_clk clksrcs[] = {
.clk = { .clk = {
.name = "uclk1", .name = "uclk1",
.id = 2, .id = 2,
.enable = s5pv310_clk_ip_peril_ctrl, .enable = s5pv310_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 2), .ctrlbit = (1 << 8),
}, },
.sources = &clkset_group, .sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 }, .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
@ -427,8 +432,8 @@ static struct clksrc_clk clksrcs[] = {
.clk = { .clk = {
.name = "uclk1", .name = "uclk1",
.id = 3, .id = 3,
.enable = s5pv310_clk_ip_peril_ctrl, .enable = s5pv310_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 12),
}, },
.sources = &clkset_group, .sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 }, .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
@ -437,7 +442,7 @@ static struct clksrc_clk clksrcs[] = {
.clk = { .clk = {
.name = "sclk_pwm", .name = "sclk_pwm",
.id = -1, .id = -1,
.enable = s5pv310_clk_ip_peril_ctrl, .enable = s5pv310_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 24), .ctrlbit = (1 << 24),
}, },
.sources = &clkset_group, .sources = &clkset_group,

2
arch/arm/mach-s5pv310/include/mach/regs-clock.h
View File

@ -38,6 +38,8 @@
#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560) #define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560)
#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564) #define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950) #define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
#define S5P_CLKSRC_CORE S5P_CLKREG(0x10200) #define S5P_CLKSRC_CORE S5P_CLKREG(0x10200)