forked from luck/tmp_suning_uos_patched
PCI: Simplify PCI device PM code
If the offset of PCI device's PM capability in its configuration space, the mask of states that the device supports PME# from and the D1 and D2 support bits are cached in the corresponding struct pci_dev, the PCI device PM code can be simplified quite a bit. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
This commit is contained in:
Rafael J. Wysocki
Jesse Barnes
parent
404cc2d8ce
commit
337001b6c4
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@ -419,7 +419,6 @@ static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
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* pci_raw_set_power_state - Use PCI PM registers to set the power state of
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* given PCI device
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* @dev: PCI device to handle.
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* @pm: PCI PM capability offset of the device.
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* @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
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*
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* RETURN VALUE:
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@ -430,12 +429,12 @@ static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
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* 0 if device's power state has been successfully changed.
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*/
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static int
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pci_raw_set_power_state(struct pci_dev *dev, int pm, pci_power_t state)
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pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
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{
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u16 pmcsr, pmc;
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u16 pmcsr;
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bool need_restore = false;
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if (!pm)
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if (!dev->pm_cap)
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return -EIO;
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if (state < PCI_D0 || state > PCI_D3hot)
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@ -455,20 +454,12 @@ pci_raw_set_power_state(struct pci_dev *dev, int pm, pci_power_t state)
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return -EINVAL;
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}
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pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
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if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
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dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
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pmc & PCI_PM_CAP_VER_MASK);
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return -EIO;
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}
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/* check if this device supports the desired state */
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if ((state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
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|| (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2)))
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if ((state == PCI_D1 && !dev->d1_support)
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|| (state == PCI_D2 && !dev->d2_support))
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return -EIO;
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pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
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pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
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/* If we're (effectively) in D3, force entire word to 0.
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* This doesn't affect PME_Status, disables PME_En, and
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@ -492,7 +483,7 @@ pci_raw_set_power_state(struct pci_dev *dev, int pm, pci_power_t state)
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}
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/* enter specified state */
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pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
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pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
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/* Mandatory power management transition delays */
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/* see PCI PM 1.1 5.6.1 table 18 */
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@ -528,14 +519,13 @@ pci_raw_set_power_state(struct pci_dev *dev, int pm, pci_power_t state)
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* pci_update_current_state - Read PCI power state of given device from its
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* PCI PM registers and cache it
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* @dev: PCI device to handle.
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* @pm: PCI PM capability offset of the device.
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*/
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static void pci_update_current_state(struct pci_dev *dev, int pm)
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static void pci_update_current_state(struct pci_dev *dev)
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{
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if (pm) {
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if (dev->pm_cap) {
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u16 pmcsr;
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pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
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pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
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dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
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}
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}
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@ -557,7 +547,7 @@ static void pci_update_current_state(struct pci_dev *dev, int pm)
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*/
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int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
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{
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int pm, error;
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int error;
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/* bound the state we're entering */
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if (state > PCI_D3hot)
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@ -572,9 +562,6 @@ int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
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*/
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return 0;
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/* Find PCI PM capability in the list */
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pm = pci_find_capability(dev, PCI_CAP_ID_PM);
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if (state == PCI_D0 && platform_pci_power_manageable(dev)) {
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/*
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* Allow the platform to change the state, for example via ACPI
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@ -582,16 +569,16 @@ int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
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*/
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int ret = platform_pci_set_power_state(dev, PCI_D0);
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if (!ret)
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pci_update_current_state(dev, pm);
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pci_update_current_state(dev);
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}
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error = pci_raw_set_power_state(dev, pm, state);
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error = pci_raw_set_power_state(dev, state);
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if (state > PCI_D0 && platform_pci_power_manageable(dev)) {
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/* Allow the platform to finalize the transition */
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int ret = platform_pci_set_power_state(dev, state);
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if (!ret) {
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pci_update_current_state(dev, pm);
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pci_update_current_state(dev);
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error = 0;
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}
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}
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@ -1050,48 +1037,38 @@ int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
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/**
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* pci_pme_capable - check the capability of PCI device to generate PME#
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* @dev: PCI device to handle.
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* @pm: PCI PM capability offset of the device.
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* @state: PCI state from which device will issue PME#.
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*/
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static bool pci_pme_capable(struct pci_dev *dev, int pm, pci_power_t state)
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static bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
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{
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u16 pmc;
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if (!pm)
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if (!dev->pm_cap)
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return false;
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/* Check device's ability to generate PME# from given state */
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pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
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pmc &= PCI_PM_CAP_PME_MASK;
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pmc >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
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return !!(pmc & (1 << state));
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return !!(dev->pme_support & (1 << state));
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}
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/**
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* pci_pme_active - enable or disable PCI device's PME# function
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* @dev: PCI device to handle.
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* @pm: PCI PM capability offset of the device.
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* @enable: 'true' to enable PME# generation; 'false' to disable it.
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*
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* The caller must verify that the device is capable of generating PME# before
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* calling this function with @enable equal to 'true'.
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*/
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static void pci_pme_active(struct pci_dev *dev, int pm, bool enable)
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static void pci_pme_active(struct pci_dev *dev, bool enable)
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{
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u16 pmcsr;
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if (!pm)
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if (!dev->pm_cap)
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return;
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pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
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pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
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/* Clear PME_Status by writing 1 to it and enable PME# */
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pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
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if (!enable)
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pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
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pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
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pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
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dev_printk(KERN_INFO, &dev->dev, "PME# %s\n",
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enable ? "enabled" : "disabled");
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@ -1118,7 +1095,6 @@ static void pci_pme_active(struct pci_dev *dev, int pm, bool enable)
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*/
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int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
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{
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int pm;
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int error = 0;
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bool pme_done = false;
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@ -1134,9 +1110,8 @@ int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
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if (!enable && platform_pci_can_wakeup(dev))
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error = platform_pci_sleep_wake(dev, false);
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pm = pci_find_capability(dev, PCI_CAP_ID_PM);
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if (!enable || pci_pme_capable(dev, pm, state)) {
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pci_pme_active(dev, pm, enable);
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if (!enable || pci_pme_capable(dev, state)) {
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pci_pme_active(dev, enable);
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pme_done = true;
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}
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@ -1158,7 +1133,6 @@ int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
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int pci_prepare_to_sleep(struct pci_dev *dev)
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{
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pci_power_t target_state = PCI_D3hot;
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int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
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int error;
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if (platform_pci_power_manageable(dev)) {
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@ -1186,23 +1160,14 @@ int pci_prepare_to_sleep(struct pci_dev *dev)
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* wake-up events, make it the target state and enable device
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* to generate PME#.
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*/
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u16 pmc;
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if (!pm)
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if (!dev->pm_cap)
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return -EIO;
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pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
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if (pmc & PCI_PM_CAP_PME_MASK) {
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if (!(pmc & PCI_PM_CAP_PME_D3)) {
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/* Device cannot generate PME# from D3_hot */
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if (pmc & PCI_PM_CAP_PME_D2)
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target_state = PCI_D2;
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else if (pmc & PCI_PM_CAP_PME_D1)
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target_state = PCI_D1;
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else
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target_state = PCI_D0;
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}
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pci_pme_active(dev, pm, true);
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if (dev->pme_support) {
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while (target_state
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&& !(dev->pme_support & (1 << target_state)))
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target_state--;
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pci_pme_active(dev, true);
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}
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}
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@ -1236,6 +1201,8 @@ void pci_pm_init(struct pci_dev *dev)
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int pm;
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u16 pmc;
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dev->pm_cap = 0;
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/* find PCI PM capability in list */
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pm = pci_find_capability(dev, PCI_CAP_ID_PM);
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if (!pm)
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@ -1249,7 +1216,23 @@ void pci_pm_init(struct pci_dev *dev)
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return;
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}
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if (pmc & PCI_PM_CAP_PME_MASK) {
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dev->pm_cap = pm;
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dev->d1_support = false;
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dev->d2_support = false;
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if (!pci_no_d1d2(dev)) {
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if (pmc & PCI_PM_CAP_D1) {
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dev_printk(KERN_DEBUG, &dev->dev, "supports D1\n");
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dev->d1_support = true;
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}
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if (pmc & PCI_PM_CAP_D2) {
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dev_printk(KERN_DEBUG, &dev->dev, "supports D2\n");
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dev->d2_support = true;
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}
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}
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pmc &= PCI_PM_CAP_PME_MASK;
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if (pmc) {
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dev_printk(KERN_INFO, &dev->dev,
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"PME# supported from%s%s%s%s%s\n",
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(pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
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@ -1257,6 +1240,7 @@ void pci_pm_init(struct pci_dev *dev)
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(pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
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(pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
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(pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
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dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
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/*
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* Make device's PM flags reflect the wake-up capability, but
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* let the user space enable it to wake up the system as needed.
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@ -1264,7 +1248,9 @@ void pci_pm_init(struct pci_dev *dev)
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device_set_wakeup_capable(&dev->dev, true);
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device_set_wakeup_enable(&dev->dev, false);
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/* Disable the PME# generation functionality */
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pci_pme_active(dev, pm, false);
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pci_pme_active(dev, false);
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} else {
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dev->pme_support = 0;
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}
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}
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@ -177,6 +177,13 @@ struct pci_dev {
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pci_power_t current_state; /* Current operating state. In ACPI-speak,
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this is D0-D3, D0 being fully functional,
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and D3 being off. */
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int pm_cap; /* PM capability offset in the
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configuration space */
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unsigned int pme_support:5; /* Bitmask of states from which PME#
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can be generated */
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unsigned int d1_support:1; /* Low power state D1 is supported */
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unsigned int d2_support:1; /* Low power state D2 is supported */
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unsigned int no_d1d2:1; /* Only allow D0 and D3 */
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#ifdef CONFIG_PCIEASPM
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struct pcie_link_state *link_state; /* ASPM link state. */
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@ -201,7 +208,6 @@ struct pci_dev {
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unsigned int is_added:1;
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unsigned int is_busmaster:1; /* device is busmaster */
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unsigned int no_msi:1; /* device may not use msi */
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unsigned int no_d1d2:1; /* only allow d0 or d3 */
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unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
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unsigned int broken_parity_status:1; /* Device generates false positive parity */
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unsigned int msi_enabled:1;
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@ -231,6 +231,7 @@
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#define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
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#define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
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#define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
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#define PCI_PM_CAP_PME_SHIFT 11 /* Start of the PME Mask in PMC */
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#define PCI_PM_CTRL 4 /* PM control and status register */
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#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
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#define PCI_PM_CTRL_NO_SOFT_RESET 0x0004 /* No reset for D3hot->D0 */
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