forked from luck/tmp_suning_uos_patched
KVM: x86: Fold decache_cr3() into cache_reg()
Handle caching CR3 (from VMX's VMCS) into struct kvm_vcpu via the common cache_reg() callback and drop the dedicated decache_cr3(). The name decache_cr3() is somewhat confusing as the caching behavior of CR3 follows that of GPRs, RFLAGS and PDPTRs, (handled via cache_reg()), and has nothing in common with the caching behavior of CR0/CR4 (whose decache_cr{0,4}_guest_bits() likely provided the 'decache' verbiage). This would effectivel adds a BUG() if KVM attempts to cache CR3 on SVM. Change it to a WARN_ON_ONCE() -- if the cache never requires filling, the value is already in the right place -- and opportunistically add one in VMX to provide an equivalent check. Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -1033,7 +1033,6 @@ struct kvm_x86_ops {
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struct kvm_segment *var, int seg);
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void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l);
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void (*decache_cr0_guest_bits)(struct kvm_vcpu *vcpu);
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void (*decache_cr3)(struct kvm_vcpu *vcpu);
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void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu);
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void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0);
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void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3);
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@ -137,7 +137,7 @@ static inline ulong kvm_read_cr4_bits(struct kvm_vcpu *vcpu, ulong mask)
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static inline ulong kvm_read_cr3(struct kvm_vcpu *vcpu)
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{
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if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
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kvm_x86_ops->decache_cr3(vcpu);
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kvm_x86_ops->cache_reg(vcpu, VCPU_EXREG_CR3);
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return vcpu->arch.cr3;
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}
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@ -2376,7 +2376,7 @@ static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
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load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
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break;
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default:
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BUG();
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WARN_ON_ONCE(1);
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}
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}
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@ -2529,10 +2529,6 @@ static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
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{
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}
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static void svm_decache_cr3(struct kvm_vcpu *vcpu)
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{
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}
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static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
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{
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}
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@ -7269,7 +7265,6 @@ static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
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.get_cpl = svm_get_cpl,
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.get_cs_db_l_bits = kvm_get_cs_db_l_bits,
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.decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
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.decache_cr3 = svm_decache_cr3,
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.decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
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.set_cr0 = svm_set_cr0,
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.set_cr3 = svm_set_cr3,
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@ -2192,7 +2192,12 @@ static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
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if (enable_ept)
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ept_save_pdptrs(vcpu);
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break;
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case VCPU_EXREG_CR3:
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if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
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vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
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break;
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default:
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WARN_ON_ONCE(1);
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break;
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}
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}
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@ -2863,13 +2868,6 @@ static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
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vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
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}
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static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
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{
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if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
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vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
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kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
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}
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static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
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{
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ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
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@ -2914,7 +2912,7 @@ static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
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struct vcpu_vmx *vmx = to_vmx(vcpu);
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if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
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vmx_decache_cr3(vcpu);
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vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
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if (!(cr0 & X86_CR0_PG)) {
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/* From paging/starting to nonpaging */
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exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
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@ -7784,7 +7782,6 @@ static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
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.get_cpl = vmx_get_cpl,
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.get_cs_db_l_bits = vmx_get_cs_db_l_bits,
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.decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
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.decache_cr3 = vmx_decache_cr3,
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.decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
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.set_cr0 = vmx_set_cr0,
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.set_cr3 = vmx_set_cr3,
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