forked from luck/tmp_suning_uos_patched
Merge branch 'arm/renesas' into arm/smmu
This commit is contained in:
Joerg Roedel
commit
3430abd6f4
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@ -36,12 +36,16 @@
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#define arm_iommu_detach_device(...) do {} while (0)
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#endif
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#define IPMMU_CTX_MAX 8
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#define IPMMU_CTX_MAX 8U
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#define IPMMU_CTX_INVALID -1
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#define IPMMU_UTLB_MAX 48U
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struct ipmmu_features {
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bool use_ns_alias_offset;
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bool has_cache_leaf_nodes;
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unsigned int number_of_contexts;
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unsigned int num_utlbs;
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bool setup_imbuscr;
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bool twobit_imttbcr_sl0;
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bool reserved_context;
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@ -53,11 +57,11 @@ struct ipmmu_vmsa_device {
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struct iommu_device iommu;
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struct ipmmu_vmsa_device *root;
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const struct ipmmu_features *features;
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unsigned int num_utlbs;
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unsigned int num_ctx;
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spinlock_t lock; /* Protects ctx and domains[] */
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DECLARE_BITMAP(ctx, IPMMU_CTX_MAX);
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struct ipmmu_vmsa_domain *domains[IPMMU_CTX_MAX];
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s8 utlb_ctx[IPMMU_UTLB_MAX];
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struct iommu_group *group;
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struct dma_iommu_mapping *mapping;
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@ -186,7 +190,8 @@ static struct ipmmu_vmsa_device *to_ipmmu(struct device *dev)
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#define IMMAIR_ATTR_IDX_WBRWA 1
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#define IMMAIR_ATTR_IDX_DEV 2
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#define IMEAR 0x0030
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#define IMELAR 0x0030 /* IMEAR on R-Car Gen2 */
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#define IMEUAR 0x0034 /* R-Car Gen3 only */
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#define IMPCTR 0x0200
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#define IMPSTR 0x0208
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@ -334,6 +339,7 @@ static void ipmmu_utlb_enable(struct ipmmu_vmsa_domain *domain,
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ipmmu_write(mmu, IMUCTR(utlb),
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IMUCTR_TTSEL_MMU(domain->context_id) | IMUCTR_FLUSH |
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IMUCTR_MMUEN);
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mmu->utlb_ctx[utlb] = domain->context_id;
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}
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/*
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@ -345,6 +351,7 @@ static void ipmmu_utlb_disable(struct ipmmu_vmsa_domain *domain,
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struct ipmmu_vmsa_device *mmu = domain->mmu;
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ipmmu_write(mmu, IMUCTR(utlb), 0);
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mmu->utlb_ctx[utlb] = IPMMU_CTX_INVALID;
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}
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static void ipmmu_tlb_flush_all(void *cookie)
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@ -403,53 +410,10 @@ static void ipmmu_domain_free_context(struct ipmmu_vmsa_device *mmu,
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spin_unlock_irqrestore(&mmu->lock, flags);
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}
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static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
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static void ipmmu_domain_setup_context(struct ipmmu_vmsa_domain *domain)
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{
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u64 ttbr;
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u32 tmp;
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int ret;
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/*
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* Allocate the page table operations.
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*
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* VMSA states in section B3.6.3 "Control of Secure or Non-secure memory
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* access, Long-descriptor format" that the NStable bit being set in a
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* table descriptor will result in the NStable and NS bits of all child
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* entries being ignored and considered as being set. The IPMMU seems
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* not to comply with this, as it generates a secure access page fault
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* if any of the NStable and NS bits isn't set when running in
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* non-secure mode.
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*/
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domain->cfg.quirks = IO_PGTABLE_QUIRK_ARM_NS;
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domain->cfg.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K;
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domain->cfg.ias = 32;
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domain->cfg.oas = 40;
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domain->cfg.tlb = &ipmmu_gather_ops;
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domain->io_domain.geometry.aperture_end = DMA_BIT_MASK(32);
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domain->io_domain.geometry.force_aperture = true;
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/*
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* TODO: Add support for coherent walk through CCI with DVM and remove
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* cache handling. For now, delegate it to the io-pgtable code.
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*/
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domain->cfg.coherent_walk = false;
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domain->cfg.iommu_dev = domain->mmu->root->dev;
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/*
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* Find an unused context.
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*/
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ret = ipmmu_domain_allocate_context(domain->mmu->root, domain);
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if (ret < 0)
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return ret;
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domain->context_id = ret;
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domain->iop = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &domain->cfg,
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domain);
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if (!domain->iop) {
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ipmmu_domain_free_context(domain->mmu->root,
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domain->context_id);
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return -EINVAL;
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}
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/* TTBR0 */
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ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr[0];
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@ -495,7 +459,55 @@ static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
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*/
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ipmmu_ctx_write_all(domain, IMCTR,
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IMCTR_INTEN | IMCTR_FLUSH | IMCTR_MMUEN);
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}
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static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
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{
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int ret;
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/*
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* Allocate the page table operations.
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*
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* VMSA states in section B3.6.3 "Control of Secure or Non-secure memory
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* access, Long-descriptor format" that the NStable bit being set in a
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* table descriptor will result in the NStable and NS bits of all child
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* entries being ignored and considered as being set. The IPMMU seems
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* not to comply with this, as it generates a secure access page fault
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* if any of the NStable and NS bits isn't set when running in
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* non-secure mode.
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*/
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domain->cfg.quirks = IO_PGTABLE_QUIRK_ARM_NS;
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domain->cfg.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K;
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domain->cfg.ias = 32;
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domain->cfg.oas = 40;
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domain->cfg.tlb = &ipmmu_gather_ops;
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domain->io_domain.geometry.aperture_end = DMA_BIT_MASK(32);
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domain->io_domain.geometry.force_aperture = true;
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/*
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* TODO: Add support for coherent walk through CCI with DVM and remove
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* cache handling. For now, delegate it to the io-pgtable code.
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*/
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domain->cfg.coherent_walk = false;
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domain->cfg.iommu_dev = domain->mmu->root->dev;
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/*
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* Find an unused context.
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*/
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ret = ipmmu_domain_allocate_context(domain->mmu->root, domain);
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if (ret < 0)
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return ret;
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domain->context_id = ret;
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domain->iop = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &domain->cfg,
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domain);
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if (!domain->iop) {
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ipmmu_domain_free_context(domain->mmu->root,
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domain->context_id);
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return -EINVAL;
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}
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ipmmu_domain_setup_context(domain);
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return 0;
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}
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@ -523,14 +535,16 @@ static irqreturn_t ipmmu_domain_irq(struct ipmmu_vmsa_domain *domain)
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{
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const u32 err_mask = IMSTR_MHIT | IMSTR_ABORT | IMSTR_PF | IMSTR_TF;
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struct ipmmu_vmsa_device *mmu = domain->mmu;
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unsigned long iova;
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u32 status;
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u32 iova;
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status = ipmmu_ctx_read_root(domain, IMSTR);
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if (!(status & err_mask))
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return IRQ_NONE;
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iova = ipmmu_ctx_read_root(domain, IMEAR);
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iova = ipmmu_ctx_read_root(domain, IMELAR);
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if (IS_ENABLED(CONFIG_64BIT))
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iova |= (u64)ipmmu_ctx_read_root(domain, IMEUAR) << 32;
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/*
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* Clear the error status flags. Unlike traditional interrupt flag
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@ -542,10 +556,10 @@ static irqreturn_t ipmmu_domain_irq(struct ipmmu_vmsa_domain *domain)
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/* Log fatal errors. */
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if (status & IMSTR_MHIT)
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dev_err_ratelimited(mmu->dev, "Multiple TLB hits @0x%08x\n",
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dev_err_ratelimited(mmu->dev, "Multiple TLB hits @0x%lx\n",
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iova);
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if (status & IMSTR_ABORT)
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dev_err_ratelimited(mmu->dev, "Page Table Walk Abort @0x%08x\n",
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dev_err_ratelimited(mmu->dev, "Page Table Walk Abort @0x%lx\n",
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iova);
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if (!(status & (IMSTR_PF | IMSTR_TF)))
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@ -561,7 +575,7 @@ static irqreturn_t ipmmu_domain_irq(struct ipmmu_vmsa_domain *domain)
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return IRQ_HANDLED;
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dev_err_ratelimited(mmu->dev,
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"Unhandled fault: status 0x%08x iova 0x%08x\n",
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"Unhandled fault: status 0x%08x iova 0x%lx\n",
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status, iova);
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return IRQ_HANDLED;
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@ -886,27 +900,37 @@ static int ipmmu_init_arm_mapping(struct device *dev)
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static int ipmmu_add_device(struct device *dev)
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{
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struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
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struct iommu_group *group;
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int ret;
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/*
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* Only let through devices that have been verified in xlate()
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*/
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if (!to_ipmmu(dev))
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if (!mmu)
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return -ENODEV;
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if (IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_IOMMU_DMA))
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return ipmmu_init_arm_mapping(dev);
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if (IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_IOMMU_DMA)) {
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ret = ipmmu_init_arm_mapping(dev);
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if (ret)
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return ret;
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} else {
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group = iommu_group_get_for_dev(dev);
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if (IS_ERR(group))
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return PTR_ERR(group);
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group = iommu_group_get_for_dev(dev);
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if (IS_ERR(group))
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return PTR_ERR(group);
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iommu_group_put(group);
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}
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iommu_group_put(group);
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iommu_device_link(&mmu->iommu, dev);
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return 0;
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}
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static void ipmmu_remove_device(struct device *dev)
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{
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struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
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iommu_device_unlink(&mmu->iommu, dev);
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arm_iommu_detach_device(dev);
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iommu_group_remove_device(dev);
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}
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@ -960,6 +984,7 @@ static const struct ipmmu_features ipmmu_features_default = {
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.use_ns_alias_offset = true,
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.has_cache_leaf_nodes = false,
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.number_of_contexts = 1, /* software only tested with one context */
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.num_utlbs = 32,
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.setup_imbuscr = true,
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.twobit_imttbcr_sl0 = false,
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.reserved_context = false,
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@ -969,6 +994,7 @@ static const struct ipmmu_features ipmmu_features_rcar_gen3 = {
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.use_ns_alias_offset = false,
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.has_cache_leaf_nodes = true,
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.number_of_contexts = 8,
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.num_utlbs = 48,
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.setup_imbuscr = false,
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.twobit_imttbcr_sl0 = true,
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.reserved_context = true,
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@ -1021,10 +1047,10 @@ static int ipmmu_probe(struct platform_device *pdev)
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}
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mmu->dev = &pdev->dev;
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mmu->num_utlbs = 48;
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spin_lock_init(&mmu->lock);
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bitmap_zero(mmu->ctx, IPMMU_CTX_MAX);
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mmu->features = of_device_get_match_data(&pdev->dev);
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memset(mmu->utlb_ctx, IPMMU_CTX_INVALID, mmu->features->num_utlbs);
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dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
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/* Map I/O memory and request IRQ. */
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@ -1048,8 +1074,7 @@ static int ipmmu_probe(struct platform_device *pdev)
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if (mmu->features->use_ns_alias_offset)
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mmu->base += IM_NS_ALIAS_OFFSET;
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mmu->num_ctx = min_t(unsigned int, IPMMU_CTX_MAX,
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mmu->features->number_of_contexts);
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mmu->num_ctx = min(IPMMU_CTX_MAX, mmu->features->number_of_contexts);
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irq = platform_get_irq(pdev, 0);
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@ -1141,10 +1166,48 @@ static int ipmmu_remove(struct platform_device *pdev)
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int ipmmu_resume_noirq(struct device *dev)
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{
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struct ipmmu_vmsa_device *mmu = dev_get_drvdata(dev);
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unsigned int i;
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/* Reset root MMU and restore contexts */
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if (ipmmu_is_root(mmu)) {
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ipmmu_device_reset(mmu);
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for (i = 0; i < mmu->num_ctx; i++) {
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if (!mmu->domains[i])
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continue;
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ipmmu_domain_setup_context(mmu->domains[i]);
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}
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}
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/* Re-enable active micro-TLBs */
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for (i = 0; i < mmu->features->num_utlbs; i++) {
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if (mmu->utlb_ctx[i] == IPMMU_CTX_INVALID)
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continue;
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ipmmu_utlb_enable(mmu->root->domains[mmu->utlb_ctx[i]], i);
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}
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return 0;
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}
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static const struct dev_pm_ops ipmmu_pm = {
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SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, ipmmu_resume_noirq)
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};
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#define DEV_PM_OPS &ipmmu_pm
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#else
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#define DEV_PM_OPS NULL
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#endif /* CONFIG_PM_SLEEP */
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static struct platform_driver ipmmu_driver = {
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.driver = {
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.name = "ipmmu-vmsa",
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.of_match_table = of_match_ptr(ipmmu_of_ids),
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.pm = DEV_PM_OPS,
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},
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.probe = ipmmu_probe,
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.remove = ipmmu_remove,
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