forked from luck/tmp_suning_uos_patched
Intel IOMMU: DMAR fault handling support
MSI interrupt handler registrations and fault handling support for Intel-IOMMU hadrware. This patch enables the MSI interrupts for the DMA remapping units and in the interrupt handler read the fault cause and outputs the same on to the console. Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Cc: Andi Kleen <ak@suse.de> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Muli Ben-Yehuda <muli@il.ibm.com> Cc: "Siddha, Suresh B" <suresh.b.siddha@intel.com> Cc: Arjan van de Ven <arjan@infradead.org> Cc: Ashok Raj <ashok.raj@intel.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Christoph Lameter <clameter@sgi.com> Cc: Greg KH <greg@kroah.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Keshavamurthy, Anil S
Linus Torvalds
parent
7d3b03ce7b
commit
3460a6d9ce
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@ -63,6 +63,15 @@ Interrupt ranges are not address translated, (0xfee00000 - 0xfeefffff).
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The same is true for peer to peer transactions. Hence we reserve the
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address from PCI MMIO ranges so they are not allocated for IOVA addresses.
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Fault reporting
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---------------
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When errors are reported, the DMA engine signals via an interrupt. The fault
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reason and device that caused it with fault reason is printed on console.
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See below for sample.
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Boot Message Sample
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-------------------
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@ -85,6 +94,14 @@ When DMAR is enabled for use, you will notice..
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PCI-DMA: Using DMAR IOMMU
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Fault reporting
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---------------
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DMAR:[DMA Write] Request device [00:02.0] fault addr 6df084000
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DMAR:[fault reason 05] PTE Write access is not set
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DMAR:[DMA Write] Request device [00:02.0] fault addr 6df084000
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DMAR:[fault reason 05] PTE Write access is not set
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TBD
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----
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@ -31,6 +31,7 @@
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#include <linux/sysdev.h>
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#include <linux/msi.h>
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#include <linux/htirq.h>
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#include <linux/dmar.h>
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#ifdef CONFIG_ACPI
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#include <acpi/acpi_bus.h>
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#endif
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@ -2031,8 +2032,64 @@ void arch_teardown_msi_irq(unsigned int irq)
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destroy_irq(irq);
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}
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#endif /* CONFIG_PCI_MSI */
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#ifdef CONFIG_DMAR
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#ifdef CONFIG_SMP
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static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
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{
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struct irq_cfg *cfg = irq_cfg + irq;
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struct msi_msg msg;
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unsigned int dest;
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cpumask_t tmp;
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cpus_and(tmp, mask, cpu_online_map);
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if (cpus_empty(tmp))
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return;
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if (assign_irq_vector(irq, mask))
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return;
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cpus_and(tmp, cfg->domain, mask);
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dest = cpu_mask_to_apicid(tmp);
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dmar_msi_read(irq, &msg);
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msg.data &= ~MSI_DATA_VECTOR_MASK;
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msg.data |= MSI_DATA_VECTOR(cfg->vector);
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msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
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msg.address_lo |= MSI_ADDR_DEST_ID(dest);
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dmar_msi_write(irq, &msg);
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irq_desc[irq].affinity = mask;
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}
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#endif /* CONFIG_SMP */
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struct irq_chip dmar_msi_type = {
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.name = "DMAR_MSI",
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.unmask = dmar_msi_unmask,
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.mask = dmar_msi_mask,
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.ack = ack_apic_edge,
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#ifdef CONFIG_SMP
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.set_affinity = dmar_msi_set_affinity,
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#endif
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.retrigger = ioapic_retrigger_irq,
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};
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int arch_setup_dmar_msi(unsigned int irq)
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{
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int ret;
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struct msi_msg msg;
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ret = msi_compose_msg(NULL, irq, &msg);
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if (ret < 0)
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return ret;
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dmar_msi_write(irq, &msg);
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set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
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"edge");
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return 0;
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}
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#endif
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#endif /* CONFIG_PCI_MSI */
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/*
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* Hypertransport interrupt support
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*/
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@ -743,6 +743,196 @@ static int iommu_disable_translation(struct intel_iommu *iommu)
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return 0;
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}
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/* iommu interrupt handling. Most stuff are MSI-like. */
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static char *fault_reason_strings[] =
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{
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"Software",
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"Present bit in root entry is clear",
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"Present bit in context entry is clear",
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"Invalid context entry",
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"Access beyond MGAW",
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"PTE Write access is not set",
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"PTE Read access is not set",
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"Next page table ptr is invalid",
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"Root table address invalid",
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"Context table ptr is invalid",
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"non-zero reserved fields in RTP",
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"non-zero reserved fields in CTP",
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"non-zero reserved fields in PTE",
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"Unknown"
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};
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#define MAX_FAULT_REASON_IDX ARRAY_SIZE(fault_reason_strings)
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char *dmar_get_fault_reason(u8 fault_reason)
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{
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if (fault_reason > MAX_FAULT_REASON_IDX)
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return fault_reason_strings[MAX_FAULT_REASON_IDX];
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else
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return fault_reason_strings[fault_reason];
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}
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void dmar_msi_unmask(unsigned int irq)
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{
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struct intel_iommu *iommu = get_irq_data(irq);
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unsigned long flag;
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/* unmask it */
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spin_lock_irqsave(&iommu->register_lock, flag);
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writel(0, iommu->reg + DMAR_FECTL_REG);
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/* Read a reg to force flush the post write */
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readl(iommu->reg + DMAR_FECTL_REG);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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void dmar_msi_mask(unsigned int irq)
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{
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unsigned long flag;
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struct intel_iommu *iommu = get_irq_data(irq);
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/* mask it */
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spin_lock_irqsave(&iommu->register_lock, flag);
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writel(DMA_FECTL_IM, iommu->reg + DMAR_FECTL_REG);
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/* Read a reg to force flush the post write */
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readl(iommu->reg + DMAR_FECTL_REG);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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void dmar_msi_write(int irq, struct msi_msg *msg)
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{
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struct intel_iommu *iommu = get_irq_data(irq);
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unsigned long flag;
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spin_lock_irqsave(&iommu->register_lock, flag);
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writel(msg->data, iommu->reg + DMAR_FEDATA_REG);
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writel(msg->address_lo, iommu->reg + DMAR_FEADDR_REG);
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writel(msg->address_hi, iommu->reg + DMAR_FEUADDR_REG);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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void dmar_msi_read(int irq, struct msi_msg *msg)
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{
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struct intel_iommu *iommu = get_irq_data(irq);
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unsigned long flag;
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spin_lock_irqsave(&iommu->register_lock, flag);
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msg->data = readl(iommu->reg + DMAR_FEDATA_REG);
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msg->address_lo = readl(iommu->reg + DMAR_FEADDR_REG);
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msg->address_hi = readl(iommu->reg + DMAR_FEUADDR_REG);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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static int iommu_page_fault_do_one(struct intel_iommu *iommu, int type,
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u8 fault_reason, u16 source_id, u64 addr)
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{
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char *reason;
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reason = dmar_get_fault_reason(fault_reason);
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printk(KERN_ERR
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"DMAR:[%s] Request device [%02x:%02x.%d] "
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"fault addr %llx \n"
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"DMAR:[fault reason %02d] %s\n",
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(type ? "DMA Read" : "DMA Write"),
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(source_id >> 8), PCI_SLOT(source_id & 0xFF),
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PCI_FUNC(source_id & 0xFF), addr, fault_reason, reason);
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return 0;
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}
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#define PRIMARY_FAULT_REG_LEN (16)
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static irqreturn_t iommu_page_fault(int irq, void *dev_id)
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{
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struct intel_iommu *iommu = dev_id;
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int reg, fault_index;
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u32 fault_status;
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unsigned long flag;
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spin_lock_irqsave(&iommu->register_lock, flag);
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fault_status = readl(iommu->reg + DMAR_FSTS_REG);
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/* TBD: ignore advanced fault log currently */
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if (!(fault_status & DMA_FSTS_PPF))
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goto clear_overflow;
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fault_index = dma_fsts_fault_record_index(fault_status);
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reg = cap_fault_reg_offset(iommu->cap);
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while (1) {
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u8 fault_reason;
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u16 source_id;
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u64 guest_addr;
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int type;
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u32 data;
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/* highest 32 bits */
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data = readl(iommu->reg + reg +
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fault_index * PRIMARY_FAULT_REG_LEN + 12);
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if (!(data & DMA_FRCD_F))
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break;
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fault_reason = dma_frcd_fault_reason(data);
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type = dma_frcd_type(data);
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data = readl(iommu->reg + reg +
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fault_index * PRIMARY_FAULT_REG_LEN + 8);
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source_id = dma_frcd_source_id(data);
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guest_addr = dmar_readq(iommu->reg + reg +
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fault_index * PRIMARY_FAULT_REG_LEN);
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guest_addr = dma_frcd_page_addr(guest_addr);
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/* clear the fault */
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writel(DMA_FRCD_F, iommu->reg + reg +
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fault_index * PRIMARY_FAULT_REG_LEN + 12);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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iommu_page_fault_do_one(iommu, type, fault_reason,
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source_id, guest_addr);
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fault_index++;
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if (fault_index > cap_num_fault_regs(iommu->cap))
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fault_index = 0;
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spin_lock_irqsave(&iommu->register_lock, flag);
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}
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clear_overflow:
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/* clear primary fault overflow */
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fault_status = readl(iommu->reg + DMAR_FSTS_REG);
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if (fault_status & DMA_FSTS_PFO)
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writel(DMA_FSTS_PFO, iommu->reg + DMAR_FSTS_REG);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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return IRQ_HANDLED;
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}
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int dmar_set_interrupt(struct intel_iommu *iommu)
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{
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int irq, ret;
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irq = create_irq();
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if (!irq) {
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printk(KERN_ERR "IOMMU: no free vectors\n");
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return -EINVAL;
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}
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set_irq_data(irq, iommu);
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iommu->irq = irq;
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ret = arch_setup_dmar_msi(irq);
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if (ret) {
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set_irq_data(irq, NULL);
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iommu->irq = 0;
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destroy_irq(irq);
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return 0;
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}
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/* Force fault register is cleared */
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iommu_page_fault(irq, iommu);
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ret = request_irq(irq, iommu_page_fault, 0, iommu->name, iommu);
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if (ret)
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printk(KERN_ERR "IOMMU: can't request irq\n");
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return ret;
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}
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static int iommu_init_domains(struct intel_iommu *iommu)
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{
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unsigned long ndomains;
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@ -1490,6 +1680,10 @@ int __init init_dmars(void)
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iommu_flush_write_buffer(iommu);
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ret = dmar_set_interrupt(iommu);
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if (ret)
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goto error;
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iommu_set_root_entry(iommu);
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iommu_flush_context_global(iommu, 0);
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@ -28,6 +28,18 @@
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#ifdef CONFIG_DMAR
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struct intel_iommu;
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extern char *dmar_get_fault_reason(u8 fault_reason);
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/* Can't use the common MSI interrupt functions
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* since DMAR is not a pci device
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*/
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extern void dmar_msi_unmask(unsigned int irq);
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extern void dmar_msi_mask(unsigned int irq);
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extern void dmar_msi_read(int irq, struct msi_msg *msg);
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extern void dmar_msi_write(int irq, struct msi_msg *msg);
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extern int dmar_set_interrupt(struct intel_iommu *iommu);
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extern int arch_setup_dmar_msi(unsigned int irq);
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/* Intel IOMMU detection and initialization functions */
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extern void detect_intel_iommu(void);
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extern int intel_iommu_init(void);
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