forked from luck/tmp_suning_uos_patched
crypto: hisilicon - add vfs_num module parameter for hpre/sec
The vfs_num module parameter has been used in zip driver, this patch adds this for HPRE and SEC driver. Signed-off-by: Hao Fang <fanghao11@huawei.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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cd1b7ae343
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@ -195,6 +195,15 @@ static u32 hpre_pf_q_num = HPRE_PF_DEF_Q_NUM;
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module_param_cb(hpre_pf_q_num, &hpre_pf_q_num_ops, &hpre_pf_q_num, 0444);
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MODULE_PARM_DESC(hpre_pf_q_num, "Number of queues in PF of CS(1-1024)");
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static const struct kernel_param_ops vfs_num_ops = {
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.set = vfs_num_set,
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.get = param_get_int,
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};
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static u32 vfs_num;
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module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444);
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MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)");
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struct hisi_qp *hpre_create_qp(void)
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{
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int node = cpu_to_node(smp_processor_id());
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@ -777,8 +786,18 @@ static int hpre_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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pci_err(pdev, "fail to register algs to crypto!\n");
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goto err_with_qm_start;
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}
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if (qm->fun_type == QM_HW_PF && vfs_num) {
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ret = hisi_qm_sriov_enable(pdev, vfs_num);
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if (ret < 0)
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goto err_with_crypto_register;
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}
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return 0;
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err_with_crypto_register:
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hpre_algs_unregister();
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err_with_qm_start:
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hisi_qm_del_from_list(qm, &hpre_devices);
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hisi_qm_stop(qm);
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@ -8,6 +8,8 @@
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#include <linux/module.h>
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#include <linux/pci.h>
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#define QM_MAX_VFS_NUM_V2 63
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/* qm user domain */
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#define QM_ARUSER_M_CFG_1 0x100088
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#define AXUSER_SNOOP_ENABLE BIT(30)
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@ -235,6 +237,24 @@ struct hisi_qp {
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struct uacce_queue *uacce_q;
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};
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static inline int vfs_num_set(const char *val, const struct kernel_param *kp)
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{
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u32 n;
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int ret;
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if (!val)
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return -EINVAL;
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ret = kstrtou32(val, 10, &n);
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if (ret < 0)
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return ret;
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if (n > QM_MAX_VFS_NUM_V2)
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return -EINVAL;
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return param_set_int(val, kp);
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}
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static inline void hisi_qm_init_list(struct hisi_qm_list *qm_list)
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{
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INIT_LIST_HEAD(&qm_list->list);
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@ -207,6 +207,15 @@ static u32 ctx_q_num = SEC_CTX_Q_NUM_DEF;
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module_param_cb(ctx_q_num, &sec_ctx_q_num_ops, &ctx_q_num, 0444);
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MODULE_PARM_DESC(ctx_q_num, "Queue num in ctx (24 default, 2, 4, ..., 32)");
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static const struct kernel_param_ops vfs_num_ops = {
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.set = vfs_num_set,
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.get = param_get_int,
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};
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static u32 vfs_num;
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module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444);
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MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)");
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void sec_destroy_qps(struct hisi_qp **qps, int qp_num)
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{
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hisi_qm_free_qps(qps, qp_num);
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@ -876,8 +885,17 @@ static int sec_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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goto err_remove_from_list;
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}
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if (qm->fun_type == QM_HW_PF && vfs_num) {
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ret = hisi_qm_sriov_enable(pdev, vfs_num);
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if (ret < 0)
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goto err_crypto_unregister;
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}
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return 0;
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err_crypto_unregister:
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sec_unregister_from_crypto();
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err_remove_from_list:
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hisi_qm_del_from_list(qm, &sec_devices);
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sec_debugfs_exit(sec);
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@ -231,9 +231,14 @@ static u32 pf_q_num = HZIP_PF_DEF_Q_NUM;
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module_param_cb(pf_q_num, &pf_q_num_ops, &pf_q_num, 0444);
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MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 1-4096, v2 1-1024)");
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static const struct kernel_param_ops vfs_num_ops = {
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.set = vfs_num_set,
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.get = param_get_int,
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};
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static u32 vfs_num;
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module_param(vfs_num, uint, 0444);
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MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63)");
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module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444);
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MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)");
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static const struct pci_device_id hisi_zip_dev_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_ZIP_PF) },
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