AcoSail/kernel_optimize_test
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Code Pull Requests Activity

Merge branch 'clk-cleanup' into clk-next

Browse Source 
* clk-cleanup:
  clk: kona-setup: Delete error messages for failed memory allocations
  ARC: clk: fix spelling mistake: "configurarion" -> "configuration"
  clk: cdce925: remove redundant check for non-null parent_name
  clk: versatile: Improve sizeof() usage
  clk: versatile: Delete error messages for failed memory allocations
  clk: ux500: Improve sizeof() usage
  clk: ux500: Delete error messages for failed memory allocations
  clk: spear: Delete error messages for failed memory allocations
  clk: ti: Delete error messages for failed memory allocations
  clk: mmp: Adjust checks for NULL pointers
  clk: mmp: Use common error handling code in mmp_clk_register_mix()
  clk: mmp: Delete error messages for failed memory allocations
  clk: clk-xgene: Adjust six checks for null pointers
  clk: clk-xgene: Delete error messages for failed memory allocations
  clk: clk-u300: Fix a typo in two comment lines
  clk: clk-u300: Add some spaces for better code readability
  clk: clk-u300: Improve sizeof() usage
  clk: clk-u300: Delete error messages for failed memory allocations
  clk: clk-mux: Improve a size determination in clk_hw_register_mux_table()
  clk: clk-mux: Delete an error message for a failed memory allocation
This commit is contained in:
Stephen Boyd 2017-11-15 08:16:13 -08:00
commit 36331641eb
22 changed files with 92 additions and 139 deletions
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7
drivers/clk/bcm/clk-kona-setup.c
View File

@ -579,18 +579,13 @@ static u32 *parent_process(const char *clocks[],
*/
parent_names = kmalloc_array(parent_count, sizeof(*parent_names),
GFP_KERNEL);
if (!parent_names) {
pr_err("%s: error allocating %u parent names\n", __func__,
parent_count);
if (!parent_names)
return ERR_PTR(-ENOMEM);
}
/* There is at least one parent, so allocate a selector array */
parent_sel = kmalloc_array(parent_count, sizeof(*parent_sel),
GFP_KERNEL);
if (!parent_sel) {
pr_err("%s: error allocating %u parent selectors\n", __func__,
parent_count);
kfree(parent_names);
return ERR_PTR(-ENOMEM);

2
drivers/clk/clk-cdce925.c
View File

@ -665,7 +665,7 @@ static int cdce925_probe(struct i2c_client *client,
init.ops = &cdce925_pll_ops;
init.flags = 0;
init.parent_names = &parent_name;
init.num_parents = parent_name ? 1 : 0;
init.num_parents = 1;
/* Register PLL clocks */
for (i = 0; i < data->chip_info->num_plls; ++i) {

4
drivers/clk/clk-hsdk-pll.c
View File

@ -139,7 +139,7 @@ static inline void hsdk_pll_set_cfg(struct hsdk_pll_clk *clk,
val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
val |= cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
dev_dbg(clk->dev, "write configurarion: %#x\n", val);
dev_dbg(clk->dev, "write configuration: %#x\n", val);
hsdk_pll_write(clk, CGU_PLL_CTRL, val);
}
@ -169,7 +169,7 @@ static unsigned long hsdk_pll_recalc_rate(struct clk_hw *hw,
val = hsdk_pll_read(clk, CGU_PLL_CTRL);
dev_dbg(clk->dev, "current configurarion: %#x\n", val);
dev_dbg(clk->dev, "current configuration: %#x\n", val);
/* Check if PLL is disabled */
if (val & CGU_PLL_CTRL_PD)

6
drivers/clk/clk-mux.c
View File

@ -134,11 +134,9 @@ struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
}
/* allocate the mux */
mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
if (!mux) {
pr_err("%s: could not allocate mux clk\n", __func__);
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
if (!mux)
return ERR_PTR(-ENOMEM);
}
init.name = name;
if (clk_mux_flags & CLK_MUX_READ_ONLY)

84
drivers/clk/clk-u300.c
View File

@ -229,15 +229,15 @@
#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0)
#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E)
#define U300_SYSCON_S0CCR_CLOCK_ENABLE (0x0001)
#define U300_SYSCON_S0CCR_SEL_MCLK (0x8<<1)
#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA<<1)
#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC<<1)
#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD<<1)
#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE<<1)
#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0<<1)
#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2<<1)
#define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4<<1)
#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6<<1)
#define U300_SYSCON_S0CCR_SEL_MCLK (0x8 << 1)
#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA << 1)
#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC << 1)
#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD << 1)
#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE << 1)
#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0 << 1)
#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2 << 1)
#define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4 << 1)
#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6 << 1)
/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
#define U300_SYSCON_S1CCR (0x124)
#define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF)
@ -247,16 +247,16 @@
#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0)
#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E)
#define U300_SYSCON_S1CCR_CLOCK_ENABLE (0x0001)
#define U300_SYSCON_S1CCR_SEL_MCLK (0x8<<1)
#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA<<1)
#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC<<1)
#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD<<1)
#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE<<1)
#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0<<1)
#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2<<1)
#define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4<<1)
#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6<<1)
/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */
#define U300_SYSCON_S1CCR_SEL_MCLK (0x8 << 1)
#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA << 1)
#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC << 1)
#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD << 1)
#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE << 1)
#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0 << 1)
#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2 << 1)
#define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4 << 1)
#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6 << 1)
/* SYS_2_CLK_CONTROL third clock control 16 bit (R/W) */
#define U300_SYSCON_S2CCR (0x128)
#define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF)
#define U300_SYSCON_S2CCR_CLK_STEAL (0x8000)
@ -266,15 +266,15 @@
#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0)
#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E)
#define U300_SYSCON_S2CCR_CLOCK_ENABLE (0x0001)
#define U300_SYSCON_S2CCR_SEL_MCLK (0x8<<1)
#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA<<1)
#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC<<1)
#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD<<1)
#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE<<1)
#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0<<1)
#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2<<1)
#define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4<<1)
#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6<<1)
#define U300_SYSCON_S2CCR_SEL_MCLK (0x8 << 1)
#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA << 1)
#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC << 1)
#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD << 1)
#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE << 1)
#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0 << 1)
#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2 << 1)
#define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4 << 1)
#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6 << 1)
/* SC_PLL_IRQ_CONTROL 16bit (R/W) */
#define U300_SYSCON_PICR (0x0130)
#define U300_SYSCON_PICR_MASK (0x00FF)
@ -378,7 +378,7 @@
* +- ISP Image Signal Processor (U335 only)
* +- CDS (U335 only)
* +- DMA Direct Memory Access Controller
* +- AAIF APP/ACC Inteface (Mobile Scalable Link, MSL)
* +- AAIF APP/ACC Interface (Mobile Scalable Link, MSL)
* +- APEX
* +- VIDEO_ENC AVE2/3 Video Encoder
* +- XGAM Graphics Accelerator Controller
@ -568,14 +568,14 @@ syscon_clk_recalc_rate(struct clk_hw *hw,
struct clk_syscon *sclk = to_syscon(hw);
u16 perf = syscon_get_perf();
switch(sclk->clk_val) {
switch (sclk->clk_val) {
case U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN:
case U300_SYSCON_SBCER_I2C0_CLK_EN:
case U300_SYSCON_SBCER_I2C1_CLK_EN:
case U300_SYSCON_SBCER_MMC_CLK_EN:
case U300_SYSCON_SBCER_SPI_CLK_EN:
/* The FAST clocks have one progression */
switch(perf) {
switch (perf) {
case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
return 13000000;
@ -586,7 +586,7 @@ syscon_clk_recalc_rate(struct clk_hw *hw,
case U300_SYSCON_SBCER_NANDIF_CLK_EN:
case U300_SYSCON_SBCER_XGAM_CLK_EN:
/* AMBA interconnect peripherals */
switch(perf) {
switch (perf) {
case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
return 6500000;
@ -598,7 +598,7 @@ syscon_clk_recalc_rate(struct clk_hw *hw,
case U300_SYSCON_SBCER_SEMI_CLK_EN:
case U300_SYSCON_SBCER_EMIF_CLK_EN:
/* EMIF speeds */
switch(perf) {
switch (perf) {
case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
return 13000000;
@ -609,7 +609,7 @@ syscon_clk_recalc_rate(struct clk_hw *hw,
}
case U300_SYSCON_SBCER_CPU_CLK_EN:
/* And the fast CPU clock */
switch(perf) {
switch (perf) {
case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
return 13000000;
@ -702,12 +702,10 @@ syscon_clk_register(struct device *dev, const char *name,
struct clk_init_data init;
int ret;
sclk = kzalloc(sizeof(struct clk_syscon), GFP_KERNEL);
if (!sclk) {
pr_err("could not allocate syscon clock %s\n",
name);
sclk = kzalloc(sizeof(*sclk), GFP_KERNEL);
if (!sclk)
return ERR_PTR(-ENOMEM);
}
init.name = name;
init.ops = &syscon_clk_ops;
init.flags = flags;
@ -1123,12 +1121,10 @@ mclk_clk_register(struct device *dev, const char *name,
struct clk_init_data init;
int ret;
mclk = kzalloc(sizeof(struct clk_mclk), GFP_KERNEL);
if (!mclk) {
pr_err("could not allocate MMC/SD clock %s\n",
name);
mclk = kzalloc(sizeof(*mclk), GFP_KERNEL);
if (!mclk)
return ERR_PTR(-ENOMEM);
}
init.name = "mclk";
init.ops = &mclk_ops;
init.flags = 0;

20
drivers/clk/clk-xgene.c
View File

@ -146,10 +146,8 @@ static struct clk *xgene_register_clk_pll(struct device *dev,
/* allocate the APM clock structure */
apmclk = kzalloc(sizeof(*apmclk), GFP_KERNEL);
if (!apmclk) {
pr_err("%s: could not allocate APM clk\n", __func__);
if (!apmclk)
return ERR_PTR(-ENOMEM);
}
init.name = name;
init.ops = &xgene_clk_pll_ops;
@ -191,7 +189,7 @@ static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_ty
int version = xgene_pllclk_version(np);
reg = of_iomap(np, 0);
if (reg == NULL) {
if (!reg) {
pr_err("Unable to map CSR register for %pOF\n", np);
return;
}
@ -467,7 +465,7 @@ static int xgene_clk_enable(struct clk_hw *hw)
if (pclk->lock)
spin_lock_irqsave(pclk->lock, flags);
if (pclk->param.csr_reg != NULL) {
if (pclk->param.csr_reg) {
pr_debug("%s clock enabled\n", clk_hw_get_name(hw));
/* First enable the clock */
data = xgene_clk_read(pclk->param.csr_reg +
@ -507,7 +505,7 @@ static void xgene_clk_disable(struct clk_hw *hw)
if (pclk->lock)
spin_lock_irqsave(pclk->lock, flags);
if (pclk->param.csr_reg != NULL) {
if (pclk->param.csr_reg) {
pr_debug("%s clock disabled\n", clk_hw_get_name(hw));
/* First put the CSR in reset */
data = xgene_clk_read(pclk->param.csr_reg +
@ -533,7 +531,7 @@ static int xgene_clk_is_enabled(struct clk_hw *hw)
struct xgene_clk *pclk = to_xgene_clk(hw);
u32 data = 0;
if (pclk->param.csr_reg != NULL) {
if (pclk->param.csr_reg) {
pr_debug("%s clock checking\n", clk_hw_get_name(hw));
data = xgene_clk_read(pclk->param.csr_reg +
pclk->param.reg_clk_offset);
@ -542,7 +540,7 @@ static int xgene_clk_is_enabled(struct clk_hw *hw)
"disabled");
}
if (pclk->param.csr_reg == NULL)
if (!pclk->param.csr_reg)
return 1;
return data & pclk->param.reg_clk_mask ? 1 : 0;
}
@ -650,10 +648,8 @@ static struct clk *xgene_register_clk(struct device *dev,
/* allocate the APM clock structure */
apmclk = kzalloc(sizeof(*apmclk), GFP_KERNEL);
if (!apmclk) {
pr_err("%s: could not allocate APM clk\n", __func__);
if (!apmclk)
return ERR_PTR(-ENOMEM);
}
init.name = name;
init.ops = &xgene_clk_ops;
@ -709,7 +705,7 @@ static void __init xgene_devclk_init(struct device_node *np)
break;
}
map_res = of_iomap(np, i);
if (map_res == NULL) {
if (!map_res) {
pr_err("Unable to map resource %d for %pOF\n", i, np);
goto err;
}

4
drivers/clk/mmp/clk-frac.c
View File

@ -172,10 +172,8 @@ struct clk *mmp_clk_register_factor(const char *name, const char *parent_name,
}
factor = kzalloc(sizeof(*factor), GFP_KERNEL);
if (!factor) {
pr_err("%s: could not allocate factor clk\n", __func__);
if (!factor)
return ERR_PTR(-ENOMEM);
}
/* struct clk_aux assignments */
factor->base = base;

4
drivers/clk/mmp/clk-gate.c
View File

@ -103,10 +103,8 @@ struct clk *mmp_clk_register_gate(struct device *dev, const char *name,
/* allocate the gate */
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
if (!gate) {
pr_err("%s:%s could not allocate gate clk\n", __func__, name);
if (!gate)
return ERR_PTR(-ENOMEM);
}
init.name = name;
init.ops = &mmp_clk_gate_ops;

27
drivers/clk/mmp/clk-mix.c
View File

@ -229,7 +229,7 @@ static int mmp_clk_mix_determine_rate(struct clk_hw *hw,
parent_rate = clk_hw_get_rate(parent);
mix_rate = parent_rate / item->divisor;
gap = abs(mix_rate - req->rate);
if (parent_best == NULL || gap < gap_best) {
if (!parent_best || gap < gap_best) {
parent_best = parent;
parent_rate_best = parent_rate;
mix_rate_best = mix_rate;
@ -247,7 +247,7 @@ static int mmp_clk_mix_determine_rate(struct clk_hw *hw,
div = _get_div(mix, j);
mix_rate = parent_rate / div;
gap = abs(mix_rate - req->rate);
if (parent_best == NULL || gap < gap_best) {
if (!parent_best || gap < gap_best) {
parent_best = parent;
parent_rate_best = parent_rate;
mix_rate_best = mix_rate;
@ -451,11 +451,8 @@ struct clk *mmp_clk_register_mix(struct device *dev,
size_t table_bytes;
mix = kzalloc(sizeof(*mix), GFP_KERNEL);
if (!mix) {
pr_err("%s:%s: could not allocate mmp mix clk\n",
__func__, name);
if (!mix)
return ERR_PTR(-ENOMEM);
}
init.name = name;
init.flags = flags | CLK_GET_RATE_NOCACHE;
@ -467,12 +464,9 @@ struct clk *mmp_clk_register_mix(struct device *dev,
if (config->table) {
table_bytes = sizeof(*config->table) * config->table_size;
mix->table = kmemdup(config->table, table_bytes, GFP_KERNEL);
if (!mix->table) {
pr_err("%s:%s: could not allocate mmp mix table\n",
__func__, name);
kfree(mix);
return ERR_PTR(-ENOMEM);
}
if (!mix->table)
goto free_mix;
mix->table_size = config->table_size;
}
@ -481,11 +475,8 @@ struct clk *mmp_clk_register_mix(struct device *dev,
mix->mux_table = kmemdup(config->mux_table, table_bytes,
GFP_KERNEL);
if (!mix->mux_table) {
pr_err("%s:%s: could not allocate mmp mix mux-table\n",
__func__, name);
kfree(mix->table);
kfree(mix);
return ERR_PTR(-ENOMEM);
goto free_mix;
}
}
@ -509,4 +500,8 @@ struct clk *mmp_clk_register_mix(struct device *dev,
}
return clk;
free_mix:
kfree(mix);
return ERR_PTR(-ENOMEM);
}

6
drivers/clk/mmp/clk-mmp2.c
View File

@ -83,19 +83,19 @@ void __init mmp2_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
void __iomem *apbc_base;
mpmu_base = ioremap(mpmu_phys, SZ_4K);
if (mpmu_base == NULL) {
if (!mpmu_base) {
pr_err("error to ioremap MPMU base\n");
return;
}
apmu_base = ioremap(apmu_phys, SZ_4K);
if (apmu_base == NULL) {
if (!apmu_base) {
pr_err("error to ioremap APMU base\n");
return;
}
apbc_base = ioremap(apbc_phys, SZ_4K);
if (apbc_base == NULL) {
if (!apbc_base) {
pr_err("error to ioremap APBC base\n");
return;
}

6
drivers/clk/mmp/clk-pxa168.c
View File

@ -75,19 +75,19 @@ void __init pxa168_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
void __iomem *apbc_base;
mpmu_base = ioremap(mpmu_phys, SZ_4K);
if (mpmu_base == NULL) {
if (!mpmu_base) {
pr_err("error to ioremap MPMU base\n");
return;
}
apmu_base = ioremap(apmu_phys, SZ_4K);
if (apmu_base == NULL) {
if (!apmu_base) {
pr_err("error to ioremap APMU base\n");
return;
}
apbc_base = ioremap(apbc_phys, SZ_4K);
if (apbc_base == NULL) {
if (!apbc_base) {
pr_err("error to ioremap APBC base\n");
return;
}

8
drivers/clk/mmp/clk-pxa910.c
View File

@ -74,25 +74,25 @@ void __init pxa910_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
void __iomem *apbc_base;
mpmu_base = ioremap(mpmu_phys, SZ_4K);
if (mpmu_base == NULL) {
if (!mpmu_base) {
pr_err("error to ioremap MPMU base\n");
return;
}
apmu_base = ioremap(apmu_phys, SZ_4K);
if (apmu_base == NULL) {
if (!apmu_base) {
pr_err("error to ioremap APMU base\n");
return;
}
apbcp_base = ioremap(apbcp_phys, SZ_4K);
if (apbcp_base == NULL) {
if (!apbcp_base) {
pr_err("error to ioremap APBC extension base\n");
return;
}
apbc_base = ioremap(apbc_phys, SZ_4K);
if (apbc_base == NULL) {
if (!apbc_base) {
pr_err("error to ioremap APBC base\n");
return;
}

4
drivers/clk/spear/clk-aux-synth.c
View File

@ -149,10 +149,8 @@ struct clk *clk_register_aux(const char *aux_name, const char *gate_name,
}
aux = kzalloc(sizeof(*aux), GFP_KERNEL);
if (!aux) {
pr_err("could not allocate aux clk\n");
if (!aux)
return ERR_PTR(-ENOMEM);
}
/* struct clk_aux assignments */
if (!masks)

4
drivers/clk/spear/clk-frac-synth.c
View File

@ -136,10 +136,8 @@ struct clk *clk_register_frac(const char *name, const char *parent_name,
}
frac = kzalloc(sizeof(*frac), GFP_KERNEL);
if (!frac) {
pr_err("could not allocate frac clk\n");
if (!frac)
return ERR_PTR(-ENOMEM);
}
/* struct clk_frac assignments */
frac->reg = reg;

4
drivers/clk/spear/clk-gpt-synth.c
View File

@ -125,10 +125,8 @@ struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned
}
gpt = kzalloc(sizeof(*gpt), GFP_KERNEL);
if (!gpt) {
pr_err("could not allocate gpt clk\n");
if (!gpt)
return ERR_PTR(-ENOMEM);
}
/* struct clk_gpt assignments */
gpt->reg = reg;

8
drivers/clk/spear/clk-vco-pll.c
View File

@ -292,16 +292,12 @@ struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name,
}
vco = kzalloc(sizeof(*vco), GFP_KERNEL);
if (!vco) {
pr_err("could not allocate vco clk\n");
if (!vco)
return ERR_PTR(-ENOMEM);
}
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
if (!pll) {
pr_err("could not allocate pll clk\n");
if (!pll)
goto free_vco;
}
/* struct clk_vco assignments */
vco->mode_reg = mode_reg;

4
drivers/clk/ti/divider.c
View File

@ -292,10 +292,8 @@ static struct clk *_register_divider(struct device *dev, const char *name,
/* allocate the divider */
div = kzalloc(sizeof(*div), GFP_KERNEL);
if (!div) {
pr_err("%s: could not allocate divider clk\n", __func__);
if (!div)
return ERR_PTR(-ENOMEM);
}
init.name = name;
init.ops = &ti_clk_divider_ops;

4
drivers/clk/ti/mux.c
View File

@ -108,10 +108,8 @@ static struct clk *_register_mux(struct device *dev, const char *name,
/* allocate the mux */
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
if (!mux) {
pr_err("%s: could not allocate mux clk\n", __func__);
if (!mux)
return ERR_PTR(-ENOMEM);
}
init.name = name;
init.ops = &ti_clk_mux_ops;

6
drivers/clk/ux500/clk-prcc.c
View File

@ -107,11 +107,9 @@ static struct clk *clk_reg_prcc(const char *name,
return ERR_PTR(-EINVAL);
}
clk = kzalloc(sizeof(struct clk_prcc), GFP_KERNEL);
if (!clk) {
pr_err("clk_prcc: %s could not allocate clk\n", __func__);
clk = kzalloc(sizeof(*clk), GFP_KERNEL);
if (!clk)
return ERR_PTR(-ENOMEM);
}
clk->base = ioremap(phy_base, SZ_4K);
if (!clk->base)

6
drivers/clk/ux500/clk-prcmu.c
View File

@ -258,11 +258,9 @@ static struct clk *clk_reg_prcmu(const char *name,
return ERR_PTR(-EINVAL);
}
clk = kzalloc(sizeof(struct clk_prcmu), GFP_KERNEL);
if (!clk) {
pr_err("clk_prcmu: %s could not allocate clk\n", __func__);
clk = kzalloc(sizeof(*clk), GFP_KERNEL);
if (!clk)
return ERR_PTR(-ENOMEM);
}
clk->cg_sel = cg_sel;
clk->is_prepared = 1;

6
drivers/clk/ux500/clk-sysctrl.c
View File

@ -139,11 +139,9 @@ static struct clk *clk_reg_sysctrl(struct device *dev,
return ERR_PTR(-EINVAL);
}
clk = devm_kzalloc(dev, sizeof(struct clk_sysctrl), GFP_KERNEL);
if (!clk) {
dev_err(dev, "clk_sysctrl: could not allocate clk\n");
clk = devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL);
if (!clk)
return ERR_PTR(-ENOMEM);
}
/* set main clock registers */
clk->reg_sel[0] = reg_sel[0];

7
drivers/clk/versatile/clk-icst.c
View File

@ -359,16 +359,13 @@ static struct clk *icst_clk_setup(struct device *dev,
struct clk_init_data init;
struct icst_params *pclone;
icst = kzalloc(sizeof(struct clk_icst), GFP_KERNEL);
if (!icst) {
pr_err("could not allocate ICST clock!\n");
icst = kzalloc(sizeof(*icst), GFP_KERNEL);
if (!icst)
return ERR_PTR(-ENOMEM);
}
pclone = kmemdup(desc->params, sizeof(*pclone), GFP_KERNEL);
if (!pclone) {
kfree(icst);
pr_err("could not clone ICST params\n");
return ERR_PTR(-ENOMEM);
}