forked from luck/tmp_suning_uos_patched
arm: eBPF JIT compiler
The JIT compiler emits ARM 32 bit instructions. Currently, It supports eBPF only. Classic BPF is supported because of the conversion by BPF core. This patch is essentially changing the current implementation of JIT compiler of Berkeley Packet Filter from classic to internal with almost all instructions from eBPF ISA supported except the following BPF_ALU64 | BPF_DIV | BPF_K BPF_ALU64 | BPF_DIV | BPF_X BPF_ALU64 | BPF_MOD | BPF_K BPF_ALU64 | BPF_MOD | BPF_X BPF_STX | BPF_XADD | BPF_W BPF_STX | BPF_XADD | BPF_DW Implementation is using scratch space to emulate 64 bit eBPF ISA on 32 bit ARM because of deficiency of general purpose registers on ARM. Currently, only LITTLE ENDIAN machines are supported in this eBPF JIT Compiler. Tested on ARMv7 with QEMU by me (Shubham Bansal). Testing results on ARMv7: 1) test_bpf: Summary: 341 PASSED, 0 FAILED, [312/333 JIT'ed] 2) test_tag: OK (40945 tests) 3) test_progs: Summary: 30 PASSED, 0 FAILED 4) test_lpm: OK 5) test_lru_map: OK Above tests are all done with following flags enabled discreatly. 1) bpf_jit_enable=1 a) CONFIG_FRAME_POINTER enabled b) CONFIG_FRAME_POINTER disabled 2) bpf_jit_enable=1 and bpf_jit_harden=2 a) CONFIG_FRAME_POINTER enabled b) CONFIG_FRAME_POINTER disabled See Documentation/networking/filter.txt for more information. Signed-off-by: Shubham Bansal <illusionist.neo@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Shubham Bansal
David S. Miller
parent
e2a7c34fb2
commit
39c13c204b
|
|
@ -50,7 +50,7 @@ config ARM
|
|||
select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
|
||||
select HAVE_ARCH_TRACEHOOK
|
||||
select HAVE_ARM_SMCCC if CPU_V7
|
||||
select HAVE_CBPF_JIT
|
||||
select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
|
||||
select HAVE_CC_STACKPROTECTOR
|
||||
select HAVE_CONTEXT_TRACKING
|
||||
select HAVE_C_RECORDMCOUNT
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -11,6 +11,7 @@
|
|||
#ifndef PFILTER_OPCODES_ARM_H
|
||||
#define PFILTER_OPCODES_ARM_H
|
||||
|
||||
/* ARM 32bit Registers */
|
||||
#define ARM_R0 0
|
||||
#define ARM_R1 1
|
||||
#define ARM_R2 2
|
||||
|
|
@ -22,38 +23,43 @@
|
|||
#define ARM_R8 8
|
||||
#define ARM_R9 9
|
||||
#define ARM_R10 10
|
||||
#define ARM_FP 11
|
||||
#define ARM_IP 12
|
||||
#define ARM_SP 13
|
||||
#define ARM_LR 14
|
||||
#define ARM_PC 15
|
||||
#define ARM_FP 11 /* Frame Pointer */
|
||||
#define ARM_IP 12 /* Intra-procedure scratch register */
|
||||
#define ARM_SP 13 /* Stack pointer: as load/store base reg */
|
||||
#define ARM_LR 14 /* Link Register */
|
||||
#define ARM_PC 15 /* Program counter */
|
||||
|
||||
#define ARM_COND_EQ 0x0
|
||||
#define ARM_COND_NE 0x1
|
||||
#define ARM_COND_CS 0x2
|
||||
#define ARM_COND_EQ 0x0 /* == */
|
||||
#define ARM_COND_NE 0x1 /* != */
|
||||
#define ARM_COND_CS 0x2 /* unsigned >= */
|
||||
#define ARM_COND_HS ARM_COND_CS
|
||||
#define ARM_COND_CC 0x3
|
||||
#define ARM_COND_CC 0x3 /* unsigned < */
|
||||
#define ARM_COND_LO ARM_COND_CC
|
||||
#define ARM_COND_MI 0x4
|
||||
#define ARM_COND_PL 0x5
|
||||
#define ARM_COND_VS 0x6
|
||||
#define ARM_COND_VC 0x7
|
||||
#define ARM_COND_HI 0x8
|
||||
#define ARM_COND_LS 0x9
|
||||
#define ARM_COND_GE 0xa
|
||||
#define ARM_COND_LT 0xb
|
||||
#define ARM_COND_GT 0xc
|
||||
#define ARM_COND_LE 0xd
|
||||
#define ARM_COND_AL 0xe
|
||||
#define ARM_COND_MI 0x4 /* < 0 */
|
||||
#define ARM_COND_PL 0x5 /* >= 0 */
|
||||
#define ARM_COND_VS 0x6 /* Signed Overflow */
|
||||
#define ARM_COND_VC 0x7 /* No Signed Overflow */
|
||||
#define ARM_COND_HI 0x8 /* unsigned > */
|
||||
#define ARM_COND_LS 0x9 /* unsigned <= */
|
||||
#define ARM_COND_GE 0xa /* Signed >= */
|
||||
#define ARM_COND_LT 0xb /* Signed < */
|
||||
#define ARM_COND_GT 0xc /* Signed > */
|
||||
#define ARM_COND_LE 0xd /* Signed <= */
|
||||
#define ARM_COND_AL 0xe /* None */
|
||||
|
||||
/* register shift types */
|
||||
#define SRTYPE_LSL 0
|
||||
#define SRTYPE_LSR 1
|
||||
#define SRTYPE_ASR 2
|
||||
#define SRTYPE_ROR 3
|
||||
#define SRTYPE_ASL (SRTYPE_LSL)
|
||||
|
||||
#define ARM_INST_ADD_R 0x00800000
|
||||
#define ARM_INST_ADDS_R 0x00900000
|
||||
#define ARM_INST_ADC_R 0x00a00000
|
||||
#define ARM_INST_ADC_I 0x02a00000
|
||||
#define ARM_INST_ADD_I 0x02800000
|
||||
#define ARM_INST_ADDS_I 0x02900000
|
||||
|
||||
#define ARM_INST_AND_R 0x00000000
|
||||
#define ARM_INST_AND_I 0x02000000
|
||||
|
|
@ -76,8 +82,10 @@
|
|||
#define ARM_INST_LDRH_I 0x01d000b0
|
||||
#define ARM_INST_LDRH_R 0x019000b0
|
||||
#define ARM_INST_LDR_I 0x05900000
|
||||
#define ARM_INST_LDR_R 0x07900000
|
||||
|
||||
#define ARM_INST_LDM 0x08900000
|
||||
#define ARM_INST_LDM_IA 0x08b00000
|
||||
|
||||
#define ARM_INST_LSL_I 0x01a00000
|
||||
#define ARM_INST_LSL_R 0x01a00010
|
||||
|
|
@ -86,6 +94,7 @@
|
|||
#define ARM_INST_LSR_R 0x01a00030
|
||||
|
||||
#define ARM_INST_MOV_R 0x01a00000
|
||||
#define ARM_INST_MOVS_R 0x01b00000
|
||||
#define ARM_INST_MOV_I 0x03a00000
|
||||
#define ARM_INST_MOVW 0x03000000
|
||||
#define ARM_INST_MOVT 0x03400000
|
||||
|
|
@ -96,17 +105,28 @@
|
|||
#define ARM_INST_PUSH 0x092d0000
|
||||
|
||||
#define ARM_INST_ORR_R 0x01800000
|
||||
#define ARM_INST_ORRS_R 0x01900000
|
||||
#define ARM_INST_ORR_I 0x03800000
|
||||
|
||||
#define ARM_INST_REV 0x06bf0f30
|
||||
#define ARM_INST_REV16 0x06bf0fb0
|
||||
|
||||
#define ARM_INST_RSB_I 0x02600000
|
||||
#define ARM_INST_RSBS_I 0x02700000
|
||||
#define ARM_INST_RSC_I 0x02e00000
|
||||
|
||||
#define ARM_INST_SUB_R 0x00400000
|
||||
#define ARM_INST_SUBS_R 0x00500000
|
||||
#define ARM_INST_RSB_R 0x00600000
|
||||
#define ARM_INST_SUB_I 0x02400000
|
||||
#define ARM_INST_SUBS_I 0x02500000
|
||||
#define ARM_INST_SBC_I 0x02c00000
|
||||
#define ARM_INST_SBC_R 0x00c00000
|
||||
#define ARM_INST_SBCS_R 0x00d00000
|
||||
|
||||
#define ARM_INST_STR_I 0x05800000
|
||||
#define ARM_INST_STRB_I 0x05c00000
|
||||
#define ARM_INST_STRH_I 0x01c000b0
|
||||
|
||||
#define ARM_INST_TST_R 0x01100000
|
||||
#define ARM_INST_TST_I 0x03100000
|
||||
|
|
@ -117,6 +137,8 @@
|
|||
|
||||
#define ARM_INST_MLS 0x00600090
|
||||
|
||||
#define ARM_INST_UXTH 0x06ff0070
|
||||
|
||||
/*
|
||||
* Use a suitable undefined instruction to use for ARM/Thumb2 faulting.
|
||||
* We need to be careful not to conflict with those used by other modules
|
||||
|
|
@ -135,9 +157,15 @@
|
|||
#define _AL3_R(op, rd, rn, rm) ((op ## _R) | (rd) << 12 | (rn) << 16 | (rm))
|
||||
/* immediate */
|
||||
#define _AL3_I(op, rd, rn, imm) ((op ## _I) | (rd) << 12 | (rn) << 16 | (imm))
|
||||
/* register with register-shift */
|
||||
#define _AL3_SR(inst) (inst | (1 << 4))
|
||||
|
||||
#define ARM_ADD_R(rd, rn, rm) _AL3_R(ARM_INST_ADD, rd, rn, rm)
|
||||
#define ARM_ADDS_R(rd, rn, rm) _AL3_R(ARM_INST_ADDS, rd, rn, rm)
|
||||
#define ARM_ADD_I(rd, rn, imm) _AL3_I(ARM_INST_ADD, rd, rn, imm)
|
||||
#define ARM_ADDS_I(rd, rn, imm) _AL3_I(ARM_INST_ADDS, rd, rn, imm)
|
||||
#define ARM_ADC_R(rd, rn, rm) _AL3_R(ARM_INST_ADC, rd, rn, rm)
|
||||
#define ARM_ADC_I(rd, rn, imm) _AL3_I(ARM_INST_ADC, rd, rn, imm)
|
||||
|
||||
#define ARM_AND_R(rd, rn, rm) _AL3_R(ARM_INST_AND, rd, rn, rm)
|
||||
#define ARM_AND_I(rd, rn, imm) _AL3_I(ARM_INST_AND, rd, rn, imm)
|
||||
|
|
@ -156,7 +184,9 @@
|
|||
#define ARM_EOR_I(rd, rn, imm) _AL3_I(ARM_INST_EOR, rd, rn, imm)
|
||||
|
||||
#define ARM_LDR_I(rt, rn, off) (ARM_INST_LDR_I | (rt) << 12 | (rn) << 16 \
|
||||
| (off))
|
||||
| ((off) & 0xfff))
|
||||
#define ARM_LDR_R(rt, rn, rm) (ARM_INST_LDR_R | (rt) << 12 | (rn) << 16 \
|
||||
| (rm))
|
||||
#define ARM_LDRB_I(rt, rn, off) (ARM_INST_LDRB_I | (rt) << 12 | (rn) << 16 \
|
||||
| (off))
|
||||
#define ARM_LDRB_R(rt, rn, rm) (ARM_INST_LDRB_R | (rt) << 12 | (rn) << 16 \
|
||||
|
|
@ -167,15 +197,23 @@
|
|||
| (rm))
|
||||
|
||||
#define ARM_LDM(rn, regs) (ARM_INST_LDM | (rn) << 16 | (regs))
|
||||
#define ARM_LDM_IA(rn, regs) (ARM_INST_LDM_IA | (rn) << 16 | (regs))
|
||||
|
||||
#define ARM_LSL_R(rd, rn, rm) (_AL3_R(ARM_INST_LSL, rd, 0, rn) | (rm) << 8)
|
||||
#define ARM_LSL_I(rd, rn, imm) (_AL3_I(ARM_INST_LSL, rd, 0, rn) | (imm) << 7)
|
||||
|
||||
#define ARM_LSR_R(rd, rn, rm) (_AL3_R(ARM_INST_LSR, rd, 0, rn) | (rm) << 8)
|
||||
#define ARM_LSR_I(rd, rn, imm) (_AL3_I(ARM_INST_LSR, rd, 0, rn) | (imm) << 7)
|
||||
#define ARM_ASR_R(rd, rn, rm) (_AL3_R(ARM_INST_ASR, rd, 0, rn) | (rm) << 8)
|
||||
#define ARM_ASR_I(rd, rn, imm) (_AL3_I(ARM_INST_ASR, rd, 0, rn) | (imm) << 7)
|
||||
|
||||
#define ARM_MOV_R(rd, rm) _AL3_R(ARM_INST_MOV, rd, 0, rm)
|
||||
#define ARM_MOVS_R(rd, rm) _AL3_R(ARM_INST_MOVS, rd, 0, rm)
|
||||
#define ARM_MOV_I(rd, imm) _AL3_I(ARM_INST_MOV, rd, 0, imm)
|
||||
#define ARM_MOV_SR(rd, rm, type, rs) \
|
||||
(_AL3_SR(ARM_MOV_R(rd, rm)) | (type) << 5 | (rs) << 8)
|
||||
#define ARM_MOV_SI(rd, rm, type, imm6) \
|
||||
(ARM_MOV_R(rd, rm) | (type) << 5 | (imm6) << 7)
|
||||
|
||||
#define ARM_MOVW(rd, imm) \
|
||||
(ARM_INST_MOVW | ((imm) >> 12) << 16 | (rd) << 12 | ((imm) & 0x0fff))
|
||||
|
|
@ -190,19 +228,38 @@
|
|||
|
||||
#define ARM_ORR_R(rd, rn, rm) _AL3_R(ARM_INST_ORR, rd, rn, rm)
|
||||
#define ARM_ORR_I(rd, rn, imm) _AL3_I(ARM_INST_ORR, rd, rn, imm)
|
||||
#define ARM_ORR_S(rd, rn, rm, type, rs) \
|
||||
(ARM_ORR_R(rd, rn, rm) | (type) << 5 | (rs) << 7)
|
||||
#define ARM_ORR_SR(rd, rn, rm, type, rs) \
|
||||
(_AL3_SR(ARM_ORR_R(rd, rn, rm)) | (type) << 5 | (rs) << 8)
|
||||
#define ARM_ORRS_R(rd, rn, rm) _AL3_R(ARM_INST_ORRS, rd, rn, rm)
|
||||
#define ARM_ORRS_SR(rd, rn, rm, type, rs) \
|
||||
(_AL3_SR(ARM_ORRS_R(rd, rn, rm)) | (type) << 5 | (rs) << 8)
|
||||
#define ARM_ORR_SI(rd, rn, rm, type, imm6) \
|
||||
(ARM_ORR_R(rd, rn, rm) | (type) << 5 | (imm6) << 7)
|
||||
#define ARM_ORRS_SI(rd, rn, rm, type, imm6) \
|
||||
(ARM_ORRS_R(rd, rn, rm) | (type) << 5 | (imm6) << 7)
|
||||
|
||||
#define ARM_REV(rd, rm) (ARM_INST_REV | (rd) << 12 | (rm))
|
||||
#define ARM_REV16(rd, rm) (ARM_INST_REV16 | (rd) << 12 | (rm))
|
||||
|
||||
#define ARM_RSB_I(rd, rn, imm) _AL3_I(ARM_INST_RSB, rd, rn, imm)
|
||||
#define ARM_RSBS_I(rd, rn, imm) _AL3_I(ARM_INST_RSBS, rd, rn, imm)
|
||||
#define ARM_RSC_I(rd, rn, imm) _AL3_I(ARM_INST_RSC, rd, rn, imm)
|
||||
|
||||
#define ARM_SUB_R(rd, rn, rm) _AL3_R(ARM_INST_SUB, rd, rn, rm)
|
||||
#define ARM_SUBS_R(rd, rn, rm) _AL3_R(ARM_INST_SUBS, rd, rn, rm)
|
||||
#define ARM_RSB_R(rd, rn, rm) _AL3_R(ARM_INST_RSB, rd, rn, rm)
|
||||
#define ARM_SBC_R(rd, rn, rm) _AL3_R(ARM_INST_SBC, rd, rn, rm)
|
||||
#define ARM_SBCS_R(rd, rn, rm) _AL3_R(ARM_INST_SBCS, rd, rn, rm)
|
||||
#define ARM_SUB_I(rd, rn, imm) _AL3_I(ARM_INST_SUB, rd, rn, imm)
|
||||
#define ARM_SUBS_I(rd, rn, imm) _AL3_I(ARM_INST_SUBS, rd, rn, imm)
|
||||
#define ARM_SBC_I(rd, rn, imm) _AL3_I(ARM_INST_SBC, rd, rn, imm)
|
||||
|
||||
#define ARM_STR_I(rt, rn, off) (ARM_INST_STR_I | (rt) << 12 | (rn) << 16 \
|
||||
| (off))
|
||||
| ((off) & 0xfff))
|
||||
#define ARM_STRH_I(rt, rn, off) (ARM_INST_STRH_I | (rt) << 12 | (rn) << 16 \
|
||||
| (((off) & 0xf0) << 4) | ((off) & 0xf))
|
||||
#define ARM_STRB_I(rt, rn, off) (ARM_INST_STRB_I | (rt) << 12 | (rn) << 16 \
|
||||
| (((off) & 0xf0) << 4) | ((off) & 0xf))
|
||||
|
||||
#define ARM_TST_R(rn, rm) _AL3_R(ARM_INST_TST, 0, rn, rm)
|
||||
#define ARM_TST_I(rn, imm) _AL3_I(ARM_INST_TST, 0, rn, imm)
|
||||
|
|
@ -214,5 +271,6 @@
|
|||
|
||||
#define ARM_MLS(rd, rn, rm, ra) (ARM_INST_MLS | (rd) << 16 | (rn) | (rm) << 8 \
|
||||
| (ra) << 12)
|
||||
#define ARM_UXTH(rd, rm) (ARM_INST_UXTH | (rd) << 12 | (rm))
|
||||
|
||||
#endif /* PFILTER_OPCODES_ARM_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user