forked from luck/tmp_suning_uos_patched
k10temp fixes
Fix race condition when accessing System Management Network registers
Fix reading critical temperatures on F15h M60h and M70h
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Merge tag 'hwmon-for-linus-v4.17-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging
Pull hwmon fixes from Guenter Roeck:
"Two k10temp fixes:
- fix race condition when accessing System Management Network
registers
- fix reading critical temperatures on F15h M60h and M70h
Also add PCI ID's for the AMD Raven Ridge root bridge"
* tag 'hwmon-for-linus-v4.17-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging:
hwmon: (k10temp) Use API function to access System Management Network
x86/amd_nb: Add support for Raven Ridge CPUs
hwmon: (k10temp) Fix reading critical temperature register
This commit is contained in:
Linus Torvalds
commit
3acf4e3952
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@ -14,8 +14,11 @@
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#include <asm/amd_nb.h>
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#define PCI_DEVICE_ID_AMD_17H_ROOT 0x1450
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#define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0
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#define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
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#define PCI_DEVICE_ID_AMD_17H_DF_F4 0x1464
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#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
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#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
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/* Protect the PCI config register pairs used for SMN and DF indirect access. */
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static DEFINE_MUTEX(smn_mutex);
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@ -24,6 +27,7 @@ static u32 *flush_words;
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static const struct pci_device_id amd_root_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_ROOT) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_ROOT) },
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{}
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};
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@ -39,6 +43,7 @@ const struct pci_device_id amd_nb_misc_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
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{}
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};
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@ -51,6 +56,7 @@ static const struct pci_device_id amd_nb_link_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
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{}
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};
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@ -272,7 +272,7 @@ config SENSORS_K8TEMP
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config SENSORS_K10TEMP
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tristate "AMD Family 10h+ temperature sensor"
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depends on X86 && PCI
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depends on X86 && PCI && AMD_NB
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help
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If you say yes here you get support for the temperature
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sensor(s) inside your CPU. Supported are later revisions of
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@ -23,6 +23,7 @@
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <asm/amd_nb.h>
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#include <asm/processor.h>
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MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
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@ -40,8 +41,8 @@ static DEFINE_MUTEX(nb_smu_ind_mutex);
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#define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
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#endif
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#ifndef PCI_DEVICE_ID_AMD_17H_RR_NB
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#define PCI_DEVICE_ID_AMD_17H_RR_NB 0x15d0
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#ifndef PCI_DEVICE_ID_AMD_17H_M10H_DF_F3
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#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
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#endif
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/* CPUID function 0x80000001, ebx */
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@ -63,10 +64,12 @@ static DEFINE_MUTEX(nb_smu_ind_mutex);
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#define NB_CAP_HTC 0x00000400
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/*
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* For F15h M60h, functionality of REG_REPORTED_TEMPERATURE
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* has been moved to D0F0xBC_xD820_0CA4 [Reported Temperature
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* Control]
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* For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL
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* and REG_REPORTED_TEMPERATURE have been moved to
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* D0F0xBC_xD820_0C64 [Hardware Temperature Control]
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* D0F0xBC_xD820_0CA4 [Reported Temperature Control]
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*/
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#define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64
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#define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
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/* F17h M01h Access througn SMN */
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@ -74,6 +77,7 @@ static DEFINE_MUTEX(nb_smu_ind_mutex);
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struct k10temp_data {
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struct pci_dev *pdev;
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void (*read_htcreg)(struct pci_dev *pdev, u32 *regval);
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void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
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int temp_offset;
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u32 temp_adjust_mask;
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@ -98,6 +102,11 @@ static const struct tctl_offset tctl_offset_table[] = {
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{ 0x17, "AMD Ryzen Threadripper 1910", 10000 },
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};
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static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval)
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{
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pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
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}
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static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
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{
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pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
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@ -114,6 +123,12 @@ static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
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mutex_unlock(&nb_smu_ind_mutex);
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}
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static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval)
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{
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amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
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F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
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}
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static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
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{
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amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
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@ -122,8 +137,8 @@ static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
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static void read_tempreg_nb_f17(struct pci_dev *pdev, u32 *regval)
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{
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amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0x60,
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F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval);
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amd_smn_read(amd_pci_dev_to_node_id(pdev),
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F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval);
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}
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static ssize_t temp1_input_show(struct device *dev,
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@ -160,8 +175,7 @@ static ssize_t show_temp_crit(struct device *dev,
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u32 regval;
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int value;
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pci_read_config_dword(data->pdev,
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REG_HARDWARE_THERMAL_CONTROL, ®val);
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data->read_htcreg(data->pdev, ®val);
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value = ((regval >> 16) & 0x7f) * 500 + 52000;
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if (show_hyst)
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value -= ((regval >> 24) & 0xf) * 500;
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@ -181,13 +195,18 @@ static umode_t k10temp_is_visible(struct kobject *kobj,
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struct pci_dev *pdev = data->pdev;
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if (index >= 2) {
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u32 reg_caps, reg_htc;
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u32 reg;
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if (!data->read_htcreg)
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return 0;
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pci_read_config_dword(pdev, REG_NORTHBRIDGE_CAPABILITIES,
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®_caps);
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pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL,
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®_htc);
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if (!(reg_caps & NB_CAP_HTC) || !(reg_htc & HTC_ENABLE))
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®);
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if (!(reg & NB_CAP_HTC))
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return 0;
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data->read_htcreg(data->pdev, ®);
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if (!(reg & HTC_ENABLE))
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return 0;
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}
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return attr->mode;
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@ -268,11 +287,13 @@ static int k10temp_probe(struct pci_dev *pdev,
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if (boot_cpu_data.x86 == 0x15 && (boot_cpu_data.x86_model == 0x60 ||
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boot_cpu_data.x86_model == 0x70)) {
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data->read_htcreg = read_htcreg_nb_f15;
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data->read_tempreg = read_tempreg_nb_f15;
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} else if (boot_cpu_data.x86 == 0x17) {
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data->temp_adjust_mask = 0x80000;
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data->read_tempreg = read_tempreg_nb_f17;
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} else {
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data->read_htcreg = read_htcreg_pci;
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data->read_tempreg = read_tempreg_pci;
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}
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@ -302,7 +323,7 @@ static const struct pci_device_id k10temp_id_table[] = {
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_RR_NB) },
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
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{}
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};
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MODULE_DEVICE_TABLE(pci, k10temp_id_table);
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