forked from luck/tmp_suning_uos_patched
The imx fixes for 3.10, take 2:
- One device tree fix for all spi node to have per clock added. The clock is needed by spi driver to calculate bit rate divisor. The spi node in the current device trees either does not have the clock or is defined as dummy clock, in which case the driver probe will fail or spi will run at a wrong bit rate. - Two imx6q clock fixes, which correct axi_sels and ldb_di_sels. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAABAgAGBQJRrLClAAoJEFBXWFqHsHzO7mIH/0zrRS+0aOdrrdL6pPWW+dua b1q5xk7vU3LU57SN6WozsfoR5zWiO3qCK5R7wvT1eYFamDryUmlNsTiFz2XG8ZdK qYVegCh86UqteSJYRBBYAuNcBjkKryPUP+Iy2PJuZKmrwNKhFfdoYYFh68th0Dc8 UcIv999Jm0JswfQ8Av4idSSMWtPwwyBm3dBEa3nI/pDdj2Wg9UmWXFml36wiEYyd CUdlcY4UenBvPIAXq0UwH4vD65Bkuz7XQqjuLtP7rgwJmVdedXYOLv59Cka5FBR9 cZoeoKl9lm+7fJVfWwTtMiW1jmE+nOh/cmCZN9aE/T1xWu8dl29h6nCOXUFCbfI= =sjAQ -----END PGP SIGNATURE----- Merge tag 'imx-fixes-3.10-2' of git://git.linaro.org/people/shawnguo/linux-2.6 into fixes From Shawn Guo, imx fixes for 3.10, take 2: - One device tree fix for all spi node to have per clock added. The clock is needed by spi driver to calculate bit rate divisor. The spi node in the current device trees either does not have the clock or is defined as dummy clock, in which case the driver probe will fail or spi will run at a wrong bit rate. - Two imx6q clock fixes, which correct axi_sels and ldb_di_sels. * tag 'imx-fixes-3.10-2' of git://git.linaro.org/people/shawnguo/linux-2.6: ARM: imx: clk-imx6q: AXI clock select index is incorrect ARM: dts: imx: fix clocks for cspi ARM i.MX6q: fix for ldb_di_sels Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
3d0d8b9155
@ -141,8 +141,8 @@ spi1: cspi@43fa4000 {
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#size-cells = <0>;
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compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
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reg = <0x43fa4000 0x4000>;
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clocks = <&clks 62>;
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clock-names = "ipg";
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clocks = <&clks 62>, <&clks 62>;
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clock-names = "ipg", "per";
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interrupts = <14>;
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status = "disabled";
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};
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@ -182,8 +182,8 @@ spi3: cspi@50004000 {
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compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
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reg = <0x50004000 0x4000>;
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interrupts = <0>;
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clocks = <&clks 80>;
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clock-names = "ipg";
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clocks = <&clks 80>, <&clks 80>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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@ -210,8 +210,8 @@ spi2: cspi@50010000 {
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#size-cells = <0>;
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compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
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reg = <0x50010000 0x4000>;
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clocks = <&clks 79>;
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clock-names = "ipg";
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clocks = <&clks 79>, <&clks 79>;
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clock-names = "ipg", "per";
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interrupts = <13>;
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status = "disabled";
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};
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@ -131,7 +131,7 @@ cspi1: cspi@1000e000 {
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compatible = "fsl,imx27-cspi";
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reg = <0x1000e000 0x1000>;
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interrupts = <16>;
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clocks = <&clks 53>, <&clks 0>;
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clocks = <&clks 53>, <&clks 53>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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@ -142,7 +142,7 @@ cspi2: cspi@1000f000 {
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compatible = "fsl,imx27-cspi";
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reg = <0x1000f000 0x1000>;
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interrupts = <15>;
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clocks = <&clks 52>, <&clks 0>;
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clocks = <&clks 52>, <&clks 52>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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@ -223,7 +223,7 @@ cspi3: cspi@10017000 {
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compatible = "fsl,imx27-cspi";
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reg = <0x10017000 0x1000>;
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interrupts = <6>;
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clocks = <&clks 51>, <&clks 0>;
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clocks = <&clks 51>, <&clks 51>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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@ -631,7 +631,7 @@ cspi: cspi@83fc0000 {
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compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
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reg = <0x83fc0000 0x4000>;
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interrupts = <38>;
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clocks = <&clks 55>, <&clks 0>;
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clocks = <&clks 55>, <&clks 55>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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@ -714,7 +714,7 @@ cspi: cspi@63fc0000 {
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compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
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reg = <0x63fc0000 0x4000>;
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interrupts = <38>;
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clocks = <&clks 55>, <&clks 0>;
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clocks = <&clks 55>, <&clks 55>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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@ -181,14 +181,14 @@ static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy",
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static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", };
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static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
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static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
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static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "pll3_pfd1_540m", };
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static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", };
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static const char *audio_sels[] = { "pll4_post_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };
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static const char *gpu_axi_sels[] = { "axi", "ahb", };
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static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };
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static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };
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static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", };
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static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
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static const char *ldb_di_sels[] = { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", };
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static const char *ldb_di_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", };
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static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
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static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
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static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
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