forked from luck/tmp_suning_uos_patched
e1000e: cleanup e1000_sw_lcd_config_ich8lan()
Do not acquire and release the PHY unnecessarily for parts that return from this workaround without actually accessing the PHY registers. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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3f0c16e844
@ -820,14 +820,6 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
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s32 ret_val = 0;
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u16 word_addr, reg_data, reg_addr, phy_page = 0;
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if (!(hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) &&
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!(hw->mac.type == e1000_pchlan))
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return ret_val;
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ret_val = hw->phy.ops.acquire(hw);
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if (ret_val)
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return ret_val;
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/*
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* Initialize the PHY from the NVM on ICH platforms. This
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* is needed due to an issue where the NVM configuration is
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@ -835,12 +827,26 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
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* Therefore, after each PHY reset, we will load the
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* configuration data out of the NVM manually.
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*/
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if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
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(adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M) ||
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(hw->mac.type == e1000_pchlan))
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switch (hw->mac.type) {
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case e1000_ich8lan:
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if (phy->type != e1000_phy_igp_3)
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return ret_val;
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if (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) {
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sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
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break;
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}
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/* Fall-thru */
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case e1000_pchlan:
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sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
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else
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sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
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break;
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default:
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return ret_val;
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}
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ret_val = hw->phy.ops.acquire(hw);
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if (ret_val)
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return ret_val;
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data = er32(FEXTNVM);
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if (!(data & sw_cfg_mask))
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