forked from luck/tmp_suning_uos_patched
powerpc/fsl: update crypto node definition and device tree instances
delete obsolete device-type property, delete model property (use compatible property instead), prepend "fsl," to Freescale specific properties. Add nodes to device trees that are missing them, and fix broken property values in other trees. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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68
Documentation/powerpc/dts-bindings/fsl/sec.txt
Normal file
68
Documentation/powerpc/dts-bindings/fsl/sec.txt
Normal file
@ -0,0 +1,68 @@
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Freescale SoC SEC Security Engines
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Required properties:
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- compatible : Should contain entries for this and backward compatible
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SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0"
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- reg : Offset and length of the register set for the device
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- interrupts : the SEC's interrupt number
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- fsl,num-channels : An integer representing the number of channels
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available.
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- fsl,channel-fifo-len : An integer representing the number of
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descriptor pointers each channel fetch fifo can hold.
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- fsl,exec-units-mask : The bitmask representing what execution units
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(EUs) are available. It's a single 32-bit cell. EU information
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should be encoded following the SEC's Descriptor Header Dword
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EU_SEL0 field documentation, i.e. as follows:
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bit 0 = reserved - should be 0
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bit 1 = set if SEC has the ARC4 EU (AFEU)
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bit 2 = set if SEC has the DES/3DES EU (DEU)
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bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A)
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bit 4 = set if SEC has the random number generator EU (RNG)
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bit 5 = set if SEC has the public key EU (PKEU)
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bit 6 = set if SEC has the AES EU (AESU)
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bit 7 = set if SEC has the Kasumi EU (KEU)
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bit 8 = set if SEC has the CRC EU (CRCU)
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bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B)
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remaining bits are reserved for future SEC EUs.
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- fsl,descriptor-types-mask : The bitmask representing what descriptors
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are available. It's a single 32-bit cell. Descriptor type information
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should be encoded following the SEC's Descriptor Header Dword DESC_TYPE
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field documentation, i.e. as follows:
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bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type
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bit 1 = set if SEC supports the ipsec_esp descriptor type
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bit 2 = set if SEC supports the common_nonsnoop desc. type
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bit 3 = set if SEC supports the 802.11i AES ccmp desc. type
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bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type
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bit 5 = set if SEC supports the srtp descriptor type
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bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type
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bit 7 = set if SEC supports the pkeu_assemble descriptor type
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bit 8 = set if SEC supports the aesu_key_expand_output desc.type
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bit 9 = set if SEC supports the pkeu_ptmul descriptor type
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bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type
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bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type
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..and so on and so forth.
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Optional properties:
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- interrupt-parent : the phandle for the interrupt controller that
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services interrupts for this device.
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Example:
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/* MPC8548E */
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crypto@30000 {
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compatible = "fsl,sec2.1", "fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <29 2>;
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interrupt-parent = <&mpic>;
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fsl,num-channels = <4>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0xfe>;
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fsl,descriptor-types-mask = <0x12b0ebf>;
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};
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@ -237,22 +237,15 @@ PIC: interrupt-controller@10c00 {
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compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic";
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};
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/* May need to remove if on a part without crypto engine */
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crypto@30000 {
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device_type = "crypto";
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model = "SEC2";
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compatible = "fsl,mpc8272-talitos-sec2",
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"fsl,talitos-sec2",
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"fsl,talitos",
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"talitos";
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reg = <0x30000 0x10000>;
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interrupts = <11 8>;
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compatible = "fsl,sec1.0";
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reg = <0x40000 0x13000>;
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interrupts = <47 0x8>;
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interrupt-parent = <&PIC>;
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num-channels = <4>;
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channel-fifo-len = <24>;
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exec-units-mask = <0x7e>;
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/* desc mask is for rev1.x, we need runtime fixup for >=2.x */
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descriptor-types-mask = <0x1010ebf>;
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fsl,num-channels = <4>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0x7e>;
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fsl,descriptor-types-mask = <0x1010415>;
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};
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};
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@ -254,17 +254,14 @@ serial1: serial@4600 {
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};
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crypto@30000 {
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device_type = "crypto";
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model = "SEC2";
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compatible = "talitos";
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reg = <0x30000 0x7000>;
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compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <11 0x8>;
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interrupt-parent = <&ipic>;
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/* Rev. 2.2 */
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num-channels = <1>;
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channel-fifo-len = <24>;
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exec-units-mask = <0x0000004c>;
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descriptor-types-mask = <0x0122003f>;
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fsl,num-channels = <1>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0x4c>;
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fsl,descriptor-types-mask = <0x0122003f>;
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};
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/* IPIC
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@ -241,17 +241,16 @@ serial1: serial@4600 {
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};
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crypto@30000 {
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model = "SEC3";
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device_type = "crypto";
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compatible = "talitos";
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compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
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"fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
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"fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <11 0x8>;
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interrupt-parent = <&ipic>;
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/* Rev. 3.0 geometry */
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num-channels = <4>;
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channel-fifo-len = <24>;
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exec-units-mask = <0x000001fe>;
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descriptor-types-mask = <0x03ab0ebf>;
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fsl,num-channels = <4>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0x97c>;
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fsl,descriptor-types-mask = <0x3ab0abf>;
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};
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sata@18000 {
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@ -150,17 +150,14 @@ dma-channel@180 {
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};
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crypto@30000 {
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device_type = "crypto";
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model = "SEC2";
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compatible = "talitos";
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reg = <0x30000 0x7000>;
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compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <11 0x8>;
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interrupt-parent = <&ipic>;
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/* Rev. 2.2 */
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num-channels = <1>;
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channel-fifo-len = <24>;
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exec-units-mask = <0x0000004c>;
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descriptor-types-mask = <0x0122003f>;
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fsl,num-channels = <1>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0x4c>;
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fsl,descriptor-types-mask = <0x0122003f>;
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};
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ipic: pic@700 {
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@ -128,17 +128,14 @@ dma-channel@180 {
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};
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crypto@30000 {
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device_type = "crypto";
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model = "SEC2";
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compatible = "talitos";
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reg = <0x30000 0x7000>;
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compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <11 0x8>;
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interrupt-parent = <&ipic>;
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/* Rev. 2.2 */
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num-channels = <1>;
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channel-fifo-len = <24>;
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exec-units-mask = <0x0000004c>;
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descriptor-types-mask = <0x0122003f>;
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fsl,num-channels = <1>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0x4c>;
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fsl,descriptor-types-mask = <0x0122003f>;
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};
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ipic:pic@700 {
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@ -213,16 +213,14 @@ serial1: serial@4600 {
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};
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crypto@30000 {
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device_type = "crypto";
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model = "SEC2";
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compatible = "talitos";
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compatible = "fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <11 0x8>;
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interrupt-parent = <&ipic>;
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num-channels = <4>;
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channel-fifo-len = <24>;
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exec-units-mask = <0x0000007e>;
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descriptor-types-mask = <0x01010ebf>;
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fsl,num-channels = <4>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0x7e>;
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fsl,descriptor-types-mask = <0x01010ebf>;
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};
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ipic: pic@700 {
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@ -186,16 +186,14 @@ serial1: serial@4600 {
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};
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crypto@30000 {
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device_type = "crypto";
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model = "SEC2";
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compatible = "talitos";
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compatible = "fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <11 0x8>;
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interrupt-parent = <&ipic>;
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num-channels = <4>;
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channel-fifo-len = <24>;
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exec-units-mask = <0x0000007e>;
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descriptor-types-mask = <0x01010ebf>;
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fsl,num-channels = <4>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0x7e>;
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fsl,descriptor-types-mask = <0x01010ebf>;
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};
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ipic: pic@700 {
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@ -228,20 +228,15 @@ serial1: serial@4600 {
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interrupt-parent = <&ipic>;
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};
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/* May need to remove if on a part without crypto engine */
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crypto@30000 {
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device_type = "crypto";
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model = "SEC2";
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compatible = "talitos";
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compatible = "fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <11 0x8>;
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interrupt-parent = <&ipic>;
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num-channels = <4>;
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channel-fifo-len = <24>;
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exec-units-mask = <0x0000007e>;
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/* desc mask is for rev2.0,
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* we need runtime fixup for >2.0 */
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descriptor-types-mask = <0x01010ebf>;
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fsl,num-channels = <4>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0x7e>;
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fsl,descriptor-types-mask = <0x01010ebf>;
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};
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/* IPIC
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@ -154,17 +154,14 @@ dma-channel@180 {
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};
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crypto@30000 {
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device_type = "crypto";
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model = "SEC2";
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compatible = "talitos";
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compatible = "fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <11 0x8>;
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interrupt-parent = <&ipic>;
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num-channels = <4>;
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channel-fifo-len = <24>;
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exec-units-mask = <0x0000007e>;
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/* desc mask is for rev1.x, we need runtime fixup for >=2.x */
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descriptor-types-mask = <0x01010ebf>;
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fsl,num-channels = <4>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0x7e>;
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fsl,descriptor-types-mask = <0x01010ebf>;
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};
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ipic: pic@700 {
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@ -269,16 +269,15 @@ dma-channel@180 {
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};
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crypto@30000 {
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model = "SEC3";
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compatible = "talitos";
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compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
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"fsl,sec2.1", "fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <11 0x8>;
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interrupt-parent = <&ipic>;
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/* Rev. 3.0 geometry */
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num-channels = <4>;
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channel-fifo-len = <24>;
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exec-units-mask = <0x000001fe>;
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descriptor-types-mask = <0x03ab0ebf>;
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fsl,num-channels = <4>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0x9fe>;
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fsl,descriptor-types-mask = <0x3ab0ebf>;
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};
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sdhc@2e000 {
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@ -248,17 +248,15 @@ serial1: serial@4600 {
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};
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crypto@30000 {
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model = "SEC3";
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device_type = "crypto";
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compatible = "talitos";
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compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
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"fsl,sec2.1", "fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <11 0x8>;
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interrupt-parent = <&ipic>;
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/* Rev. 3.0 geometry */
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num-channels = <4>;
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channel-fifo-len = <24>;
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exec-units-mask = <0x000001fe>;
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descriptor-types-mask = <0x03ab0ebf>;
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fsl,num-channels = <4>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0x9fe>;
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fsl,descriptor-types-mask = <0x3ab0ebf>;
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};
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sata@18000 {
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@ -269,16 +269,15 @@ serial1: serial@4600 {
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};
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crypto@30000 {
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model = "SEC3";
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compatible = "talitos";
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compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
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"fsl,sec2.1", "fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <11 0x8>;
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interrupt-parent = <&ipic>;
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/* Rev. 3.0 geometry */
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num-channels = <4>;
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channel-fifo-len = <24>;
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exec-units-mask = <0x000001fe>;
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descriptor-types-mask = <0x03ab0ebf>;
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fsl,num-channels = <4>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0x9fe>;
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fsl,descriptor-types-mask = <0x3ab0ebf>;
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};
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sdhc@2e000 {
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@ -248,17 +248,15 @@ serial1: serial@4600 {
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};
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crypto@30000 {
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model = "SEC3";
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device_type = "crypto";
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compatible = "talitos";
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compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
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"fsl,sec2.1", "fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <11 0x8>;
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interrupt-parent = <&ipic>;
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/* Rev. 3.0 geometry */
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num-channels = <4>;
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channel-fifo-len = <24>;
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exec-units-mask = <0x000001fe>;
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descriptor-types-mask = <0x03ab0ebf>;
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fsl,num-channels = <4>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0x9fe>;
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fsl,descriptor-types-mask = <0x3ab0ebf>;
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};
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/* IPIC
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@ -269,16 +269,15 @@ serial1: serial@4600 {
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};
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crypto@30000 {
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model = "SEC3";
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compatible = "talitos";
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compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
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"fsl,sec2.1", "fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <11 0x8>;
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interrupt-parent = <&ipic>;
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/* Rev. 3.0 geometry */
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num-channels = <4>;
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channel-fifo-len = <24>;
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exec-units-mask = <0x000001fe>;
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descriptor-types-mask = <0x03ab0ebf>;
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fsl,num-channels = <4>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0x9fe>;
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fsl,descriptor-types-mask = <0x3ab0ebf>;
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};
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sdhc@2e000 {
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@ -248,17 +248,15 @@ serial1: serial@4600 {
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};
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crypto@30000 {
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model = "SEC3";
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device_type = "crypto";
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compatible = "talitos";
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compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
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"fsl,sec2.1", "fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <11 0x8>;
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interrupt-parent = <&ipic>;
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/* Rev. 3.0 geometry */
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num-channels = <4>;
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channel-fifo-len = <24>;
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exec-units-mask = <0x000001fe>;
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descriptor-types-mask = <0x03ab0ebf>;
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fsl,num-channels = <4>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0x9fe>;
|
||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||
};
|
||||
|
||||
sata@18000 {
|
||||
|
@ -231,6 +231,18 @@ serial1: serial@4600 {
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
|
||||
"fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2 58 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x9fe>;
|
||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||
};
|
||||
|
||||
sata@18000 {
|
||||
compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
|
||||
reg = <0x18000 0x1000>;
|
||||
|
@ -189,6 +189,17 @@ serial1: serial@4600 {
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x7e>;
|
||||
fsl,descriptor-types-mask = <0x01010ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
|
@ -210,6 +210,17 @@ global-utilities@e0000 { //global utilities block
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0xfe>;
|
||||
fsl,descriptor-types-mask = <0x12b0ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
|
@ -249,6 +249,17 @@ global-utilities@e0000 { //global utilities reg
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0xfe>;
|
||||
fsl,descriptor-types-mask = <0x12b0ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
|
@ -189,6 +189,17 @@ serial1: serial@4600 {
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x7e>;
|
||||
fsl,descriptor-types-mask = <0x01010ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
|
@ -231,16 +231,14 @@ serial1: serial@4600 {
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
device_type = "crypto";
|
||||
model = "SEC2";
|
||||
compatible = "talitos";
|
||||
reg = <0x30000 0xf000>;
|
||||
compatible = "fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0xfe>;
|
||||
descriptor-types-mask = <0x12b0ebf>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0xfe>;
|
||||
fsl,descriptor-types-mask = <0x12b0ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
|
@ -321,6 +321,18 @@ msi@41600 {
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
|
||||
"fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2 58 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x9fe>;
|
||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
|
@ -221,19 +221,15 @@ serial1: serial@4600 {
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
/* May need to remove if on a part without crypto engine */
|
||||
crypto@30000 {
|
||||
model = "SEC2";
|
||||
compatible = "talitos";
|
||||
compatible = "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x0000007e>;
|
||||
/* desc mask is for rev2.0,
|
||||
* we need runtime fixup for >2.0 */
|
||||
descriptor-types-mask = <0x01010ebf>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x7e>;
|
||||
fsl,descriptor-types-mask = <0x01010ebf>;
|
||||
};
|
||||
|
||||
/* IPIC
|
||||
|
@ -304,6 +304,17 @@ global-utilities@e0000 { //global utilities reg
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0xfe>;
|
||||
fsl,descriptor-types-mask = <0x12b0ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
|
@ -200,6 +200,17 @@ serial1: serial@4600 {
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x7e>;
|
||||
fsl,descriptor-types-mask = <0x01010ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
|
@ -200,6 +200,17 @@ serial1: serial@4600 {
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x7e>;
|
||||
fsl,descriptor-types-mask = <0x01010ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
|
Loading…
Reference in New Issue
Block a user