forked from luck/tmp_suning_uos_patched
perf/x86/intel: Implement support for TSX Force Abort
Skylake (and later) will receive a microcode update to address a TSX errata. This microcode will, on execution of a TSX instruction (speculative or not) use (clobber) PMC3. This update will also provide a new MSR to change this behaviour along with a CPUID bit to enumerate the presence of this new MSR. When the MSR gets set; the microcode will no longer use PMC3 but will Force Abort every TSX transaction (upon executing COMMIT). When TSX Force Abort (TFA) is allowed (default); the MSR gets set when PMC3 gets scheduled and cleared when, after scheduling, PMC3 is unused. When TFA is not allowed; clear PMC3 from all constraints such that it will not get used. Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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52f6490940
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400816f60c
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@ -1999,6 +1999,39 @@ static void intel_pmu_nhm_enable_all(int added)
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intel_pmu_enable_all(added);
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}
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static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on)
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{
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u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0;
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if (cpuc->tfa_shadow != val) {
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cpuc->tfa_shadow = val;
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wrmsrl(MSR_TSX_FORCE_ABORT, val);
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}
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}
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static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
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{
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/*
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* We're going to use PMC3, make sure TFA is set before we touch it.
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*/
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if (cntr == 3 && !cpuc->is_fake)
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intel_set_tfa(cpuc, true);
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}
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static void intel_tfa_pmu_enable_all(int added)
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{
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struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
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/*
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* If we find PMC3 is no longer used when we enable the PMU, we can
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* clear TFA.
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*/
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if (!test_bit(3, cpuc->active_mask))
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intel_set_tfa(cpuc, false);
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intel_pmu_enable_all(added);
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}
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static void enable_counter_freeze(void)
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{
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update_debugctlmsr(get_debugctlmsr() |
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@ -3354,6 +3387,26 @@ glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
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return c;
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}
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static bool allow_tsx_force_abort = true;
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static struct event_constraint *
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tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
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struct perf_event *event)
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{
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struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event);
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/*
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* Without TFA we must not use PMC3.
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*/
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if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) {
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c = dyn_constraint(cpuc, c, idx);
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c->idxmsk64 &= ~(1ULL << 3);
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c->weight--;
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}
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return c;
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}
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/*
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* Broadwell:
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*
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@ -3448,13 +3501,15 @@ int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
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goto err;
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}
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if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
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if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) {
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size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
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cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu));
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if (!cpuc->constraint_list)
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goto err_shared_regs;
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}
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if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
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cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
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if (!cpuc->excl_cntrs)
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goto err_constraint_list;
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@ -3564,9 +3619,10 @@ static void free_excl_cntrs(struct cpu_hw_events *cpuc)
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if (c->core_id == -1 || --c->refcnt == 0)
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kfree(c);
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cpuc->excl_cntrs = NULL;
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kfree(cpuc->constraint_list);
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cpuc->constraint_list = NULL;
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}
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kfree(cpuc->constraint_list);
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cpuc->constraint_list = NULL;
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}
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static void intel_pmu_cpu_dying(int cpu)
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@ -4086,8 +4142,11 @@ static struct attribute *intel_pmu_caps_attrs[] = {
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NULL
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};
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DEVICE_BOOL_ATTR(allow_tsx_force_abort, 0644, allow_tsx_force_abort);
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static struct attribute *intel_pmu_attrs[] = {
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&dev_attr_freeze_on_smi.attr,
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NULL, /* &dev_attr_allow_tsx_force_abort.attr.attr */
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NULL,
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};
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@ -4580,6 +4639,15 @@ __init int intel_pmu_init(void)
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tsx_attr = hsw_tsx_events_attrs;
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intel_pmu_pebs_data_source_skl(
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boot_cpu_data.x86_model == INTEL_FAM6_SKYLAKE_X);
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if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) {
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x86_pmu.flags |= PMU_FL_TFA;
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x86_pmu.get_event_constraints = tfa_get_event_constraints;
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x86_pmu.enable_all = intel_tfa_pmu_enable_all;
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x86_pmu.commit_scheduling = intel_tfa_commit_scheduling;
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intel_pmu_attrs[1] = &dev_attr_allow_tsx_force_abort.attr.attr;
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}
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pr_cont("Skylake events, ");
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name = "skylake";
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break;
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@ -242,6 +242,11 @@ struct cpu_hw_events {
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struct intel_excl_cntrs *excl_cntrs;
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int excl_thread_id; /* 0 or 1 */
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/*
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* SKL TSX_FORCE_ABORT shadow
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*/
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u64 tfa_shadow;
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/*
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* AMD specific bits
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*/
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@ -681,6 +686,7 @@ do { \
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#define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */
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#define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */
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#define PMU_FL_PEBS_ALL 0x10 /* all events are valid PEBS events */
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#define PMU_FL_TFA 0x20 /* deal with TSX force abort */
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#define EVENT_VAR(_id) event_attr_##_id
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#define EVENT_PTR(_id) &event_attr_##_id.attr.attr
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