forked from luck/tmp_suning_uos_patched
ALSA: hda: Add dma stop delay variable
A variable dma_stop_delay is added as a new member in hdac_bus structure to avoid memory decode error incase DMA RUN bit is not disabled in the given timeout from snd_hdac_stream_sync function and followed by stream reset which results in memory decode error between reset set and clear operation. Signed-off-by: Mohan Kumar <mkumard@nvidia.com> Link: https://lore.kernel.org/r/20200805095221.5476-3-mkumard@nvidia.com Signed-off-by: Takashi Iwai <tiwai@suse.de>
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@ -347,6 +347,9 @@ struct hdac_bus {
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int bdl_pos_adj; /* BDL position adjustment */
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/* delay time in us for dma stop */
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unsigned int dma_stop_delay;
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/* locks */
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spinlock_t reg_lock;
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struct mutex cmd_mutex;
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@ -150,9 +150,12 @@ void snd_hdac_stream_reset(struct hdac_stream *azx_dev)
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{
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unsigned char val;
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int timeout;
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int dma_run_state;
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snd_hdac_stream_clear(azx_dev);
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dma_run_state = snd_hdac_stream_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START;
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snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
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udelay(3);
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timeout = 300;
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@ -162,6 +165,10 @@ void snd_hdac_stream_reset(struct hdac_stream *azx_dev)
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if (val)
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break;
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} while (--timeout);
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if (azx_dev->bus->dma_stop_delay && dma_run_state)
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udelay(azx_dev->bus->dma_stop_delay);
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val &= ~SD_CTL_STREAM_RESET;
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snd_hdac_stream_writeb(azx_dev, SD_CTL, val);
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udelay(3);
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