forked from luck/tmp_suning_uos_patched
Reset controller changes for v5.4
This tag adds support for the i.MX8MM SRC via the reset-imx7 driver and for DesignWare IP reset controllers via the reset-simple driver. A typo in the i.MX8MQ DSI reset definitions is fixed, and the Meson reset driver and binding headers are updated to SPDX license identifiers. -----BEGIN PGP SIGNATURE----- iI0EABYIADUWIQRRO6F6WdpH1R0vGibVhaclGDdiwAUCXVE2PxcccC56YWJlbEBw ZW5ndXRyb25peC5kZQAKCRDVhaclGDdiwP2dAQCPcwxmyNt9DeRTcHMsZ/8WpROG 8dNLl6lGJIRHBon+wAD/ZGO7GI3YLgghInSWurSn2w3VjqB9yjrEiYjCOt3LkAg= =hIhK -----END PGP SIGNATURE----- Merge tag 'reset-for-v5.4' of git://git.pengutronix.de/git/pza/linux into arm/drivers Reset controller changes for v5.4 This tag adds support for the i.MX8MM SRC via the reset-imx7 driver and for DesignWare IP reset controllers via the reset-simple driver. A typo in the i.MX8MQ DSI reset definitions is fixed, and the Meson reset driver and binding headers are updated to SPDX license identifiers. * tag 'reset-for-v5.4' of git://git.pengutronix.de/git/pza/linux: reset: Add DesignWare IP support to simple reset dt-bindings: Document the DesignWare IP reset bindings dt-bindings: reset: amlogic,meson8b-reset: update with SPDX Licence identifier dt-bindings: reset: amlogic,meson-gxbb-reset: update with SPDX Licence identifier reset: reset-meson: update with SPDX Licence identifier dt-bindings: reset: Fix typo in imx8mq resets dt-bindings: reset: imx7: Add support for i.MX8MM Link: https://lore.kernel.org/r/1565603668.5017.2.camel@pengutronix.de Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
428cb860c4
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@ -8,6 +8,7 @@ Required properties:
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- compatible:
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- For i.MX7 SoCs should be "fsl,imx7d-src", "syscon"
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- For i.MX8MQ SoCs should be "fsl,imx8mq-src", "syscon"
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- For i.MX8MM SoCs should be "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"
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- reg: should be register base and length as documented in the
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datasheet
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- interrupts: Should contain SRC interrupt
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@ -46,5 +47,6 @@ Example:
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For list of all valid reset indices see
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<dt-bindings/reset/imx7-reset.h> for i.MX7 and
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<dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ
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<dt-bindings/reset/imx7-reset.h> for i.MX7,
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<dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ and
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<dt-bindings/reset/imx8mq-reset.h> for i.MX8MM
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30
Documentation/devicetree/bindings/reset/snps,dw-reset.txt
Normal file
30
Documentation/devicetree/bindings/reset/snps,dw-reset.txt
Normal file
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@ -0,0 +1,30 @@
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Synopsys DesignWare Reset controller
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=======================================
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Please also refer to reset.txt in this directory for common reset
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controller binding usage.
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Required properties:
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- compatible: should be one of the following.
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"snps,dw-high-reset" - for active high configuration
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"snps,dw-low-reset" - for active low configuration
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #reset-cells: must be 1.
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example:
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dw_rst_1: reset-controller@0000 {
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compatible = "snps,dw-high-reset";
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reg = <0x0000 0x4>;
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#reset-cells = <1>;
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};
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dw_rst_2: reset-controller@1000 {i
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compatible = "snps,dw-low-reset";
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reg = <0x1000 0x8>;
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#reset-cells = <1>;
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};
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@ -118,7 +118,7 @@ config RESET_QCOM_PDC
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config RESET_SIMPLE
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bool "Simple Reset Controller Driver" if COMPILE_TEST
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default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED || ARCH_BITMAIN
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default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED || ARCH_BITMAIN || ARC
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help
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This enables a simple reset controller driver for reset lines that
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that can be asserted and deasserted by toggling bits in a contiguous,
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@ -169,9 +169,9 @@ static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = {
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[IMX8MQ_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) },
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[IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N] = { SRC_MIPIPHY_RCR, BIT(1) },
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[IMX8MQ_RESET_MIPI_DSI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(2) },
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[IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(3) },
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[IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N] = { SRC_MIPIPHY_RCR, BIT(4) },
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[IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N] = { SRC_MIPIPHY_RCR, BIT(5) },
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[IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(3) },
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[IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N] = { SRC_MIPIPHY_RCR, BIT(4) },
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[IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N] = { SRC_MIPIPHY_RCR, BIT(5) },
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[IMX8MQ_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR,
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BIT(2) | BIT(1) },
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[IMX8MQ_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
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@ -220,9 +220,9 @@ static int imx8mq_reset_set(struct reset_controller_dev *rcdev,
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case IMX8MQ_RESET_PCIE_CTRL_APPS_EN:
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case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN: /* fallthrough */
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case IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N: /* fallthrough */
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case IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N: /* fallthrough */
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case IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N: /* fallthrough */
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case IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N: /* fallthrough */
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case IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N: /* fallthrough */
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case IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N: /* fallthrough */
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case IMX8MQ_RESET_MIPI_DSI_RESET_N: /* fallthrough */
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case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N: /* fallthrough */
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value = assert ? 0 : bit;
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@ -1,58 +1,9 @@
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/*
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* Amlogic Meson Reset Controller driver
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright (c) 2016 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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* The full GNU General Public License is included in this distribution
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* in the file called COPYING.
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*
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* BSD LICENSE
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*
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* Copyright (c) 2016 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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@ -127,6 +127,9 @@ static const struct of_device_id reset_simple_dt_ids[] = {
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{ .compatible = "aspeed,ast2500-lpc-reset" },
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{ .compatible = "bitmain,bm1880-reset",
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.data = &reset_simple_active_low },
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{ .compatible = "snps,dw-high-reset" },
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{ .compatible = "snps,dw-low-reset",
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.data = &reset_simple_active_low },
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{ /* sentinel */ },
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};
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@ -1,56 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright (c) 2016 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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* The full GNU General Public License is included in this distribution
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* in the file called COPYING.
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*
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* BSD LICENSE
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*
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* Copyright (c) 2016 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
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#define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
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@ -1,56 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright (c) 2016 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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||||
* along with this program; if not, see <http://www.gnu.org/licenses/>.
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* The full GNU General Public License is included in this distribution
|
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* in the file called COPYING.
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*
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* BSD LICENSE
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*
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* Copyright (c) 2016 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* Redistribution and use in source and binary forms, with or without
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||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
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* distribution.
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||||
* * Neither the name of Intel Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
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#ifndef _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H
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#define _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H
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@ -31,33 +31,33 @@
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#define IMX8MQ_RESET_OTG2_PHY_RESET 20
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#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21
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#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22
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#define IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N 23
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#define IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N 24
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#define IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N 25
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#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23
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#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24
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#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25
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#define IMX8MQ_RESET_PCIEPHY 26
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#define IMX8MQ_RESET_PCIEPHY_PERST 27
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#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28
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#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29
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#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30
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#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM does NOT support */
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#define IMX8MQ_RESET_DISP_RESET 31
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#define IMX8MQ_RESET_GPU_RESET 32
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#define IMX8MQ_RESET_VPU_RESET 33
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#define IMX8MQ_RESET_PCIEPHY2 34
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#define IMX8MQ_RESET_PCIEPHY2_PERST 35
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#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36
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#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37
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#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38
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#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39
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#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40
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#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41
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#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42
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#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43
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#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM does NOT support */
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#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM does NOT support */
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#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM does NOT support */
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#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM does NOT support */
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#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM does NOT support */
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#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM does NOT support */
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#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM does NOT support */
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#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM does NOT support */
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#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM does NOT support */
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#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM does NOT support */
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#define IMX8MQ_RESET_DDRC1_PRST 44
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#define IMX8MQ_RESET_DDRC1_CORE_RESET 45
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#define IMX8MQ_RESET_DDRC1_PHY_RESET 46
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#define IMX8MQ_RESET_DDRC2_PRST 47
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#define IMX8MQ_RESET_DDRC2_CORE_RESET 48
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#define IMX8MQ_RESET_DDRC2_PHY_RESET 49
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#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM does NOT support */
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#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM does NOT support */
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#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM does NOT support */
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#define IMX8MQ_RESET_NUM 50
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|
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Block a user