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Merge branch 'for_david' of git://git.kernel.org/pub/scm/linux/kernel/git/kkeil/ISDN-2.6-net-next

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This commit is contained in:
David S. Miller 2009-07-26 10:00:21 -07:00
commit 436b355b96
52 changed files with 10356 additions and 462 deletions
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6
drivers/isdn/Kconfig
View File

@ -21,8 +21,6 @@ menuconfig ISDN
if ISDN
source "drivers/isdn/mISDN/Kconfig"
menuconfig ISDN_I4L
tristate "Old ISDN4Linux (deprecated)"
---help---
@ -41,9 +39,9 @@ menuconfig ISDN_I4L
It is still available, though, for use with adapters that are not
supported by the new CAPI subsystem yet.
if ISDN_I4L
source "drivers/isdn/mISDN/Kconfig"
source "drivers/isdn/i4l/Kconfig"
endif
menuconfig ISDN_CAPI
tristate "CAPI 2.0 subsystem"

3
drivers/isdn/act2000/capi.c
View File

@ -78,7 +78,6 @@ static actcapi_msgdsc valid_msg[] = {
#endif
{{ 0x00, 0x00}, NULL},
};
#define num_valid_msg (sizeof(valid_msg)/sizeof(actcapi_msgdsc))
#define num_valid_imsg 27 /* MANUFACTURER_IND */
/*
@ -1025,7 +1024,7 @@ actcapi_debug_msg(struct sk_buff *skb, int direction)
#ifdef DEBUG_DUMP_SKB
dump_skb(skb);
#endif
for (i = 0; i < num_valid_msg; i++)
for (i = 0; i < ARRAY_SIZE(valid_msg); i++)
if ((msg->hdr.cmd.cmd == valid_msg[i].cmd.cmd) &&
(msg->hdr.cmd.subcmd == valid_msg[i].cmd.subcmd)) {
descr = valid_msg[i].description;

31
drivers/isdn/act2000/module.c
View File

@ -23,7 +23,6 @@ static unsigned short act2000_isa_ports[] =
0x0200, 0x0240, 0x0280, 0x02c0, 0x0300, 0x0340, 0x0380,
0xcfe0, 0xcfa0, 0xcf60, 0xcf20, 0xcee0, 0xcea0, 0xce60,
};
#define ISA_NRPORTS (sizeof(act2000_isa_ports)/sizeof(unsigned short))
static act2000_card *cards = (act2000_card *) NULL;
@ -686,21 +685,21 @@ act2000_addcard(int bus, int port, int irq, char *id)
* This may result in more than one card detected.
*/
switch (bus) {
case ACT2000_BUS_ISA:
for (i = 0; i < ISA_NRPORTS; i++)
if (act2000_isa_detect(act2000_isa_ports[i])) {
printk(KERN_INFO
"act2000: Detected ISA card at port 0x%x\n",
act2000_isa_ports[i]);
act2000_alloccard(bus, act2000_isa_ports[i], irq, id);
}
break;
case ACT2000_BUS_MCA:
case ACT2000_BUS_PCMCIA:
default:
printk(KERN_WARNING
"act2000: addcard: Invalid BUS type %d\n",
bus);
case ACT2000_BUS_ISA:
for (i = 0; i < ARRAY_SIZE(act2000_isa_ports); i++)
if (act2000_isa_detect(act2000_isa_ports[i])) {
printk(KERN_INFO "act2000: Detected "
"ISA card at port 0x%x\n",
act2000_isa_ports[i]);
act2000_alloccard(bus,
act2000_isa_ports[i], irq, id);
}
break;
case ACT2000_BUS_MCA:
case ACT2000_BUS_PCMCIA:
default:
printk(KERN_WARNING
"act2000: addcard: Invalid BUS type %d\n", bus);
}
}
if (!cards)

4
drivers/isdn/hardware/eicon/message.c
View File

@ -551,9 +551,7 @@ word api_put(APPL * appl, CAPI_MSG * msg)
dbug(1,dprintf("com=%x",msg->header.command));
for(j=0;j<MAX_MSG_PARMS+1;j++) msg_parms[j].length = 0;
for(i=0, ret = _BAD_MSG;
i<(sizeof(ftable)/sizeof(struct _ftable));
i++) {
for(i=0, ret = _BAD_MSG; i < ARRAY_SIZE(ftable); i++) {
if(ftable[i].command==msg->header.command) {
/* break loop if the message is correct, otherwise continue scan */

3
drivers/isdn/hardware/eicon/os_4bri.c
View File

@ -149,8 +149,7 @@ int diva_4bri_init_card(diva_os_xdi_adapter_t * a)
diva_os_xdi_adapter_t *diva_current;
diva_os_xdi_adapter_t *adapter_list[4];
PISDN_ADAPTER Slave;
unsigned long bar_length[sizeof(_4bri_bar_length) /
sizeof(_4bri_bar_length[0])];
unsigned long bar_length[ARRAY_SIZE(_4bri_bar_length)];
int v2 = _4bri_is_rev_2_card(a->CardOrdinal);
int tasks = _4bri_is_rev_2_bri_card(a->CardOrdinal) ? 1 : MQ_INSTANCE_COUNT;
int factor = (tasks == 1) ? 1 : 2;

51
drivers/isdn/hardware/mISDN/Kconfig
View File

@ -39,3 +39,54 @@ config MISDN_HFCUSB
Enable support for USB ISDN TAs with Cologne Chip AG's
HFC-S USB ISDN Controller
config MISDN_AVMFRITZ
tristate "Support for AVM FRITZ!CARD PCI"
depends on MISDN
depends on PCI
select MISDN_IPAC
help
Enable support for AVMs FRITZ!CARD PCI cards
config MISDN_SPEEDFAX
tristate "Support for Sedlbauer Speedfax+"
depends on MISDN
depends on PCI
select MISDN_IPAC
select MISDN_ISAR
help
Enable support for Sedlbauer Speedfax+.
config MISDN_INFINEON
tristate "Support for cards with Infineon chipset"
depends on MISDN
depends on PCI
select MISDN_IPAC
help
Enable support for cards with ISAC + HSCX, IPAC or IPAC-SX
chip from Infineon (former manufacturer Siemens).
config MISDN_W6692
tristate "Support for cards with Winbond 6692"
depends on MISDN
depends on PCI
help
Enable support for Winbond 6692 PCI chip based cards.
config MISDN_NETJET
tristate "Support for NETJet cards"
depends on MISDN
depends on PCI
select MISDN_IPAC
select ISDN_HDLC
help
Enable support for Traverse Technologies NETJet PCI cards.
config MISDN_IPAC
tristate
depends on MISDN
config MISDN_ISAR
tristate
depends on MISDN

8
drivers/isdn/hardware/mISDN/Makefile
View File

@ -6,3 +6,11 @@
obj-$(CONFIG_MISDN_HFCPCI) += hfcpci.o
obj-$(CONFIG_MISDN_HFCMULTI) += hfcmulti.o
obj-$(CONFIG_MISDN_HFCUSB) += hfcsusb.o
obj-$(CONFIG_MISDN_AVMFRITZ) += avmfritz.o
obj-$(CONFIG_MISDN_SPEEDFAX) += speedfax.o
obj-$(CONFIG_MISDN_INFINEON) += mISDNinfineon.o
obj-$(CONFIG_MISDN_W6692) += w6692.o
obj-$(CONFIG_MISDN_NETJET) += netjet.o
# chip modules
obj-$(CONFIG_MISDN_IPAC) += mISDNipac.o
obj-$(CONFIG_MISDN_ISAR) += mISDNisar.o

1152
drivers/isdn/hardware/mISDN/avmfritz.c Normal file
View File

File diff suppressed because it is too large Load Diff

23
drivers/isdn/hardware/mISDN/hfcmulti.c
View File

@ -3416,22 +3416,8 @@ deactivate_bchannel(struct bchannel *bch)
u_long flags;
spin_lock_irqsave(&hc->lock, flags);
if (test_and_clear_bit(FLG_TX_NEXT, &bch->Flags)) {
dev_kfree_skb(bch->next_skb);
bch->next_skb = NULL;
}
if (bch->tx_skb) {
dev_kfree_skb(bch->tx_skb);
bch->tx_skb = NULL;
}
bch->tx_idx = 0;
if (bch->rx_skb) {
dev_kfree_skb(bch->rx_skb);
bch->rx_skb = NULL;
}
mISDN_clear_bchannel(bch);
hc->chan[bch->slot].coeff_count = 0;
test_and_clear_bit(FLG_ACTIVE, &bch->Flags);
test_and_clear_bit(FLG_TX_BUSY, &bch->Flags);
hc->chan[bch->slot].rx_off = 0;
hc->chan[bch->slot].conf = -1;
mode_hfcmulti(hc, bch->slot, ISDN_P_NONE, -1, 0, -1, 0);
@ -5384,9 +5370,10 @@ hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
ent->device == PCI_DEVICE_ID_CCD_HFC8S ||
ent->device == PCI_DEVICE_ID_CCD_HFCE1)) {
printk(KERN_ERR
"Unknown HFC multiport controller (vendor:%x device:%x "
"subvendor:%x subdevice:%x)\n", ent->vendor, ent->device,
ent->subvendor, ent->subdevice);
"Unknown HFC multiport controller (vendor:%04x device:%04x "
"subvendor:%04x subdevice:%04x)\n", pdev->vendor,
pdev->device, pdev->subsystem_vendor,
pdev->subsystem_device);
printk(KERN_ERR
"Please contact the driver maintainer for support.\n");
return -ENODEV;

16
drivers/isdn/hardware/mISDN/hfcpci.c
View File

@ -1522,22 +1522,8 @@ deactivate_bchannel(struct bchannel *bch)
u_long flags;
spin_lock_irqsave(&hc->lock, flags);
if (test_and_clear_bit(FLG_TX_NEXT, &bch->Flags)) {
dev_kfree_skb(bch->next_skb);
bch->next_skb = NULL;
}
if (bch->tx_skb) {
dev_kfree_skb(bch->tx_skb);
bch->tx_skb = NULL;
}
bch->tx_idx = 0;
if (bch->rx_skb) {
dev_kfree_skb(bch->rx_skb);
bch->rx_skb = NULL;
}
mISDN_clear_bchannel(bch);
mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
test_and_clear_bit(FLG_ACTIVE, &bch->Flags);
test_and_clear_bit(FLG_TX_BUSY, &bch->Flags);
spin_unlock_irqrestore(&hc->lock, flags);
}

16
drivers/isdn/hardware/mISDN/hfcsusb.c
View File

@ -1809,21 +1809,7 @@ deactivate_bchannel(struct bchannel *bch)
hw->name, __func__, bch->nr);
spin_lock_irqsave(&hw->lock, flags);
if (test_and_clear_bit(FLG_TX_NEXT, &bch->Flags)) {
dev_kfree_skb(bch->next_skb);
bch->next_skb = NULL;
}
if (bch->tx_skb) {
dev_kfree_skb(bch->tx_skb);
bch->tx_skb = NULL;
}
bch->tx_idx = 0;
if (bch->rx_skb) {
dev_kfree_skb(bch->rx_skb);
bch->rx_skb = NULL;
}
clear_bit(FLG_ACTIVE, &bch->Flags);
clear_bit(FLG_TX_BUSY, &bch->Flags);
mISDN_clear_bchannel(bch);
spin_unlock_irqrestore(&hw->lock, flags);
hfcsusb_setup_bch(bch, ISDN_P_NONE);
hfcsusb_stop_endpoint(hw, bch->nr);

109
drivers/isdn/hardware/mISDN/iohelper.h Normal file
View File

@ -0,0 +1,109 @@
/*
* iohelper.h
* helper for define functions to access ISDN hardware
* supported are memory mapped IO
* indirect port IO (one port for address, one for data)
*
* Author Karsten Keil <keil@isdn4linux.de>
*
* Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef _IOHELPER_H
#define _IOHELPER_H
typedef u8 (read_reg_t)(void *, u8);
typedef void (write_reg_t)(void *, u8, u8);
typedef void (fifo_func_t)(void *, u8, u8 *, int);
struct _ioport {
u32 port;
u32 ale;
};
#define IOFUNC_IO(name, hws, ap) \
static u8 Read##name##_IO(void *p, u8 off) {\
struct hws *hw = p;\
return inb(hw->ap.port + off);\
} \
static void Write##name##_IO(void *p, u8 off, u8 val) {\
struct hws *hw = p;\
outb(val, hw->ap.port + off);\
} \
static void ReadFiFo##name##_IO(void *p, u8 off, u8 *dp, int size) {\
struct hws *hw = p;\
insb(hw->ap.port + off, dp, size);\
} \
static void WriteFiFo##name##_IO(void *p, u8 off, u8 *dp, int size) {\
struct hws *hw = p;\
outsb(hw->ap.port + off, dp, size);\
}
#define IOFUNC_IND(name, hws, ap) \
static u8 Read##name##_IND(void *p, u8 off) {\
struct hws *hw = p;\
outb(off, hw->ap.ale);\
return inb(hw->ap.port);\
} \
static void Write##name##_IND(void *p, u8 off, u8 val) {\
struct hws *hw = p;\
outb(off, hw->ap.ale);\
outb(val, hw->ap.port);\
} \
static void ReadFiFo##name##_IND(void *p, u8 off, u8 *dp, int size) {\
struct hws *hw = p;\
outb(off, hw->ap.ale);\
insb(hw->ap.port, dp, size);\
} \
static void WriteFiFo##name##_IND(void *p, u8 off, u8 *dp, int size) {\
struct hws *hw = p;\
outb(off, hw->ap.ale);\
outsb(hw->ap.port, dp, size);\
}
#define IOFUNC_MEMIO(name, hws, typ, adr) \
static u8 Read##name##_MIO(void *p, u8 off) {\
struct hws *hw = p;\
return readb(((typ *)hw->adr) + off);\
} \
static void Write##name##_MIO(void *p, u8 off, u8 val) {\
struct hws *hw = p;\
writeb(val, ((typ *)hw->adr) + off);\
} \
static void ReadFiFo##name##_MIO(void *p, u8 off, u8 *dp, int size) {\
struct hws *hw = p;\
while (size--)\
*dp++ = readb(((typ *)hw->adr) + off);\
} \
static void WriteFiFo##name##_MIO(void *p, u8 off, u8 *dp, int size) {\
struct inf_hw *hw = p;\
while (size--)\
writeb(*dp++, ((typ *)hw->adr) + off);\
}
#define ASSIGN_FUNC(typ, name, dest) do {\
dest.read_reg = &Read##name##_##typ;\
dest.write_reg = &Write##name##_##typ;\
dest.read_fifo = &ReadFiFo##name##_##typ;\
dest.write_fifo = &WriteFiFo##name##_##typ;\
} while (0)
#define ASSIGN_FUNC_IPAC(typ, target) do {\
ASSIGN_FUNC(typ, ISAC, target.isac);\
ASSIGN_FUNC(typ, IPAC, target);\
} while (0)
#endif

405
drivers/isdn/hardware/mISDN/ipac.h Normal file
View File

@ -0,0 +1,405 @@
/*
*
* ipac.h Defines for the Infineon (former Siemens) ISDN
* chip series
*
* Author Karsten Keil <keil@isdn4linux.de>
*
* Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#include "iohelper.h"
struct isac_hw {
struct dchannel dch;
u32 type;
u32 off; /* offset to isac regs */
char *name;
spinlock_t *hwlock; /* lock HW acccess */
read_reg_t *read_reg;
write_reg_t *write_reg;
fifo_func_t *read_fifo;
fifo_func_t *write_fifo;
int (*monitor)(void *, u32, u8 *, int);
void (*release)(struct isac_hw *);
int (*init)(struct isac_hw *);
int (*ctrl)(struct isac_hw *, u32, u_long);
int (*open)(struct isac_hw *, struct channel_req *);
u8 *mon_tx;
u8 *mon_rx;
int mon_txp;
int mon_txc;
int mon_rxp;
struct arcofi_msg *arcofi_list;
struct timer_list arcofitimer;
wait_queue_head_t arcofi_wait;
u8 arcofi_bc;
u8 arcofi_state;
u8 mocr;
u8 adf2;
u8 state;
};
struct ipac_hw;
struct hscx_hw {
struct bchannel bch;
struct ipac_hw *ip;
u8 fifo_size;
u8 off; /* offset to ICA or ICB */
u8 slot;
char log[64];
};
struct ipac_hw {
struct isac_hw isac;
struct hscx_hw hscx[2];
char *name;
void *hw;
spinlock_t *hwlock; /* lock HW acccess */
struct module *owner;
u32 type;
read_reg_t *read_reg;
write_reg_t *write_reg;
fifo_func_t *read_fifo;
fifo_func_t *write_fifo;
void (*release)(struct ipac_hw *);
int (*init)(struct ipac_hw *);
int (*ctrl)(struct ipac_hw *, u32, u_long);
u8 conf;
};
#define IPAC_TYPE_ISAC 0x0010
#define IPAC_TYPE_IPAC 0x0020
#define IPAC_TYPE_ISACX 0x0040
#define IPAC_TYPE_IPACX 0x0080
#define IPAC_TYPE_HSCX 0x0100
#define ISAC_USE_ARCOFI 0x1000
/* Monitor functions */
#define MONITOR_RX_0 0x1000
#define MONITOR_RX_1 0x1001
#define MONITOR_TX_0 0x2000
#define MONITOR_TX_1 0x2001
/* All registers original Siemens Spec */
/* IPAC/ISAC registers */
#define ISAC_MASK 0x20
#define ISAC_ISTA 0x20
#define ISAC_STAR 0x21
#define ISAC_CMDR 0x21
#define ISAC_EXIR 0x24
#define ISAC_ADF2 0x39
#define ISAC_SPCR 0x30
#define ISAC_ADF1 0x38
#define ISAC_CIR0 0x31
#define ISAC_CIX0 0x31
#define ISAC_CIR1 0x33
#define ISAC_CIX1 0x33
#define ISAC_STCR 0x37
#define ISAC_MODE 0x22
#define ISAC_RSTA 0x27
#define ISAC_RBCL 0x25
#define ISAC_RBCH 0x2A
#define ISAC_TIMR 0x23
#define ISAC_SQXR 0x3b
#define ISAC_SQRR 0x3b
#define ISAC_MOSR 0x3a
#define ISAC_MOCR 0x3a
#define ISAC_MOR0 0x32
#define ISAC_MOX0 0x32
#define ISAC_MOR1 0x34
#define ISAC_MOX1 0x34
#define ISAC_RBCH_XAC 0x80
#define IPAC_D_TIN2 0x01
/* IPAC/HSCX */
#define IPAC_ISTAB 0x20 /* RD */
#define IPAC_MASKB 0x20 /* WR */
#define IPAC_STARB 0x21 /* RD */
#define IPAC_CMDRB 0x21 /* WR */
#define IPAC_MODEB 0x22 /* R/W */
#define IPAC_EXIRB 0x24 /* RD */
#define IPAC_RBCLB 0x25 /* RD */
#define IPAC_RAH1 0x26 /* WR */
#define IPAC_RAH2 0x27 /* WR */
#define IPAC_RSTAB 0x27 /* RD */
#define IPAC_RAL1 0x28 /* R/W */
#define IPAC_RAL2 0x29 /* WR */
#define IPAC_RHCRB 0x29 /* RD */
#define IPAC_XBCL 0x2A /* WR */
#define IPAC_CCR2 0x2C /* R/W */
#define IPAC_RBCHB 0x2D /* RD */
#define IPAC_XBCH 0x2D /* WR */
#define HSCX_VSTR 0x2E /* RD */
#define IPAC_RLCR 0x2E /* WR */
#define IPAC_CCR1 0x2F /* R/W */
#define IPAC_TSAX 0x30 /* WR */
#define IPAC_TSAR 0x31 /* WR */
#define IPAC_XCCR 0x32 /* WR */
#define IPAC_RCCR 0x33 /* WR */
/* IPAC_ISTAB/IPAC_MASKB bits */
#define IPAC_B_XPR 0x10
#define IPAC_B_RPF 0x40
#define IPAC_B_RME 0x80
#define IPAC_B_ON 0x2F
/* IPAC_EXIRB bits */
#define IPAC_B_RFS 0x04
#define IPAC_B_RFO 0x10
#define IPAC_B_XDU 0x40
#define IPAC_B_XMR 0x80
/* IPAC special registers */
#define IPAC_CONF 0xC0 /* R/W */
#define IPAC_ISTA 0xC1 /* RD */
#define IPAC_MASK 0xC1 /* WR */
#define IPAC_ID 0xC2 /* RD */
#define IPAC_ACFG 0xC3 /* R/W */
#define IPAC_AOE 0xC4 /* R/W */
#define IPAC_ARX 0xC5 /* RD */
#define IPAC_ATX 0xC5 /* WR */
#define IPAC_PITA1 0xC6 /* R/W */
#define IPAC_PITA2 0xC7 /* R/W */
#define IPAC_POTA1 0xC8 /* R/W */
#define IPAC_POTA2 0xC9 /* R/W */
#define IPAC_PCFG 0xCA /* R/W */
#define IPAC_SCFG 0xCB /* R/W */
#define IPAC_TIMR2 0xCC /* R/W */
/* IPAC_ISTA/_MASK bits */
#define IPAC__EXB 0x01
#define IPAC__ICB 0x02
#define IPAC__EXA 0x04
#define IPAC__ICA 0x08
#define IPAC__EXD 0x10
#define IPAC__ICD 0x20
#define IPAC__INT0 0x40
#define IPAC__INT1 0x80
#define IPAC__ON 0xC0
/* HSCX ISTA/MASK bits */
#define HSCX__EXB 0x01
#define HSCX__EXA 0x02
#define HSCX__ICA 0x04
/* ISAC/ISACX/IPAC/IPACX L1 commands */
#define ISAC_CMD_TIM 0x0
#define ISAC_CMD_RS 0x1
#define ISAC_CMD_SCZ 0x4
#define ISAC_CMD_SSZ 0x2
#define ISAC_CMD_AR8 0x8
#define ISAC_CMD_AR10 0x9
#define ISAC_CMD_ARL 0xA
#define ISAC_CMD_DUI 0xF
/* ISAC/ISACX/IPAC/IPACX L1 indications */
#define ISAC_IND_RS 0x1
#define ISAC_IND_PU 0x7
#define ISAC_IND_DR 0x0
#define ISAC_IND_SD 0x2
#define ISAC_IND_DIS 0x3
#define ISAC_IND_EI 0x6
#define ISAC_IND_RSY 0x4
#define ISAC_IND_ARD 0x8
#define ISAC_IND_TI 0xA
#define ISAC_IND_ATI 0xB
#define ISAC_IND_AI8 0xC
#define ISAC_IND_AI10 0xD
#define ISAC_IND_DID 0xF
/* the new ISACX / IPACX */
/* D-channel registers */
#define ISACX_RFIFOD 0x00 /* RD */
#define ISACX_XFIFOD 0x00 /* WR */
#define ISACX_ISTAD 0x20 /* RD */
#define ISACX_MASKD 0x20 /* WR */
#define ISACX_STARD 0x21 /* RD */
#define ISACX_CMDRD 0x21 /* WR */
#define ISACX_MODED 0x22 /* R/W */
#define ISACX_EXMD1 0x23 /* R/W */
#define ISACX_TIMR1 0x24 /* R/W */
#define ISACX_SAP1 0x25 /* WR */
#define ISACX_SAP2 0x26 /* WR */
#define ISACX_RBCLD 0x26 /* RD */
#define ISACX_RBCHD 0x27 /* RD */
#define ISACX_TEI1 0x27 /* WR */
#define ISACX_TEI2 0x28 /* WR */
#define ISACX_RSTAD 0x28 /* RD */
#define ISACX_TMD 0x29 /* R/W */
#define ISACX_CIR0 0x2E /* RD */
#define ISACX_CIX0 0x2E /* WR */
#define ISACX_CIR1 0x2F /* RD */
#define ISACX_CIX1 0x2F /* WR */
/* Transceiver registers */
#define ISACX_TR_CONF0 0x30 /* R/W */
#define ISACX_TR_CONF1 0x31 /* R/W */
#define ISACX_TR_CONF2 0x32 /* R/W */
#define ISACX_TR_STA 0x33 /* RD */
#define ISACX_TR_CMD 0x34 /* R/W */
#define ISACX_SQRR1 0x35 /* RD */
#define ISACX_SQXR1 0x35 /* WR */
#define ISACX_SQRR2 0x36 /* RD */
#define ISACX_SQXR2 0x36 /* WR */
#define ISACX_SQRR3 0x37 /* RD */
#define ISACX_SQXR3 0x37 /* WR */
#define ISACX_ISTATR 0x38 /* RD */
#define ISACX_MASKTR 0x39 /* R/W */
#define ISACX_TR_MODE 0x3A /* R/W */
#define ISACX_ACFG1 0x3C /* R/W */
#define ISACX_ACFG2 0x3D /* R/W */
#define ISACX_AOE 0x3E /* R/W */
#define ISACX_ARX 0x3F /* RD */
#define ISACX_ATX 0x3F /* WR */
/* IOM: Timeslot, DPS, CDA */
#define ISACX_CDA10 0x40 /* R/W */
#define ISACX_CDA11 0x41 /* R/W */
#define ISACX_CDA20 0x42 /* R/W */
#define ISACX_CDA21 0x43 /* R/W */
#define ISACX_CDA_TSDP10 0x44 /* R/W */
#define ISACX_CDA_TSDP11 0x45 /* R/W */
#define ISACX_CDA_TSDP20 0x46 /* R/W */
#define ISACX_CDA_TSDP21 0x47 /* R/W */
#define ISACX_BCHA_TSDP_BC1 0x48 /* R/W */
#define ISACX_BCHA_TSDP_BC2 0x49 /* R/W */
#define ISACX_BCHB_TSDP_BC1 0x4A /* R/W */
#define ISACX_BCHB_TSDP_BC2 0x4B /* R/W */
#define ISACX_TR_TSDP_BC1 0x4C /* R/W */
#define ISACX_TR_TSDP_BC2 0x4D /* R/W */
#define ISACX_CDA1_CR 0x4E /* R/W */
#define ISACX_CDA2_CR 0x4F /* R/W */
/* IOM: Contol, Sync transfer, Monitor */
#define ISACX_TR_CR 0x50 /* R/W */
#define ISACX_TRC_CR 0x50 /* R/W */
#define ISACX_BCHA_CR 0x51 /* R/W */
#define ISACX_BCHB_CR 0x52 /* R/W */
#define ISACX_DCI_CR 0x53 /* R/W */
#define ISACX_DCIC_CR 0x53 /* R/W */
#define ISACX_MON_CR 0x54 /* R/W */
#define ISACX_SDS1_CR 0x55 /* R/W */
#define ISACX_SDS2_CR 0x56 /* R/W */
#define ISACX_IOM_CR 0x57 /* R/W */
#define ISACX_STI 0x58 /* RD */
#define ISACX_ASTI 0x58 /* WR */
#define ISACX_MSTI 0x59 /* R/W */
#define ISACX_SDS_CONF 0x5A /* R/W */
#define ISACX_MCDA 0x5B /* RD */
#define ISACX_MOR 0x5C /* RD */
#define ISACX_MOX 0x5C /* WR */
#define ISACX_MOSR 0x5D /* RD */
#define ISACX_MOCR 0x5E /* R/W */
#define ISACX_MSTA 0x5F /* RD */
#define ISACX_MCONF 0x5F /* WR */
/* Interrupt and general registers */
#define ISACX_ISTA 0x60 /* RD */
#define ISACX_MASK 0x60 /* WR */
#define ISACX_AUXI 0x61 /* RD */
#define ISACX_AUXM 0x61 /* WR */
#define ISACX_MODE1 0x62 /* R/W */
#define ISACX_MODE2 0x63 /* R/W */
#define ISACX_ID 0x64 /* RD */
#define ISACX_SRES 0x64 /* WR */
#define ISACX_TIMR2 0x65 /* R/W */
/* Register Bits */
/* ISACX/IPACX _ISTAD (R) and _MASKD (W) */
#define ISACX_D_XDU 0x04
#define ISACX_D_XMR 0x08
#define ISACX_D_XPR 0x10
#define ISACX_D_RFO 0x20
#define ISACX_D_RPF 0x40
#define ISACX_D_RME 0x80
/* ISACX/IPACX _ISTA (R) and _MASK (W) */
#define ISACX__ICD 0x01
#define ISACX__MOS 0x02
#define ISACX__TRAN 0x04
#define ISACX__AUX 0x08
#define ISACX__CIC 0x10
#define ISACX__ST 0x20
#define IPACX__ICB 0x40
#define IPACX__ICA 0x80
#define IPACX__ON 0x2C
/* ISACX/IPACX _CMDRD (W) */
#define ISACX_CMDRD_XRES 0x01
#define ISACX_CMDRD_XME 0x02
#define ISACX_CMDRD_XTF 0x08
#define ISACX_CMDRD_STI 0x10
#define ISACX_CMDRD_RRES 0x40
#define ISACX_CMDRD_RMC 0x80
/* ISACX/IPACX _RSTAD (R) */
#define ISACX_RSTAD_TA 0x01
#define ISACX_RSTAD_CR 0x02
#define ISACX_RSTAD_SA0 0x04
#define ISACX_RSTAD_SA1 0x08
#define ISACX_RSTAD_RAB 0x10
#define ISACX_RSTAD_CRC 0x20
#define ISACX_RSTAD_RDO 0x40
#define ISACX_RSTAD_VFR 0x80
/* ISACX/IPACX _CIR0 (R) */
#define ISACX_CIR0_BAS 0x01
#define ISACX_CIR0_SG 0x08
#define ISACX_CIR0_CIC1 0x08
#define ISACX_CIR0_CIC0 0x08
/* B-channel registers */
#define IPACX_OFF_ICA 0x70
#define IPACX_OFF_ICB 0x80
/* ICA: IPACX_OFF_ICA + Reg ICB: IPACX_OFF_ICB + Reg */
#define IPACX_ISTAB 0x00 /* RD */
#define IPACX_MASKB 0x00 /* WR */
#define IPACX_STARB 0x01 /* RD */
#define IPACX_CMDRB 0x01 /* WR */
#define IPACX_MODEB 0x02 /* R/W */
#define IPACX_EXMB 0x03 /* R/W */
#define IPACX_RAH1 0x05 /* WR */
#define IPACX_RAH2 0x06 /* WR */
#define IPACX_RBCLB 0x06 /* RD */
#define IPACX_RBCHB 0x07 /* RD */
#define IPACX_RAL1 0x07 /* WR */
#define IPACX_RAL2 0x08 /* WR */
#define IPACX_RSTAB 0x08 /* RD */
#define IPACX_TMB 0x09 /* R/W */
#define IPACX_RFIFOB 0x0A /* RD */
#define IPACX_XFIFOB 0x0A /* WR */
/* IPACX_ISTAB / IPACX_MASKB bits */
#define IPACX_B_XDU 0x04
#define IPACX_B_XPR 0x10
#define IPACX_B_RFO 0x20
#define IPACX_B_RPF 0x40
#define IPACX_B_RME 0x80
#define IPACX_B_ON 0x0B
extern int mISDNisac_init(struct isac_hw *, void *);
extern irqreturn_t mISDNisac_irq(struct isac_hw *, u8);
extern u32 mISDNipac_init(struct ipac_hw *, void *);
extern irqreturn_t mISDNipac_irq(struct ipac_hw *, int);

269
drivers/isdn/hardware/mISDN/isar.h Normal file
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/*
*
* isar.h ISAR (Siemens PSB 7110) specific defines
*
* Author Karsten Keil (keil@isdn4linux.de)
*
* Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#include "iohelper.h"
struct isar_hw;
struct isar_ch {
struct bchannel bch;
struct isar_hw *is;
struct timer_list ftimer;
u8 nr;
u8 dpath;
u8 mml;
u8 state;
u8 cmd;
u8 mod;
u8 newcmd;
u8 newmod;
u8 try_mod;
u8 conmsg[16];
};
struct isar_hw {
struct isar_ch ch[2];
void *hw;
spinlock_t *hwlock; /* lock HW acccess */
char *name;
struct module *owner;
read_reg_t *read_reg;
write_reg_t *write_reg;
fifo_func_t *read_fifo;
fifo_func_t *write_fifo;
int (*ctrl)(void *, u32, u_long);
void (*release)(struct isar_hw *);
int (*init)(struct isar_hw *);
int (*open)(struct isar_hw *, struct channel_req *);
int (*firmware)(struct isar_hw *, const u8 *, int);
unsigned long Flags;
int version;
u8 bstat;
u8 iis;
u8 cmsb;
u8 clsb;
u8 buf[256];
u8 log[256];
};
#define ISAR_IRQMSK 0x04
#define ISAR_IRQSTA 0x04
#define ISAR_IRQBIT 0x75
#define ISAR_CTRL_H 0x61
#define ISAR_CTRL_L 0x60
#define ISAR_IIS 0x58
#define ISAR_IIA 0x58
#define ISAR_HIS 0x50
#define ISAR_HIA 0x50
#define ISAR_MBOX 0x4c
#define ISAR_WADR 0x4a
#define ISAR_RADR 0x48
#define ISAR_HIS_VNR 0x14
#define ISAR_HIS_DKEY 0x02
#define ISAR_HIS_FIRM 0x1e
#define ISAR_HIS_STDSP 0x08
#define ISAR_HIS_DIAG 0x05
#define ISAR_HIS_P0CFG 0x3c
#define ISAR_HIS_P12CFG 0x24
#define ISAR_HIS_SARTCFG 0x25
#define ISAR_HIS_PUMPCFG 0x26
#define ISAR_HIS_PUMPCTRL 0x2a
#define ISAR_HIS_IOM2CFG 0x27
#define ISAR_HIS_IOM2REQ 0x07
#define ISAR_HIS_IOM2CTRL 0x2b
#define ISAR_HIS_BSTREQ 0x0c
#define ISAR_HIS_PSTREQ 0x0e
#define ISAR_HIS_SDATA 0x20
#define ISAR_HIS_DPS1 0x40
#define ISAR_HIS_DPS2 0x80
#define SET_DPS(x) ((x<<6) & 0xc0)
#define ISAR_IIS_MSCMSD 0x3f
#define ISAR_IIS_VNR 0x15
#define ISAR_IIS_DKEY 0x03
#define ISAR_IIS_FIRM 0x1f
#define ISAR_IIS_STDSP 0x09
#define ISAR_IIS_DIAG 0x25
#define ISAR_IIS_GSTEV 0x00
#define ISAR_IIS_BSTEV 0x28
#define ISAR_IIS_BSTRSP 0x2c
#define ISAR_IIS_PSTRSP 0x2e
#define ISAR_IIS_PSTEV 0x2a
#define ISAR_IIS_IOM2RSP 0x27
#define ISAR_IIS_RDATA 0x20
#define ISAR_IIS_INVMSG 0x3f
#define ISAR_CTRL_SWVER 0x10
#define ISAR_CTRL_STST 0x40
#define ISAR_MSG_HWVER 0x20
#define ISAR_DP1_USE 1
#define ISAR_DP2_USE 2
#define ISAR_RATE_REQ 3
#define PMOD_DISABLE 0
#define PMOD_FAX 1
#define PMOD_DATAMODEM 2
#define PMOD_HALFDUPLEX 3
#define PMOD_V110 4
#define PMOD_DTMF 5
#define PMOD_DTMF_TRANS 6
#define PMOD_BYPASS 7
#define PCTRL_ORIG 0x80
#define PV32P2_V23R 0x40
#define PV32P2_V22A 0x20
#define PV32P2_V22B 0x10
#define PV32P2_V22C 0x08
#define PV32P2_V21 0x02
#define PV32P2_BEL 0x01
/* LSB MSB in ISAR doc wrong !!! Arghhh */
#define PV32P3_AMOD 0x80
#define PV32P3_V32B 0x02
#define PV32P3_V23B 0x01
#define PV32P4_48 0x11
#define PV32P5_48 0x05
#define PV32P4_UT48 0x11
#define PV32P5_UT48 0x0d
#define PV32P4_96 0x11
#define PV32P5_96 0x03
#define PV32P4_UT96 0x11
#define PV32P5_UT96 0x0f
#define PV32P4_B96 0x91
#define PV32P5_B96 0x0b
#define PV32P4_UTB96 0xd1
#define PV32P5_UTB96 0x0f
#define PV32P4_120 0xb1
#define PV32P5_120 0x09
#define PV32P4_UT120 0xf1
#define PV32P5_UT120 0x0f
#define PV32P4_144 0x99
#define PV32P5_144 0x09
#define PV32P4_UT144 0xf9
#define PV32P5_UT144 0x0f
#define PV32P6_CTN 0x01
#define PV32P6_ATN 0x02
#define PFAXP2_CTN 0x01
#define PFAXP2_ATN 0x04
#define PSEV_10MS_TIMER 0x02
#define PSEV_CON_ON 0x18
#define PSEV_CON_OFF 0x19
#define PSEV_V24_OFF 0x20
#define PSEV_CTS_ON 0x21
#define PSEV_CTS_OFF 0x22
#define PSEV_DCD_ON 0x23
#define PSEV_DCD_OFF 0x24
#define PSEV_DSR_ON 0x25
#define PSEV_DSR_OFF 0x26
#define PSEV_REM_RET 0xcc
#define PSEV_REM_REN 0xcd
#define PSEV_GSTN_CLR 0xd4
#define PSEV_RSP_READY 0xbc
#define PSEV_LINE_TX_H 0xb3
#define PSEV_LINE_TX_B 0xb2
#define PSEV_LINE_RX_H 0xb1
#define PSEV_LINE_RX_B 0xb0
#define PSEV_RSP_CONN 0xb5
#define PSEV_RSP_DISC 0xb7
#define PSEV_RSP_FCERR 0xb9
#define PSEV_RSP_SILDET 0xbe
#define PSEV_RSP_SILOFF 0xab
#define PSEV_FLAGS_DET 0xba
#define PCTRL_CMD_TDTMF 0x5a
#define PCTRL_CMD_FTH 0xa7
#define PCTRL_CMD_FRH 0xa5
#define PCTRL_CMD_FTM 0xa8
#define PCTRL_CMD_FRM 0xa6
#define PCTRL_CMD_SILON 0xac
#define PCTRL_CMD_CONT 0xa2
#define PCTRL_CMD_ESC 0xa4
#define PCTRL_CMD_SILOFF 0xab
#define PCTRL_CMD_HALT 0xa9
#define PCTRL_LOC_RET 0xcf
#define PCTRL_LOC_REN 0xce
#define SMODE_DISABLE 0
#define SMODE_V14 2
#define SMODE_HDLC 3
#define SMODE_BINARY 4
#define SMODE_FSK_V14 5
#define SCTRL_HDMC_BOTH 0x00
#define SCTRL_HDMC_DTX 0x80
#define SCTRL_HDMC_DRX 0x40
#define S_P1_OVSP 0x40
#define S_P1_SNP 0x20
#define S_P1_EOP 0x10
#define S_P1_EDP 0x08
#define S_P1_NSB 0x04
#define S_P1_CHS_8 0x03
#define S_P1_CHS_7 0x02
#define S_P1_CHS_6 0x01
#define S_P1_CHS_5 0x00
#define S_P2_BFT_DEF 0x10
#define IOM_CTRL_ENA 0x80
#define IOM_CTRL_NOPCM 0x00
#define IOM_CTRL_ALAW 0x02
#define IOM_CTRL_ULAW 0x04
#define IOM_CTRL_RCV 0x01
#define IOM_P1_TXD 0x10
#define HDLC_FED 0x40
#define HDLC_FSD 0x20
#define HDLC_FST 0x20
#define HDLC_ERROR 0x1c
#define HDLC_ERR_FAD 0x10
#define HDLC_ERR_RER 0x08
#define HDLC_ERR_CER 0x04
#define SART_NMD 0x01
#define BSTAT_RDM0 0x1
#define BSTAT_RDM1 0x2
#define BSTAT_RDM2 0x4
#define BSTAT_RDM3 0x8
#define BSTEV_TBO 0x1f
#define BSTEV_RBO 0x2f
/* FAX State Machine */
#define STFAX_NULL 0
#define STFAX_READY 1
#define STFAX_LINE 2
#define STFAX_CONT 3
#define STFAX_ACTIV 4
#define STFAX_ESCAPE 5
#define STFAX_SILDET 6
extern u32 mISDNisar_init(struct isar_hw *, void *);
extern void mISDNisar_irq(struct isar_hw *);

1178
drivers/isdn/hardware/mISDN/mISDNinfineon.c Normal file
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1655
drivers/isdn/hardware/mISDN/mISDNipac.c Normal file
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1726
drivers/isdn/hardware/mISDN/mISDNisar.c Normal file
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1156
drivers/isdn/hardware/mISDN/netjet.c Normal file
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58
drivers/isdn/hardware/mISDN/netjet.h Normal file
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/*
* NETjet common header file
*
* Author Karsten Keil
* based on work of Matt Henderson and Daniel Potts,
* Traverse Technologies P/L www.traverse.com.au
*
* Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#define NJ_CTRL 0x00
#define NJ_DMACTRL 0x01
#define NJ_AUXCTRL 0x02
#define NJ_AUXDATA 0x03
#define NJ_IRQMASK0 0x04
#define NJ_IRQMASK1 0x05
#define NJ_IRQSTAT0 0x06
#define NJ_IRQSTAT1 0x07
#define NJ_DMA_READ_START 0x08
#define NJ_DMA_READ_IRQ 0x0c
#define NJ_DMA_READ_END 0x10
#define NJ_DMA_READ_ADR 0x14
#define NJ_DMA_WRITE_START 0x18
#define NJ_DMA_WRITE_IRQ 0x1c
#define NJ_DMA_WRITE_END 0x20
#define NJ_DMA_WRITE_ADR 0x24
#define NJ_PULSE_CNT 0x28
#define NJ_ISAC_OFF 0xc0
#define NJ_ISACIRQ 0x10
#define NJ_IRQM0_RD_MASK 0x03
#define NJ_IRQM0_RD_IRQ 0x01
#define NJ_IRQM0_RD_END 0x02
#define NJ_IRQM0_WR_MASK 0x0c
#define NJ_IRQM0_WR_IRQ 0x04
#define NJ_IRQM0_WR_END 0x08
/* one page here is no need to be smaller */
#define NJ_DMA_SIZE 4096
/* 2 * 64 byte is a compromise between IRQ count and latency */
#define NJ_DMA_RXSIZE 128 /* 2 * 64 */
#define NJ_DMA_TXSIZE 128 /* 2 * 64 */

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drivers/isdn/hardware/mISDN/speedfax.c Normal file
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/*
* speedfax.c low level stuff for Sedlbauer Speedfax+ cards
* based on the ISAR DSP
* Thanks to Sedlbauer AG for informations and HW
*
* Author Karsten Keil <keil@isdn4linux.de>
*
* Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/mISDNhw.h>
#include <linux/firmware.h>
#include "ipac.h"
#include "isar.h"
#define SPEEDFAX_REV "2.0"
#define PCI_SUBVENDOR_SPEEDFAX_PYRAMID 0x51
#define PCI_SUBVENDOR_SPEEDFAX_PCI 0x54
#define PCI_SUB_ID_SEDLBAUER 0x01
#define SFAX_PCI_ADDR 0xc8
#define SFAX_PCI_ISAC 0xd0
#define SFAX_PCI_ISAR 0xe0
/* TIGER 100 Registers */
#define TIGER_RESET_ADDR 0x00
#define TIGER_EXTERN_RESET_ON 0x01
#define TIGER_EXTERN_RESET_OFF 0x00
#define TIGER_AUX_CTRL 0x02
#define TIGER_AUX_DATA 0x03
#define TIGER_AUX_IRQMASK 0x05
#define TIGER_AUX_STATUS 0x07
/* Tiger AUX BITs */
#define SFAX_AUX_IOMASK 0xdd /* 1 and 5 are inputs */
#define SFAX_ISAR_RESET_BIT_OFF 0x00
#define SFAX_ISAR_RESET_BIT_ON 0x01
#define SFAX_TIGER_IRQ_BIT 0x02
#define SFAX_LED1_BIT 0x08
#define SFAX_LED2_BIT 0x10
#define SFAX_PCI_RESET_ON (SFAX_ISAR_RESET_BIT_ON)
#define SFAX_PCI_RESET_OFF (SFAX_LED1_BIT | SFAX_LED2_BIT)
static int sfax_cnt;
static u32 debug;
static u32 irqloops = 4;
struct sfax_hw {
struct list_head list;
struct pci_dev *pdev;
char name[MISDN_MAX_IDLEN];
u32 irq;
u32 irqcnt;
u32 cfg;
struct _ioport p_isac;
struct _ioport p_isar;
u8 aux_data;
spinlock_t lock; /* HW access lock */
struct isac_hw isac;
struct isar_hw isar;
};
static LIST_HEAD(Cards);
static DEFINE_RWLOCK(card_lock); /* protect Cards */
static void
_set_debug(struct sfax_hw *card)
{
card->isac.dch.debug = debug;
card->isar.ch[0].bch.debug = debug;
card->isar.ch[1].bch.debug = debug;
}
static int
set_debug(const char *val, struct kernel_param *kp)
{
int ret;
struct sfax_hw *card;
ret = param_set_uint(val, kp);
if (!ret) {
read_lock(&card_lock);
list_for_each_entry(card, &Cards, list)
_set_debug(card);
read_unlock(&card_lock);
}
return ret;
}
MODULE_AUTHOR("Karsten Keil");
MODULE_LICENSE("GPL v2");
MODULE_VERSION(SPEEDFAX_REV);
module_param_call(debug, set_debug, param_get_uint, &debug, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(debug, "Speedfax debug mask");
module_param(irqloops, uint, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(irqloops, "Speedfax maximal irqloops (default 4)");
IOFUNC_IND(ISAC, sfax_hw, p_isac)
IOFUNC_IND(ISAR, sfax_hw, p_isar)
static irqreturn_t
speedfax_irq(int intno, void *dev_id)
{
struct sfax_hw *sf = dev_id;
u8 val;
int cnt = irqloops;
spin_lock(&sf->lock);
val = inb(sf->cfg + TIGER_AUX_STATUS);
if (val & SFAX_TIGER_IRQ_BIT) { /* for us or shared ? */
spin_unlock(&sf->lock);
return IRQ_NONE; /* shared */
}
sf->irqcnt++;
val = ReadISAR_IND(sf, ISAR_IRQBIT);
Start_ISAR:
if (val & ISAR_IRQSTA)
mISDNisar_irq(&sf->isar);
val = ReadISAC_IND(sf, ISAC_ISTA);
if (val)
mISDNisac_irq(&sf->isac, val);
val = ReadISAR_IND(sf, ISAR_IRQBIT);
if ((val & ISAR_IRQSTA) && cnt--)
goto Start_ISAR;
if (cnt < irqloops)
pr_debug("%s: %d irqloops cpu%d\n", sf->name,
irqloops - cnt, smp_processor_id());
if (irqloops && !cnt)
pr_notice("%s: %d IRQ LOOP cpu%d\n", sf->name,
irqloops, smp_processor_id());
spin_unlock(&sf->lock);
return IRQ_HANDLED;
}
static void
enable_hwirq(struct sfax_hw *sf)
{
WriteISAC_IND(sf, ISAC_MASK, 0);
WriteISAR_IND(sf, ISAR_IRQBIT, ISAR_IRQMSK);
outb(SFAX_TIGER_IRQ_BIT, sf->cfg + TIGER_AUX_IRQMASK);
}
static void
disable_hwirq(struct sfax_hw *sf)
{
WriteISAC_IND(sf, ISAC_MASK, 0xFF);
WriteISAR_IND(sf, ISAR_IRQBIT, 0);
outb(0, sf->cfg + TIGER_AUX_IRQMASK);
}
static void
reset_speedfax(struct sfax_hw *sf)
{
pr_debug("%s: resetting card\n", sf->name);
outb(TIGER_EXTERN_RESET_ON, sf->cfg + TIGER_RESET_ADDR);
outb(SFAX_PCI_RESET_ON, sf->cfg + TIGER_AUX_DATA);
mdelay(1);
outb(TIGER_EXTERN_RESET_OFF, sf->cfg + TIGER_RESET_ADDR);
sf->aux_data = SFAX_PCI_RESET_OFF;
outb(sf->aux_data, sf->cfg + TIGER_AUX_DATA);
mdelay(1);
}
static int
sfax_ctrl(struct sfax_hw *sf, u32 cmd, u_long arg)
{
int ret = 0;
switch (cmd) {
case HW_RESET_REQ:
reset_speedfax(sf);
break;
case HW_ACTIVATE_IND:
if (arg & 1)
sf->aux_data &= ~SFAX_LED1_BIT;
if (arg & 2)
sf->aux_data &= ~SFAX_LED2_BIT;
outb(sf->aux_data, sf->cfg + TIGER_AUX_DATA);
break;
case HW_DEACT_IND:
if (arg & 1)
sf->aux_data |= SFAX_LED1_BIT;
if (arg & 2)
sf->aux_data |= SFAX_LED2_BIT;
outb(sf->aux_data, sf->cfg + TIGER_AUX_DATA);
break;
default:
pr_info("%s: %s unknown command %x %lx\n",
sf->name, __func__, cmd, arg);
ret = -EINVAL;
break;
}
return ret;
}
static int
channel_ctrl(struct sfax_hw *sf, struct mISDN_ctrl_req *cq)
{
int ret = 0;
switch (cq->op) {
case MISDN_CTRL_GETOP:
cq->op = MISDN_CTRL_LOOP;
break;
case MISDN_CTRL_LOOP:
/* cq->channel: 0 disable, 1 B1 loop 2 B2 loop, 3 both */
if (cq->channel < 0 || cq->channel > 3) {
ret = -EINVAL;
break;
}
ret = sf->isac.ctrl(&sf->isac, HW_TESTLOOP, cq->channel);
break;
default:
pr_info("%s: unknown Op %x\n", sf->name, cq->op);
ret = -EINVAL;
break;
}
return ret;
}
static int
sfax_dctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
{
struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
struct dchannel *dch = container_of(dev, struct dchannel, dev);
struct sfax_hw *sf = dch->hw;
struct channel_req *rq;
int err = 0;
pr_debug("%s: cmd:%x %p\n", sf->name, cmd, arg);
switch (cmd) {
case OPEN_CHANNEL:
rq = arg;
if (rq->protocol == ISDN_P_TE_S0)
err = sf->isac.open(&sf->isac, rq);
else
err = sf->isar.open(&sf->isar, rq);
if (err)
break;
if (!try_module_get(THIS_MODULE))
pr_info("%s: cannot get module\n", sf->name);
break;
case CLOSE_CHANNEL:
pr_debug("%s: dev(%d) close from %p\n", sf->name,
dch->dev.id, __builtin_return_address(0));
module_put(THIS_MODULE);
break;
case CONTROL_CHANNEL:
err = channel_ctrl(sf, arg);
break;
default:
pr_debug("%s: unknown command %x\n", sf->name, cmd);
return -EINVAL;
}
return err;
}
static int __devinit
init_card(struct sfax_hw *sf)
{
int ret, cnt = 3;
u_long flags;
ret = request_irq(sf->irq, speedfax_irq, IRQF_SHARED, sf->name, sf);
if (ret) {
pr_info("%s: couldn't get interrupt %d\n", sf->name, sf->irq);
return ret;
}
while (cnt--) {
spin_lock_irqsave(&sf->lock, flags);
ret = sf->isac.init(&sf->isac);
if (ret) {
spin_unlock_irqrestore(&sf->lock, flags);
pr_info("%s: ISAC init failed with %d\n",
sf->name, ret);
break;
}
enable_hwirq(sf);
/* RESET Receiver and Transmitter */
WriteISAC_IND(sf, ISAC_CMDR, 0x41);
spin_unlock_irqrestore(&sf->lock, flags);
msleep_interruptible(10);
if (debug & DEBUG_HW)
pr_notice("%s: IRQ %d count %d\n", sf->name,
sf->irq, sf->irqcnt);
if (!sf->irqcnt) {
pr_info("%s: IRQ(%d) got no requests during init %d\n",
sf->name, sf->irq, 3 - cnt);
} else
return 0;
}
free_irq(sf->irq, sf);
return -EIO;
}
static int __devinit
setup_speedfax(struct sfax_hw *sf)
{
u_long flags;
if (!request_region(sf->cfg, 256, sf->name)) {
pr_info("mISDN: %s config port %x-%x already in use\n",
sf->name, sf->cfg, sf->cfg + 255);
return -EIO;
}
outb(0xff, sf->cfg);
outb(0, sf->cfg);
outb(0xdd, sf->cfg + TIGER_AUX_CTRL);
outb(0, sf->cfg + TIGER_AUX_IRQMASK);
sf->isac.type = IPAC_TYPE_ISAC;
sf->p_isac.ale = sf->cfg + SFAX_PCI_ADDR;
sf->p_isac.port = sf->cfg + SFAX_PCI_ISAC;
sf->p_isar.ale = sf->cfg + SFAX_PCI_ADDR;
sf->p_isar.port = sf->cfg + SFAX_PCI_ISAR;
ASSIGN_FUNC(IND, ISAC, sf->isac);
ASSIGN_FUNC(IND, ISAR, sf->isar);
spin_lock_irqsave(&sf->lock, flags);
reset_speedfax(sf);
disable_hwirq(sf);
spin_unlock_irqrestore(&sf->lock, flags);
return 0;
}
static void
release_card(struct sfax_hw *card) {
u_long flags;
spin_lock_irqsave(&card->lock, flags);
disable_hwirq(card);
spin_unlock_irqrestore(&card->lock, flags);
card->isac.release(&card->isac);
free_irq(card->irq, card);
card->isar.release(&card->isar);
mISDN_unregister_device(&card->isac.dch.dev);
release_region(card->cfg, 256);
pci_disable_device(card->pdev);
pci_set_drvdata(card->pdev, NULL);
write_lock_irqsave(&card_lock, flags);
list_del(&card->list);
write_unlock_irqrestore(&card_lock, flags);
kfree(card);
sfax_cnt--;
}
static int __devinit
setup_instance(struct sfax_hw *card)
{
const struct firmware *firmware;
int i, err;
u_long flags;
snprintf(card->name, MISDN_MAX_IDLEN - 1, "Speedfax.%d", sfax_cnt + 1);
write_lock_irqsave(&card_lock, flags);
list_add_tail(&card->list, &Cards);
write_unlock_irqrestore(&card_lock, flags);
_set_debug(card);
spin_lock_init(&card->lock);
card->isac.hwlock = &card->lock;
card->isar.hwlock = &card->lock;
card->isar.ctrl = (void *)&sfax_ctrl;
card->isac.name = card->name;
card->isar.name = card->name;
card->isar.owner = THIS_MODULE;
err = request_firmware(&firmware, "isdn/ISAR.BIN", &card->pdev->dev);
if (err < 0) {
pr_info("%s: firmware request failed %d\n",
card->name, err);
goto error_fw;
}
if (debug & DEBUG_HW)
pr_notice("%s: got firmware %zu bytes\n",
card->name, firmware->size);
mISDNisac_init(&card->isac, card);
card->isac.dch.dev.D.ctrl = sfax_dctrl;
card->isac.dch.dev.Bprotocols =
mISDNisar_init(&card->isar, card);
for (i = 0; i < 2; i++) {
set_channelmap(i + 1, card->isac.dch.dev.channelmap);
list_add(&card->isar.ch[i].bch.ch.list,
&card->isac.dch.dev.bchannels);
}
err = setup_speedfax(card);
if (err)
goto error_setup;
err = card->isar.init(&card->isar);
if (err)
goto error;
err = mISDN_register_device(&card->isac.dch.dev,
&card->pdev->dev, card->name);
if (err)
goto error;
err = init_card(card);
if (err)
goto error_init;
err = card->isar.firmware(&card->isar, firmware->data, firmware->size);
if (!err) {
release_firmware(firmware);
sfax_cnt++;
pr_notice("SpeedFax %d cards installed\n", sfax_cnt);
return 0;
}
disable_hwirq(card);
free_irq(card->irq, card);
error_init:
mISDN_unregister_device(&card->isac.dch.dev);
error:
release_region(card->cfg, 256);
error_setup:
card->isac.release(&card->isac);
card->isar.release(&card->isar);
release_firmware(firmware);
error_fw:
pci_disable_device(card->pdev);
write_lock_irqsave(&card_lock, flags);
list_del(&card->list);
write_unlock_irqrestore(&card_lock, flags);
kfree(card);
return err;
}
static int __devinit
sfaxpci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
int err = -ENOMEM;
struct sfax_hw *card = kzalloc(sizeof(struct sfax_hw), GFP_KERNEL);
if (!card) {
pr_info("No memory for Speedfax+ PCI\n");
return err;
}
card->pdev = pdev;
err = pci_enable_device(pdev);
if (err) {
kfree(card);
return err;
}
pr_notice("mISDN: Speedfax found adapter %s at %s\n",
(char *)ent->driver_data, pci_name(pdev));
card->cfg = pci_resource_start(pdev, 0);
card->irq = pdev->irq;
pci_set_drvdata(pdev, card);
err = setup_instance(card);
if (err)
pci_set_drvdata(pdev, NULL);
return err;
}
static void __devexit
sfax_remove_pci(struct pci_dev *pdev)
{
struct sfax_hw *card = pci_get_drvdata(pdev);
if (card)
release_card(card);
else
pr_debug("%s: drvdata allready removed\n", __func__);
}
static struct pci_device_id sfaxpci_ids[] __devinitdata = {
{ PCI_VENDOR_ID_TIGERJET, PCI_DEVICE_ID_TIGERJET_100,
PCI_SUBVENDOR_SPEEDFAX_PYRAMID, PCI_SUB_ID_SEDLBAUER,
0, 0, (unsigned long) "Pyramid Speedfax + PCI"
},
{ PCI_VENDOR_ID_TIGERJET, PCI_DEVICE_ID_TIGERJET_100,
PCI_SUBVENDOR_SPEEDFAX_PCI, PCI_SUB_ID_SEDLBAUER,
0, 0, (unsigned long) "Sedlbauer Speedfax + PCI"
},
{ }
};
MODULE_DEVICE_TABLE(pci, sfaxpci_ids);
static struct pci_driver sfaxpci_driver = {
.name = "speedfax+ pci",
.probe = sfaxpci_probe,
.remove = __devexit_p(sfax_remove_pci),
.id_table = sfaxpci_ids,
};
static int __init
Speedfax_init(void)
{
int err;
pr_notice("Sedlbauer Speedfax+ Driver Rev. %s\n",
SPEEDFAX_REV);
err = pci_register_driver(&sfaxpci_driver);
return err;
}
static void __exit
Speedfax_cleanup(void)
{
pci_unregister_driver(&sfaxpci_driver);
}
module_init(Speedfax_init);
module_exit(Speedfax_cleanup);

1440
drivers/isdn/hardware/mISDN/w6692.c Normal file
View File

File diff suppressed because it is too large Load Diff

190
drivers/isdn/hardware/mISDN/w6692.h Normal file
View File

@ -0,0 +1,190 @@
/*
* Winbond W6692 specific defines
*
* Author Karsten Keil <keil@isdn4linux.de>
* based on the w6692 I4L driver from Petr Novak <petr.novak@i.cz>
*
* Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
/* Specifications of W6692 registers */
#define W_D_RFIFO 0x00 /* R */
#define W_D_XFIFO 0x04 /* W */
#define W_D_CMDR 0x08 /* W */
#define W_D_MODE 0x0c /* R/W */
#define W_D_TIMR 0x10 /* R/W */
#define W_ISTA 0x14 /* R_clr */
#define W_IMASK 0x18 /* R/W */
#define W_D_EXIR 0x1c /* R_clr */
#define W_D_EXIM 0x20 /* R/W */
#define W_D_STAR 0x24 /* R */
#define W_D_RSTA 0x28 /* R */
#define W_D_SAM 0x2c /* R/W */
#define W_D_SAP1 0x30 /* R/W */
#define W_D_SAP2 0x34 /* R/W */
#define W_D_TAM 0x38 /* R/W */
#define W_D_TEI1 0x3c /* R/W */
#define W_D_TEI2 0x40 /* R/W */
#define W_D_RBCH 0x44 /* R */
#define W_D_RBCL 0x48 /* R */
#define W_TIMR2 0x4c /* W */
#define W_L1_RC 0x50 /* R/W */
#define W_D_CTL 0x54 /* R/W */
#define W_CIR 0x58 /* R */
#define W_CIX 0x5c /* W */
#define W_SQR 0x60 /* R */
#define W_SQX 0x64 /* W */
#define W_PCTL 0x68 /* R/W */
#define W_MOR 0x6c /* R */
#define W_MOX 0x70 /* R/W */
#define W_MOSR 0x74 /* R_clr */
#define W_MOCR 0x78 /* R/W */
#define W_GCR 0x7c /* R/W */
#define W_B_RFIFO 0x80 /* R */
#define W_B_XFIFO 0x84 /* W */
#define W_B_CMDR 0x88 /* W */
#define W_B_MODE 0x8c /* R/W */
#define W_B_EXIR 0x90 /* R_clr */
#define W_B_EXIM 0x94 /* R/W */
#define W_B_STAR 0x98 /* R */
#define W_B_ADM1 0x9c /* R/W */
#define W_B_ADM2 0xa0 /* R/W */
#define W_B_ADR1 0xa4 /* R/W */
#define W_B_ADR2 0xa8 /* R/W */
#define W_B_RBCL 0xac /* R */
#define W_B_RBCH 0xb0 /* R */
#define W_XADDR 0xf4 /* R/W */
#define W_XDATA 0xf8 /* R/W */
#define W_EPCTL 0xfc /* W */
/* W6692 register bits */
#define W_D_CMDR_XRST 0x01
#define W_D_CMDR_XME 0x02
#define W_D_CMDR_XMS 0x08
#define W_D_CMDR_STT 0x10
#define W_D_CMDR_RRST 0x40
#define W_D_CMDR_RACK 0x80
#define W_D_MODE_RLP 0x01
#define W_D_MODE_DLP 0x02
#define W_D_MODE_MFD 0x04
#define W_D_MODE_TEE 0x08
#define W_D_MODE_TMS 0x10
#define W_D_MODE_RACT 0x40
#define W_D_MODE_MMS 0x80
#define W_INT_B2_EXI 0x01
#define W_INT_B1_EXI 0x02
#define W_INT_D_EXI 0x04
#define W_INT_XINT0 0x08
#define W_INT_XINT1 0x10
#define W_INT_D_XFR 0x20
#define W_INT_D_RME 0x40
#define W_INT_D_RMR 0x80
#define W_D_EXI_WEXP 0x01
#define W_D_EXI_TEXP 0x02
#define W_D_EXI_ISC 0x04
#define W_D_EXI_MOC 0x08
#define W_D_EXI_TIN2 0x10
#define W_D_EXI_XCOL 0x20
#define W_D_EXI_XDUN 0x40
#define W_D_EXI_RDOV 0x80
#define W_D_STAR_DRDY 0x10
#define W_D_STAR_XBZ 0x20
#define W_D_STAR_XDOW 0x80
#define W_D_RSTA_RMB 0x10
#define W_D_RSTA_CRCE 0x20
#define W_D_RSTA_RDOV 0x40
#define W_D_CTL_SRST 0x20
#define W_CIR_SCC 0x80
#define W_CIR_ICC 0x40
#define W_CIR_COD_MASK 0x0f
#define W_PCTL_PCX 0x01
#define W_PCTL_XMODE 0x02
#define W_PCTL_OE0 0x04
#define W_PCTL_OE1 0x08
#define W_PCTL_OE2 0x10
#define W_PCTL_OE3 0x20
#define W_PCTL_OE4 0x40
#define W_PCTL_OE5 0x80
#define W_B_CMDR_XRST 0x01
#define W_B_CMDR_XME 0x02
#define W_B_CMDR_XMS 0x04
#define W_B_CMDR_RACT 0x20
#define W_B_CMDR_RRST 0x40
#define W_B_CMDR_RACK 0x80
#define W_B_MODE_FTS0 0x01
#define W_B_MODE_FTS1 0x02
#define W_B_MODE_SW56 0x04
#define W_B_MODE_BSW0 0x08
#define W_B_MODE_BSW1 0x10
#define W_B_MODE_EPCM 0x20
#define W_B_MODE_ITF 0x40
#define W_B_MODE_MMS 0x80
#define W_B_EXI_XDUN 0x01
#define W_B_EXI_XFR 0x02
#define W_B_EXI_RDOV 0x10
#define W_B_EXI_RME 0x20
#define W_B_EXI_RMR 0x40
#define W_B_STAR_XBZ 0x01
#define W_B_STAR_XDOW 0x04
#define W_B_STAR_RMB 0x10
#define W_B_STAR_CRCE 0x20
#define W_B_STAR_RDOV 0x40
#define W_B_RBCH_LOV 0x20
/* W6692 Layer1 commands */
#define W_L1CMD_ECK 0x00
#define W_L1CMD_RST 0x01
#define W_L1CMD_SCP 0x04
#define W_L1CMD_SSP 0x02
#define W_L1CMD_AR8 0x08
#define W_L1CMD_AR10 0x09
#define W_L1CMD_EAL 0x0a
#define W_L1CMD_DRC 0x0f
/* W6692 Layer1 indications */
#define W_L1IND_CE 0x07
#define W_L1IND_DRD 0x00
#define W_L1IND_LD 0x04
#define W_L1IND_ARD 0x08
#define W_L1IND_TI 0x0a
#define W_L1IND_ATI 0x0b
#define W_L1IND_AI8 0x0c
#define W_L1IND_AI10 0x0d
#define W_L1IND_CD 0x0f
/* FIFO thresholds */
#define W_D_FIFO_THRESH 64
#define W_B_FIFO_THRESH 64

6
drivers/isdn/hisax/Kconfig
View File

@ -391,6 +391,7 @@ comment "HiSax sub driver modules"
config HISAX_ST5481
tristate "ST5481 USB ISDN modem (EXPERIMENTAL)"
depends on USB && EXPERIMENTAL
select ISDN_HDLC
select CRC_CCITT
select BITREVERSE
help
@ -418,11 +419,6 @@ config HISAX_FRITZ_PCIPNP
(the latter also needs you to select "ISA Plug and Play support"
from the menu "Plug and Play configuration")
config HISAX_HDLC
bool
depends on HISAX_ST5481
default y
config HISAX_AVM_A1_PCMCIA
bool
depends on HISAX_AVM_A1_CS

4
drivers/isdn/hisax/Makefile
View File

@ -16,10 +16,6 @@ obj-$(CONFIG_HISAX_HFCUSB) += hfc_usb.o
obj-$(CONFIG_HISAX_HFC4S8S) += hfc4s8s_l1.o
obj-$(CONFIG_HISAX_FRITZ_PCIPNP) += hisax_isac.o hisax_fcpcipnp.o
ifdef CONFIG_HISAX_HDLC
obj-$(CONFIG_ISDN_DRV_HISAX) += isdnhdlc.o
endif
# Multipart objects.
hisax_st5481-y := st5481_init.o st5481_usb.o st5481_d.o \

2
drivers/isdn/hisax/amd7930_fn.c
View File

@ -238,8 +238,6 @@ Amd7930_bh(struct work_struct *work)
container_of(work, struct IsdnCardState, tqueue);
struct PStack *stptr;
if (!cs)
return;
if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) {
if (cs->debug)
debugl1(cs, "Amd7930: bh, D-Channel Busy cleared");

4
drivers/isdn/hisax/callc.c
View File

@ -833,8 +833,6 @@ static struct FsmNode fnlist[] __initdata =
};
/* *INDENT-ON* */
#define FNCOUNT (sizeof(fnlist)/sizeof(struct FsmNode))
int __init
CallcNew(void)
{
@ -842,7 +840,7 @@ CallcNew(void)
callcfsm.event_count = EVENT_COUNT;
callcfsm.strEvent = strEvent;
callcfsm.strState = strState;
return FsmNew(&callcfsm, fnlist, FNCOUNT);
return FsmNew(&callcfsm, fnlist, ARRAY_SIZE(fnlist));
}
void

2
drivers/isdn/hisax/hfc_pci.c
View File

@ -1506,8 +1506,6 @@ hfcpci_bh(struct work_struct *work)
u_long flags;
// struct PStack *stptr;
if (!cs)
return;
if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) {
if (!cs->hw.hfcpci.nt_mode)
switch (cs->dc.hfcpci.ph_state) {

2
drivers/isdn/hisax/hfc_sx.c
View File

@ -1255,8 +1255,6 @@ hfcsx_bh(struct work_struct *work)
container_of(work, struct IsdnCardState, tqueue);
u_long flags;
if (!cs)
return;
if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) {
if (!cs->hw.hfcsx.nt_mode)
switch (cs->dc.hfcsx.ph_state) {

2
drivers/isdn/hisax/icc.c
View File

@ -83,8 +83,6 @@ icc_bh(struct work_struct *work)
container_of(work, struct IsdnCardState, tqueue);
struct PStack *stptr;
if (!cs)
return;
if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) {
if (cs->debug)
debugl1(cs, "D-Channel Busy cleared");

2
drivers/isdn/hisax/isac.c
View File

@ -86,8 +86,6 @@ isac_bh(struct work_struct *work)
container_of(work, struct IsdnCardState, tqueue);
struct PStack *stptr;
if (!cs)
return;
if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) {
if (cs->debug)
debugl1(cs, "D-Channel Busy cleared");

70
drivers/isdn/hisax/isdnhdlc.h
View File

@ -1,70 +0,0 @@
/*
* isdnhdlc.h -- General purpose ISDN HDLC decoder.
*
* Implementation of a HDLC decoder/encoder in software.
* Neccessary because some ISDN devices don't have HDLC
* controllers. Also included: a bit reversal table.
*
*Copyright (C) 2002 Wolfgang Mües <wolfgang@iksw-muees.de>
* 2001 Frode Isaksen <fisaksen@bewan.com>
* 2001 Kai Germaschewski <kai.germaschewski@gmx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ISDNHDLC_H__
#define __ISDNHDLC_H__
struct isdnhdlc_vars {
int bit_shift;
int hdlc_bits1;
int data_bits;
int ffbit_shift; // encoding only
int state;
int dstpos;
unsigned short crc;
unsigned char cbin;
unsigned char shift_reg;
unsigned char ffvalue;
unsigned int data_received:1; // set if transferring data
unsigned int dchannel:1; // set if D channel (send idle instead of flags)
unsigned int do_adapt56:1; // set if 56K adaptation
unsigned int do_closing:1; // set if in closing phase (need to send CRC + flag
};
/*
The return value from isdnhdlc_decode is
the frame length, 0 if no complete frame was decoded,
or a negative error number
*/
#define HDLC_FRAMING_ERROR 1
#define HDLC_CRC_ERROR 2
#define HDLC_LENGTH_ERROR 3
extern void isdnhdlc_rcv_init (struct isdnhdlc_vars *hdlc, int do_adapt56);
extern int isdnhdlc_decode (struct isdnhdlc_vars *hdlc, const unsigned char *src, int slen,int *count,
unsigned char *dst, int dsize);
extern void isdnhdlc_out_init (struct isdnhdlc_vars *hdlc,int is_d_channel,int do_adapt56);
extern int isdnhdlc_encode (struct isdnhdlc_vars *hdlc,const unsigned char *src,unsigned short slen,int *count,
unsigned char *dst,int dsize);
#endif /* __ISDNHDLC_H__ */

12
drivers/isdn/hisax/isdnl1.c
View File

@ -647,8 +647,6 @@ static struct FsmNode L1SFnList[] __initdata =
{ST_L1_F8, EV_TIMER_DEACT, l1_timer_deact},
};
#define L1S_FN_COUNT (sizeof(L1SFnList)/sizeof(struct FsmNode))
#ifdef HISAX_UINTERFACE
static void
l1_deact_req_u(struct FsmInst *fi, int event, void *arg)
@ -706,8 +704,6 @@ static struct FsmNode L1UFnList[] __initdata =
{ST_L1_RESET, EV_TIMER_DEACT, l1_timer_deact},
};
#define L1U_FN_COUNT (sizeof(L1UFnList)/sizeof(struct FsmNode))
#endif
static void
@ -754,8 +750,6 @@ static struct FsmNode L1BFnList[] __initdata =
{ST_L1_WAIT_DEACT, EV_TIMER_DEACT, l1b_timer_deact},
};
#define L1B_FN_COUNT (sizeof(L1BFnList)/sizeof(struct FsmNode))
int __init
Isdnl1New(void)
{
@ -765,7 +759,7 @@ Isdnl1New(void)
l1fsm_s.event_count = L1_EVENT_COUNT;
l1fsm_s.strEvent = strL1Event;
l1fsm_s.strState = strL1SState;
retval = FsmNew(&l1fsm_s, L1SFnList, L1S_FN_COUNT);
retval = FsmNew(&l1fsm_s, L1SFnList, ARRAY_SIZE(L1SFnList));
if (retval)
return retval;
@ -773,7 +767,7 @@ Isdnl1New(void)
l1fsm_b.event_count = L1_EVENT_COUNT;
l1fsm_b.strEvent = strL1Event;
l1fsm_b.strState = strL1BState;
retval = FsmNew(&l1fsm_b, L1BFnList, L1B_FN_COUNT);
retval = FsmNew(&l1fsm_b, L1BFnList, ARRAY_SIZE(L1BFnList));
if (retval) {
FsmFree(&l1fsm_s);
return retval;
@ -783,7 +777,7 @@ Isdnl1New(void)
l1fsm_u.event_count = L1_EVENT_COUNT;
l1fsm_u.strEvent = strL1Event;
l1fsm_u.strState = strL1UState;
retval = FsmNew(&l1fsm_u, L1UFnList, L1U_FN_COUNT);
retval = FsmNew(&l1fsm_u, L1UFnList, ARRAY_SIZE(L1UFnList));
if (retval) {
FsmFree(&l1fsm_s);
FsmFree(&l1fsm_b);

4
drivers/isdn/hisax/isdnl2.c
View File

@ -1623,8 +1623,6 @@ static struct FsmNode L2FnList[] __initdata =
{ST_L2_8, EV_L1_DEACTIVATE, l2_persistent_da},
};
#define L2_FN_COUNT (sizeof(L2FnList)/sizeof(struct FsmNode))
static void
isdnl2_l1l2(struct PStack *st, int pr, void *arg)
{
@ -1836,7 +1834,7 @@ Isdnl2New(void)
l2fsm.event_count = L2_EVENT_COUNT;
l2fsm.strEvent = strL2Event;
l2fsm.strState = strL2State;
return FsmNew(&l2fsm, L2FnList, L2_FN_COUNT);
return FsmNew(&l2fsm, L2FnList, ARRAY_SIZE(L2FnList));
}
void

4
drivers/isdn/hisax/isdnl3.c
View File

@ -543,8 +543,6 @@ static struct FsmNode L3FnList[] __initdata =
};
/* *INDENT-ON* */
#define L3_FN_COUNT (sizeof(L3FnList)/sizeof(struct FsmNode))
void
l3_msg(struct PStack *st, int pr, void *arg)
{
@ -587,7 +585,7 @@ Isdnl3New(void)
l3fsm.event_count = L3_EVENT_COUNT;
l3fsm.strEvent = strL3Event;
l3fsm.strState = strL3State;
return FsmNew(&l3fsm, L3FnList, L3_FN_COUNT);
return FsmNew(&l3fsm, L3FnList, ARRAY_SIZE(L3FnList));
}
void

20
drivers/isdn/hisax/l3_1tr6.c
View File

@ -698,9 +698,6 @@ static struct stateentry downstl[] =
CC_T308_2, l3_1tr6_t308_2},
};
#define DOWNSTL_LEN \
(sizeof(downstl) / sizeof(struct stateentry))
static struct stateentry datastln1[] =
{
{SBIT(0),
@ -735,9 +732,6 @@ static struct stateentry datastln1[] =
MT_N1_REL_ACK, l3_1tr6_rel_ack}
};
#define DATASTLN1_LEN \
(sizeof(datastln1) / sizeof(struct stateentry))
static struct stateentry manstatelist[] =
{
{SBIT(2),
@ -746,8 +740,6 @@ static struct stateentry manstatelist[] =
DL_RELEASE | INDICATION, l3_1tr6_dl_release},
};
#define MANSLLEN \
(sizeof(manstatelist) / sizeof(struct stateentry))
/* *INDENT-ON* */
static void
@ -840,11 +832,11 @@ up1tr6(struct PStack *st, int pr, void *arg)
mt = MT_N1_INVALID;
}
}
for (i = 0; i < DATASTLN1_LEN; i++)
for (i = 0; i < ARRAY_SIZE(datastln1); i++)
if ((mt == datastln1[i].primitive) &&
((1 << proc->state) & datastln1[i].state))
break;
if (i == DATASTLN1_LEN) {
if (i == ARRAY_SIZE(datastln1)) {
dev_kfree_skb(skb);
if (st->l3.debug & L3_DEB_STATE) {
sprintf(tmp, "up1tr6%sstate %d mt %x unhandled",
@ -892,11 +884,11 @@ down1tr6(struct PStack *st, int pr, void *arg)
proc = arg;
}
for (i = 0; i < DOWNSTL_LEN; i++)
for (i = 0; i < ARRAY_SIZE(downstl); i++)
if ((pr == downstl[i].primitive) &&
((1 << proc->state) & downstl[i].state))
break;
if (i == DOWNSTL_LEN) {
if (i == ARRAY_SIZE(downstl)) {
if (st->l3.debug & L3_DEB_STATE) {
sprintf(tmp, "down1tr6 state %d prim %d unhandled",
proc->state, pr);
@ -922,11 +914,11 @@ man1tr6(struct PStack *st, int pr, void *arg)
printk(KERN_ERR "HiSax man1tr6 without proc pr=%04x\n", pr);
return;
}
for (i = 0; i < MANSLLEN; i++)
for (i = 0; i < ARRAY_SIZE(manstatelist); i++)
if ((pr == manstatelist[i].primitive) &&
((1 << proc->state) & manstatelist[i].state))
break;
if (i == MANSLLEN) {
if (i == ARRAY_SIZE(manstatelist)) {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "cr %d man1tr6 state %d prim %d unhandled",
proc->callref & 0x7f, proc->state, pr);

26
drivers/isdn/hisax/l3dss1.c
View File

@ -2820,9 +2820,6 @@ static struct stateentry downstatelist[] =
CC_T309, l3dss1_dl_release},
};
#define DOWNSLLEN \
(sizeof(downstatelist) / sizeof(struct stateentry))
static struct stateentry datastatelist[] =
{
{ALL_STATES,
@ -2875,9 +2872,6 @@ static struct stateentry datastatelist[] =
MT_RESUME_REJECT, l3dss1_resume_rej},
};
#define DATASLLEN \
(sizeof(datastatelist) / sizeof(struct stateentry))
static struct stateentry globalmes_list[] =
{
{ALL_STATES,
@ -2888,8 +2882,6 @@ static struct stateentry globalmes_list[] =
MT_RESTART_ACKNOWLEDGE, l3dss1_restart_ack},
*/
};
#define GLOBALM_LEN \
(sizeof(globalmes_list) / sizeof(struct stateentry))
static struct stateentry manstatelist[] =
{
@ -2903,8 +2895,6 @@ static struct stateentry manstatelist[] =
DL_RELEASE | INDICATION, l3dss1_dl_release},
};
#define MANSLLEN \
(sizeof(manstatelist) / sizeof(struct stateentry))
/* *INDENT-ON* */
@ -2918,11 +2908,11 @@ global_handler(struct PStack *st, int mt, struct sk_buff *skb)
struct l3_process *proc = st->l3.global;
proc->callref = skb->data[2]; /* cr flag */
for (i = 0; i < GLOBALM_LEN; i++)
for (i = 0; i < ARRAY_SIZE(globalmes_list); i++)
if ((mt == globalmes_list[i].primitive) &&
((1 << proc->state) & globalmes_list[i].state))
break;
if (i == GLOBALM_LEN) {
if (i == ARRAY_SIZE(globalmes_list)) {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "dss1 global state %d mt %x unhandled",
proc->state, mt);
@ -3097,11 +3087,11 @@ dss1up(struct PStack *st, int pr, void *arg)
}
if ((p = findie(skb->data, skb->len, IE_DISPLAY, 0)) != NULL)
l3dss1_deliver_display(proc, pr, p); /* Display IE included */
for (i = 0; i < DATASLLEN; i++)
for (i = 0; i < ARRAY_SIZE(datastatelist); i++)
if ((mt == datastatelist[i].primitive) &&
((1 << proc->state) & datastatelist[i].state))
break;
if (i == DATASLLEN) {
if (i == ARRAY_SIZE(datastatelist)) {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "dss1up%sstate %d mt %#x unhandled",
(pr == (DL_DATA | INDICATION)) ? " " : "(broadcast) ",
@ -3156,11 +3146,11 @@ dss1down(struct PStack *st, int pr, void *arg)
return;
}
for (i = 0; i < DOWNSLLEN; i++)
for (i = 0; i < ARRAY_SIZE(downstatelist); i++)
if ((pr == downstatelist[i].primitive) &&
((1 << proc->state) & downstatelist[i].state))
break;
if (i == DOWNSLLEN) {
if (i == ARRAY_SIZE(downstatelist)) {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "dss1down state %d prim %#x unhandled",
proc->state, pr);
@ -3184,11 +3174,11 @@ dss1man(struct PStack *st, int pr, void *arg)
printk(KERN_ERR "HiSax dss1man without proc pr=%04x\n", pr);
return;
}
for (i = 0; i < MANSLLEN; i++)
for (i = 0; i < ARRAY_SIZE(manstatelist); i++)
if ((pr == manstatelist[i].primitive) &&
((1 << proc->state) & manstatelist[i].state))
break;
if (i == MANSLLEN) {
if (i == ARRAY_SIZE(manstatelist)) {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "cr %d dss1man state %d prim %#x unhandled",
proc->callref & 0x7f, proc->state, pr);

26
drivers/isdn/hisax/l3ni1.c
View File

@ -2755,9 +2755,6 @@ static struct stateentry downstatelist[] =
CC_TSPID, l3ni1_spid_tout },
};
#define DOWNSLLEN \
(sizeof(downstatelist) / sizeof(struct stateentry))
static struct stateentry datastatelist[] =
{
{ALL_STATES,
@ -2810,9 +2807,6 @@ static struct stateentry datastatelist[] =
MT_RESUME_REJECT, l3ni1_resume_rej},
};
#define DATASLLEN \
(sizeof(datastatelist) / sizeof(struct stateentry))
static struct stateentry globalmes_list[] =
{
{ALL_STATES,
@ -2825,8 +2819,6 @@ static struct stateentry globalmes_list[] =
{ SBIT( 0 ), MT_DL_ESTABLISHED, l3ni1_spid_send },
{ SBIT( 20 ) | SBIT( 21 ) | SBIT( 22 ), MT_INFORMATION, l3ni1_spid_epid },
};
#define GLOBALM_LEN \
(sizeof(globalmes_list) / sizeof(struct stateentry))
static struct stateentry manstatelist[] =
{
@ -2840,8 +2832,6 @@ static struct stateentry manstatelist[] =
DL_RELEASE | INDICATION, l3ni1_dl_release},
};
#define MANSLLEN \
(sizeof(manstatelist) / sizeof(struct stateentry))
/* *INDENT-ON* */
@ -2858,11 +2848,11 @@ global_handler(struct PStack *st, int mt, struct sk_buff *skb)
proc->callref = skb->data[2]; /* cr flag */
else
proc->callref = 0;
for (i = 0; i < GLOBALM_LEN; i++)
for (i = 0; i < ARRAY_SIZE(globalmes_list); i++)
if ((mt == globalmes_list[i].primitive) &&
((1 << proc->state) & globalmes_list[i].state))
break;
if (i == GLOBALM_LEN) {
if (i == ARRAY_SIZE(globalmes_list)) {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "ni1 global state %d mt %x unhandled",
proc->state, mt);
@ -3049,11 +3039,11 @@ ni1up(struct PStack *st, int pr, void *arg)
}
if ((p = findie(skb->data, skb->len, IE_DISPLAY, 0)) != NULL)
l3ni1_deliver_display(proc, pr, p); /* Display IE included */
for (i = 0; i < DATASLLEN; i++)
for (i = 0; i < ARRAY_SIZE(datastatelist); i++)
if ((mt == datastatelist[i].primitive) &&
((1 << proc->state) & datastatelist[i].state))
break;
if (i == DATASLLEN) {
if (i == ARRAY_SIZE(datastatelist)) {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "ni1up%sstate %d mt %#x unhandled",
(pr == (DL_DATA | INDICATION)) ? " " : "(broadcast) ",
@ -3108,11 +3098,11 @@ ni1down(struct PStack *st, int pr, void *arg)
return;
}
for (i = 0; i < DOWNSLLEN; i++)
for (i = 0; i < ARRAY_SIZE(downstatelist); i++)
if ((pr == downstatelist[i].primitive) &&
((1 << proc->state) & downstatelist[i].state))
break;
if (i == DOWNSLLEN) {
if (i == ARRAY_SIZE(downstatelist)) {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "ni1down state %d prim %#x unhandled",
proc->state, pr);
@ -3136,11 +3126,11 @@ ni1man(struct PStack *st, int pr, void *arg)
printk(KERN_ERR "HiSax ni1man without proc pr=%04x\n", pr);
return;
}
for (i = 0; i < MANSLLEN; i++)
for (i = 0; i < ARRAY_SIZE(manstatelist); i++)
if ((pr == manstatelist[i].primitive) &&
((1 << proc->state) & manstatelist[i].state))
break;
if (i == MANSLLEN) {
if (i == ARRAY_SIZE(manstatelist)) {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "cr %d ni1man state %d prim %#x unhandled",
proc->callref & 0x7f, proc->state, pr);

24
drivers/isdn/hisax/q931.c
View File

@ -140,7 +140,7 @@ struct MessageType {
}
};
#define MTSIZE sizeof(mtlist)/sizeof(struct MessageType)
#define MTSIZE ARRAY_SIZE(mtlist)
static
struct MessageType mt_n0[] =
@ -157,7 +157,7 @@ struct MessageType mt_n0[] =
{MT_N0_CLO_ACK, "CLOse ACKnowledge"}
};
#define MT_N0_LEN (sizeof(mt_n0) / sizeof(struct MessageType))
#define MT_N0_LEN ARRAY_SIZE(mt_n0)
static
struct MessageType mt_n1[] =
@ -194,7 +194,7 @@ struct MessageType mt_n1[] =
{MT_N1_STAT, "STATus"}
};
#define MT_N1_LEN (sizeof(mt_n1) / sizeof(struct MessageType))
#define MT_N1_LEN ARRAY_SIZE(mt_n1)
static int
@ -438,7 +438,7 @@ struct CauseValue {
},
};
#define CVSIZE sizeof(cvlist)/sizeof(struct CauseValue)
#define CVSIZE ARRAY_SIZE(cvlist)
static
int
@ -516,7 +516,7 @@ struct MessageType cause_1tr6[] =
{CAUSE_UserInfoDiscarded, "User Info Discarded"}
};
static int cause_1tr6_len = (sizeof(cause_1tr6) / sizeof(struct MessageType));
static int cause_1tr6_len = ARRAY_SIZE(cause_1tr6);
static int
prcause_1tr6(char *dest, u_char * p)
@ -865,7 +865,7 @@ struct DTag { /* Display tags */
{ 0x96, "Redirection name" },
{ 0x9e, "Text" },
};
#define DTAGSIZE sizeof(dtaglist)/sizeof(struct DTag)
#define DTAGSIZE ARRAY_SIZE(dtaglist)
static int
disptext_ni1(char *dest, u_char * p)
@ -1074,7 +1074,7 @@ struct InformationElement {
};
#define IESIZE sizeof(ielist)/sizeof(struct InformationElement)
#define IESIZE ARRAY_SIZE(ielist)
static
struct InformationElement ielist_ni1[] = {
@ -1102,7 +1102,7 @@ struct InformationElement ielist_ni1[] = {
};
#define IESIZE_NI1 sizeof(ielist_ni1)/sizeof(struct InformationElement)
#define IESIZE_NI1 ARRAY_SIZE(ielist_ni1)
static
struct InformationElement ielist_ni1_cs5[] = {
@ -1110,14 +1110,14 @@ struct InformationElement ielist_ni1_cs5[] = {
{ 0x2a, "Display text", disptext_ni1 },
};
#define IESIZE_NI1_CS5 sizeof(ielist_ni1_cs5)/sizeof(struct InformationElement)
#define IESIZE_NI1_CS5 ARRAY_SIZE(ielist_ni1_cs5)
static
struct InformationElement ielist_ni1_cs6[] = {
{ 0x7b, "Call appearance", general_ni1 },
};
#define IESIZE_NI1_CS6 sizeof(ielist_ni1_cs6)/sizeof(struct InformationElement)
#define IESIZE_NI1_CS6 ARRAY_SIZE(ielist_ni1_cs6)
static struct InformationElement we_0[] =
{
@ -1133,7 +1133,7 @@ static struct InformationElement we_0[] =
{WE0_userInfo, "User Info", general}
};
#define WE_0_LEN (sizeof(we_0) / sizeof(struct InformationElement))
#define WE_0_LEN ARRAY_SIZE(we_0)
static struct InformationElement we_6[] =
{
@ -1145,7 +1145,7 @@ static struct InformationElement we_6[] =
{WE6_statusCalled, "Status Called", general},
{WE6_addTransAttr, "Additional Transmission Attributes", general}
};
#define WE_6_LEN (sizeof(we_6) / sizeof(struct InformationElement))
#define WE_6_LEN ARRAY_SIZE(we_6)
int
QuickHex(char *txt, u_char * p, int cnt)

2
drivers/isdn/hisax/st5481.h
View File

@ -226,7 +226,7 @@ printk(KERN_WARNING "%s:%s: " format "\n" , __FILE__, __func__ , ## arg)
#define INFO(format, arg...) \
printk(KERN_INFO "%s:%s: " format "\n" , __FILE__, __func__ , ## arg)
#include "isdnhdlc.h"
#include <linux/isdn/hdlc.h>
#include "fsm.h"
#include "hisax_if.h"
#include <linux/skbuff.h>

5
drivers/isdn/hisax/st5481_b.c
View File

@ -218,7 +218,10 @@ static void st5481B_mode(struct st5481_bcs *bcs, int mode)
if (bcs->mode != L1_MODE_NULL) {
// Open the B channel
if (bcs->mode != L1_MODE_TRANS) {
isdnhdlc_out_init(&b_out->hdlc_state, 0, bcs->mode == L1_MODE_HDLC_56K);
u32 features = HDLC_BITREVERSE;
if (bcs->mode == L1_MODE_HDLC_56K)
features |= HDLC_56KBIT;
isdnhdlc_out_init(&b_out->hdlc_state, features);
}
st5481_usb_pipe_reset(adapter, (bcs->channel+1)*2, NULL, NULL);

2
drivers/isdn/hisax/st5481_d.c
View File

@ -417,7 +417,7 @@ static void dout_start_xmit(struct FsmInst *fsm, int event, void *arg)
DBG(2,"len=%d",skb->len);
isdnhdlc_out_init(&d_out->hdlc_state, 1, 0);
isdnhdlc_out_init(&d_out->hdlc_state, HDLC_DCHANNEL | HDLC_BITREVERSE);
if (test_and_set_bit(buf_nr, &d_out->busy)) {
WARNING("ep %d urb %d busy %#lx", EP_D_OUT, buf_nr, d_out->busy);

11
drivers/isdn/hisax/st5481_usb.c
View File

@ -637,10 +637,13 @@ void st5481_in_mode(struct st5481_in *in, int mode)
usb_unlink_urb(in->urb[1]);
if (in->mode != L1_MODE_NULL) {
if (in->mode != L1_MODE_TRANS)
isdnhdlc_rcv_init(&in->hdlc_state,
in->mode == L1_MODE_HDLC_56K);
if (in->mode != L1_MODE_TRANS) {
u32 features = HDLC_BITREVERSE;
if (in->mode == L1_MODE_HDLC_56K)
features |= HDLC_56KBIT;
isdnhdlc_rcv_init(&in->hdlc_state, features);
}
st5481_usb_pipe_reset(in->adapter, in->ep, NULL, NULL);
st5481_usb_device_ctrl_msg(in->adapter, in->counter,
in->packet_size,

4
drivers/isdn/hisax/tei.c
View File

@ -447,8 +447,6 @@ static struct FsmNode TeiFnList[] __initdata =
{ST_TEI_IDVERIFY, EV_CHKREQ, tei_id_chk_req},
};
#define TEI_FN_COUNT (sizeof(TeiFnList)/sizeof(struct FsmNode))
int __init
TeiNew(void)
{
@ -456,7 +454,7 @@ TeiNew(void)
teifsm.event_count = TEI_EVENT_COUNT;
teifsm.strEvent = strTeiEvent;
teifsm.strState = strTeiState;
return FsmNew(&teifsm, TeiFnList, TEI_FN_COUNT);
return FsmNew(&teifsm, TeiFnList, ARRAY_SIZE(TeiFnList));
}
void

2
drivers/isdn/hisax/w6692.c
View File

@ -105,8 +105,6 @@ W6692_bh(struct work_struct *work)
container_of(work, struct IsdnCardState, tqueue);
struct PStack *stptr;
if (!cs)
return;
if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) {
if (cs->debug)
debugl1(cs, "D-Channel Busy cleared");

11
drivers/isdn/i4l/Kconfig
View File

@ -2,6 +2,8 @@
# Old ISDN4Linux config
#
if ISDN_I4L
config ISDN_PPP
bool "Support synchronous PPP"
depends on INET
@ -135,3 +137,12 @@ source "drivers/isdn/act2000/Kconfig"
source "drivers/isdn/hysdn/Kconfig"
endmenu
# end ISDN_I4L
endif
config ISDN_HDLC
tristate
depends on HISAX_ST5481
select CRC_CCITT
select BITREVERSE

1
drivers/isdn/i4l/Makefile
View File

@ -4,6 +4,7 @@
obj-$(CONFIG_ISDN_I4L) += isdn.o
obj-$(CONFIG_ISDN_PPP_BSDCOMP) += isdn_bsdcomp.o
obj-$(CONFIG_ISDN_HDLC) += isdnhdlc.o
# Multipart objects.

429
drivers/isdn/hisax/isdnhdlc.c → drivers/isdn/i4l/isdnhdlc.c
View File

@ -1,29 +1,32 @@
/*
* isdnhdlc.c -- General purpose ISDN HDLC decoder.
*
*Copyright (C) 2002 Wolfgang Mües <wolfgang@iksw-muees.de>
* 2001 Frode Isaksen <fisaksen@bewan.com>
* 2001 Kai Germaschewski <kai.germaschewski@gmx.de>
* Copyright (C)
* 2009 Karsten Keil <keil@b1-systems.de>
* 2002 Wolfgang Mües <wolfgang@iksw-muees.de>
* 2001 Frode Isaksen <fisaksen@bewan.com>
* 2001 Kai Germaschewski <kai.germaschewski@gmx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/crc-ccitt.h>
#include "isdnhdlc.h"
#include <linux/isdn/hdlc.h>
#include <linux/bitrev.h>
/*-------------------------------------------------------------------*/
@ -36,44 +39,32 @@ MODULE_LICENSE("GPL");
/*-------------------------------------------------------------------*/
enum {
HDLC_FAST_IDLE,HDLC_GET_FLAG_B0,HDLC_GETFLAG_B1A6,HDLC_GETFLAG_B7,
HDLC_GET_DATA,HDLC_FAST_FLAG
HDLC_FAST_IDLE, HDLC_GET_FLAG_B0, HDLC_GETFLAG_B1A6, HDLC_GETFLAG_B7,
HDLC_GET_DATA, HDLC_FAST_FLAG
};
enum {
HDLC_SEND_DATA,HDLC_SEND_CRC1,HDLC_SEND_FAST_FLAG,
HDLC_SEND_FIRST_FLAG,HDLC_SEND_CRC2,HDLC_SEND_CLOSING_FLAG,
HDLC_SEND_IDLE1,HDLC_SEND_FAST_IDLE,HDLC_SENDFLAG_B0,
HDLC_SENDFLAG_B1A6,HDLC_SENDFLAG_B7,STOPPED
HDLC_SEND_DATA, HDLC_SEND_CRC1, HDLC_SEND_FAST_FLAG,
HDLC_SEND_FIRST_FLAG, HDLC_SEND_CRC2, HDLC_SEND_CLOSING_FLAG,
HDLC_SEND_IDLE1, HDLC_SEND_FAST_IDLE, HDLC_SENDFLAG_B0,
HDLC_SENDFLAG_B1A6, HDLC_SENDFLAG_B7, STOPPED, HDLC_SENDFLAG_ONE
};
void isdnhdlc_rcv_init (struct isdnhdlc_vars *hdlc, int do_adapt56)
void isdnhdlc_rcv_init(struct isdnhdlc_vars *hdlc, u32 features)
{
hdlc->bit_shift = 0;
hdlc->hdlc_bits1 = 0;
hdlc->data_bits = 0;
hdlc->ffbit_shift = 0;
hdlc->data_received = 0;
memset(hdlc, 0, sizeof(struct isdnhdlc_vars));
hdlc->state = HDLC_GET_DATA;
hdlc->do_adapt56 = do_adapt56;
hdlc->dchannel = 0;
hdlc->crc = 0;
hdlc->cbin = 0;
hdlc->shift_reg = 0;
hdlc->ffvalue = 0;
hdlc->dstpos = 0;
if (features & HDLC_56KBIT)
hdlc->do_adapt56 = 1;
if (features & HDLC_BITREVERSE)
hdlc->do_bitreverse = 1;
}
EXPORT_SYMBOL(isdnhdlc_out_init);
void isdnhdlc_out_init (struct isdnhdlc_vars *hdlc, int is_d_channel, int do_adapt56)
void isdnhdlc_out_init(struct isdnhdlc_vars *hdlc, u32 features)
{
hdlc->bit_shift = 0;
hdlc->hdlc_bits1 = 0;
hdlc->data_bits = 0;
hdlc->ffbit_shift = 0;
hdlc->data_received = 0;
hdlc->do_closing = 0;
hdlc->ffvalue = 0;
if (is_d_channel) {
memset(hdlc, 0, sizeof(struct isdnhdlc_vars));
if (features & HDLC_DCHANNEL) {
hdlc->dchannel = 1;
hdlc->state = HDLC_SEND_FIRST_FLAG;
} else {
@ -82,16 +73,32 @@ void isdnhdlc_out_init (struct isdnhdlc_vars *hdlc, int is_d_channel, int do_ada
hdlc->ffvalue = 0x7e;
}
hdlc->cbin = 0x7e;
hdlc->bit_shift = 0;
if(do_adapt56){
if (features & HDLC_56KBIT) {
hdlc->do_adapt56 = 1;
hdlc->data_bits = 0;
hdlc->state = HDLC_SENDFLAG_B0;
} else {
hdlc->do_adapt56 = 0;
} else
hdlc->data_bits = 8;
if (features & HDLC_BITREVERSE)
hdlc->do_bitreverse = 1;
}
EXPORT_SYMBOL(isdnhdlc_rcv_init);
static int
check_frame(struct isdnhdlc_vars *hdlc)
{
int status;
if (hdlc->dstpos < 2) /* too small - framing error */
status = -HDLC_FRAMING_ERROR;
else if (hdlc->crc != 0xf0b8) /* crc error */
status = -HDLC_CRC_ERROR;
else {
/* remove CRC */
hdlc->dstpos -= 2;
/* good frame */
status = hdlc->dstpos;
}
hdlc->shift_reg = 0;
return status;
}
/*
@ -121,40 +128,67 @@ void isdnhdlc_out_init (struct isdnhdlc_vars *hdlc, int is_d_channel, int do_ada
returns - number of decoded bytes in the destination buffer and status
flag.
*/
int isdnhdlc_decode (struct isdnhdlc_vars *hdlc, const unsigned char *src,
int slen, int *count, unsigned char *dst, int dsize)
int isdnhdlc_decode(struct isdnhdlc_vars *hdlc, const u8 *src, int slen,
int *count, u8 *dst, int dsize)
{
int status=0;
int status = 0;
static const unsigned char fast_flag[]={
0x00,0x00,0x00,0x20,0x30,0x38,0x3c,0x3e,0x3f
static const unsigned char fast_flag[] = {
0x00, 0x00, 0x00, 0x20, 0x30, 0x38, 0x3c, 0x3e, 0x3f
};
static const unsigned char fast_flag_value[]={
0x00,0x7e,0xfc,0xf9,0xf3,0xe7,0xcf,0x9f,0x3f
static const unsigned char fast_flag_value[] = {
0x00, 0x7e, 0xfc, 0xf9, 0xf3, 0xe7, 0xcf, 0x9f, 0x3f
};
static const unsigned char fast_abort[]={
0x00,0x00,0x80,0xc0,0xe0,0xf0,0xf8,0xfc,0xfe,0xff
static const unsigned char fast_abort[] = {
0x00, 0x00, 0x80, 0xc0, 0xe0, 0xf0, 0xf8, 0xfc, 0xfe, 0xff
};
#define handle_fast_flag(h) \
do {\
if (h->cbin == fast_flag[h->bit_shift]) {\
h->ffvalue = fast_flag_value[h->bit_shift];\
h->state = HDLC_FAST_FLAG;\
h->ffbit_shift = h->bit_shift;\
h->bit_shift = 1;\
} else {\
h->state = HDLC_GET_DATA;\
h->data_received = 0;\
} \
} while (0)
#define handle_abort(h) \
do {\
h->shift_reg = fast_abort[h->ffbit_shift - 1];\
h->hdlc_bits1 = h->ffbit_shift - 2;\
if (h->hdlc_bits1 < 0)\
h->hdlc_bits1 = 0;\
h->data_bits = h->ffbit_shift - 1;\
h->state = HDLC_GET_DATA;\
h->data_received = 0;\
} while (0)
*count = slen;
while(slen > 0){
if(hdlc->bit_shift==0){
hdlc->cbin = *src++;
while (slen > 0) {
if (hdlc->bit_shift == 0) {
/* the code is for bitreverse streams */
if (hdlc->do_bitreverse == 0)
hdlc->cbin = bitrev8(*src++);
else
hdlc->cbin = *src++;
slen--;
hdlc->bit_shift = 8;
if(hdlc->do_adapt56){
hdlc->bit_shift --;
}
if (hdlc->do_adapt56)
hdlc->bit_shift--;
}
switch(hdlc->state){
switch (hdlc->state) {
case STOPPED:
return 0;
case HDLC_FAST_IDLE:
if(hdlc->cbin == 0xff){
if (hdlc->cbin == 0xff) {
hdlc->bit_shift = 0;
break;
}
@ -163,32 +197,30 @@ int isdnhdlc_decode (struct isdnhdlc_vars *hdlc, const unsigned char *src,
hdlc->bit_shift = 8;
break;
case HDLC_GET_FLAG_B0:
if(!(hdlc->cbin & 0x80)) {
if (!(hdlc->cbin & 0x80)) {
hdlc->state = HDLC_GETFLAG_B1A6;
hdlc->hdlc_bits1 = 0;
} else {
if(!hdlc->do_adapt56){
if(++hdlc->hdlc_bits1 >=8 ) if(hdlc->bit_shift==1)
if ((!hdlc->do_adapt56) &&
(++hdlc->hdlc_bits1 >= 8) &&
(hdlc->bit_shift == 1))
hdlc->state = HDLC_FAST_IDLE;
}
}
hdlc->cbin<<=1;
hdlc->bit_shift --;
hdlc->cbin <<= 1;
hdlc->bit_shift--;
break;
case HDLC_GETFLAG_B1A6:
if(hdlc->cbin & 0x80){
if (hdlc->cbin & 0x80) {
hdlc->hdlc_bits1++;
if(hdlc->hdlc_bits1==6){
if (hdlc->hdlc_bits1 == 6)
hdlc->state = HDLC_GETFLAG_B7;
}
} else {
} else
hdlc->hdlc_bits1 = 0;
}
hdlc->cbin<<=1;
hdlc->bit_shift --;
hdlc->cbin <<= 1;
hdlc->bit_shift--;
break;
case HDLC_GETFLAG_B7:
if(hdlc->cbin & 0x80) {
if (hdlc->cbin & 0x80) {
hdlc->state = HDLC_GET_FLAG_B0;
} else {
hdlc->state = HDLC_GET_DATA;
@ -198,74 +230,55 @@ int isdnhdlc_decode (struct isdnhdlc_vars *hdlc, const unsigned char *src,
hdlc->data_bits = 0;
hdlc->data_received = 0;
}
hdlc->cbin<<=1;
hdlc->bit_shift --;
hdlc->cbin <<= 1;
hdlc->bit_shift--;
break;
case HDLC_GET_DATA:
if(hdlc->cbin & 0x80){
if (hdlc->cbin & 0x80) {
hdlc->hdlc_bits1++;
switch(hdlc->hdlc_bits1){
switch (hdlc->hdlc_bits1) {
case 6:
break;
case 7:
if(hdlc->data_received) {
// bad frame
if (hdlc->data_received)
/* bad frame */
status = -HDLC_FRAMING_ERROR;
}
if(!hdlc->do_adapt56){
if(hdlc->cbin==fast_abort[hdlc->bit_shift+1]){
hdlc->state = HDLC_FAST_IDLE;
hdlc->bit_shift=1;
if (!hdlc->do_adapt56) {
if (hdlc->cbin == fast_abort
[hdlc->bit_shift + 1]) {
hdlc->state =
HDLC_FAST_IDLE;
hdlc->bit_shift = 1;
break;
}
} else {
} else
hdlc->state = HDLC_GET_FLAG_B0;
}
break;
default:
hdlc->shift_reg>>=1;
hdlc->shift_reg >>= 1;
hdlc->shift_reg |= 0x80;
hdlc->data_bits++;
break;
}
} else {
switch(hdlc->hdlc_bits1){
switch (hdlc->hdlc_bits1) {
case 5:
break;
case 6:
if(hdlc->data_received){
if (hdlc->dstpos < 2) {
status = -HDLC_FRAMING_ERROR;
} else if (hdlc->crc != 0xf0b8){
// crc error
status = -HDLC_CRC_ERROR;
} else {
// remove CRC
hdlc->dstpos -= 2;
// good frame
status = hdlc->dstpos;
}
}
if (hdlc->data_received)
status = check_frame(hdlc);
hdlc->crc = 0xffff;
hdlc->shift_reg = 0;
hdlc->data_bits = 0;
if(!hdlc->do_adapt56){
if(hdlc->cbin==fast_flag[hdlc->bit_shift]){
hdlc->ffvalue = fast_flag_value[hdlc->bit_shift];
hdlc->state = HDLC_FAST_FLAG;
hdlc->ffbit_shift = hdlc->bit_shift;
hdlc->bit_shift = 1;
} else {
hdlc->state = HDLC_GET_DATA;
hdlc->data_received = 0;
}
} else {
if (!hdlc->do_adapt56)
handle_fast_flag(hdlc);
else {
hdlc->state = HDLC_GET_DATA;
hdlc->data_received = 0;
}
break;
default:
hdlc->shift_reg>>=1;
hdlc->shift_reg >>= 1;
hdlc->data_bits++;
break;
}
@ -278,16 +291,17 @@ int isdnhdlc_decode (struct isdnhdlc_vars *hdlc, const unsigned char *src,
hdlc->bit_shift--;
return status;
}
if(hdlc->data_bits==8){
if (hdlc->data_bits == 8) {
hdlc->data_bits = 0;
hdlc->data_received = 1;
hdlc->crc = crc_ccitt_byte(hdlc->crc, hdlc->shift_reg);
hdlc->crc = crc_ccitt_byte(hdlc->crc,
hdlc->shift_reg);
// good byte received
if (hdlc->dstpos < dsize) {
/* good byte received */
if (hdlc->dstpos < dsize)
dst[hdlc->dstpos++] = hdlc->shift_reg;
} else {
// frame too long
else {
/* frame too long */
status = -HDLC_LENGTH_ERROR;
hdlc->dstpos = 0;
}
@ -296,24 +310,18 @@ int isdnhdlc_decode (struct isdnhdlc_vars *hdlc, const unsigned char *src,
hdlc->bit_shift--;
break;
case HDLC_FAST_FLAG:
if(hdlc->cbin==hdlc->ffvalue){
if (hdlc->cbin == hdlc->ffvalue) {
hdlc->bit_shift = 0;
break;
} else {
if(hdlc->cbin == 0xff){
if (hdlc->cbin == 0xff) {
hdlc->state = HDLC_FAST_IDLE;
hdlc->bit_shift=0;
} else if(hdlc->ffbit_shift==8){
hdlc->bit_shift = 0;
} else if (hdlc->ffbit_shift == 8) {
hdlc->state = HDLC_GETFLAG_B7;
break;
} else {
hdlc->shift_reg = fast_abort[hdlc->ffbit_shift-1];
hdlc->hdlc_bits1 = hdlc->ffbit_shift-2;
if(hdlc->hdlc_bits1<0)hdlc->hdlc_bits1 = 0;
hdlc->data_bits = hdlc->ffbit_shift-1;
hdlc->state = HDLC_GET_DATA;
hdlc->data_received = 0;
}
} else
handle_abort(hdlc);
}
break;
default:
@ -323,7 +331,7 @@ int isdnhdlc_decode (struct isdnhdlc_vars *hdlc, const unsigned char *src,
*count -= slen;
return 0;
}
EXPORT_SYMBOL(isdnhdlc_decode);
/*
isdnhdlc_encode - encodes HDLC frames to a transparent bit stream.
@ -343,59 +351,70 @@ int isdnhdlc_decode (struct isdnhdlc_vars *hdlc, const unsigned char *src,
dsize - destination buffer size
returns - number of encoded bytes in the destination buffer
*/
int isdnhdlc_encode(struct isdnhdlc_vars *hdlc, const unsigned char *src,
unsigned short slen, int *count,
unsigned char *dst, int dsize)
int isdnhdlc_encode(struct isdnhdlc_vars *hdlc, const u8 *src, u16 slen,
int *count, u8 *dst, int dsize)
{
static const unsigned char xfast_flag_value[] = {
0x7e,0x3f,0x9f,0xcf,0xe7,0xf3,0xf9,0xfc,0x7e
0x7e, 0x3f, 0x9f, 0xcf, 0xe7, 0xf3, 0xf9, 0xfc, 0x7e
};
int len = 0;
*count = slen;
/* special handling for one byte frames */
if ((slen == 1) && (hdlc->state == HDLC_SEND_FAST_FLAG))
hdlc->state = HDLC_SENDFLAG_ONE;
while (dsize > 0) {
if(hdlc->bit_shift==0){
if(slen && !hdlc->do_closing){
if (hdlc->bit_shift == 0) {
if (slen && !hdlc->do_closing) {
hdlc->shift_reg = *src++;
slen--;
if (slen == 0)
hdlc->do_closing = 1; /* closing sequence, CRC + flag(s) */
/* closing sequence, CRC + flag(s) */
hdlc->do_closing = 1;
hdlc->bit_shift = 8;
} else {
if(hdlc->state == HDLC_SEND_DATA){
if(hdlc->data_received){
if (hdlc->state == HDLC_SEND_DATA) {
if (hdlc->data_received) {
hdlc->state = HDLC_SEND_CRC1;
hdlc->crc ^= 0xffff;
hdlc->bit_shift = 8;
hdlc->shift_reg = hdlc->crc & 0xff;
} else if(!hdlc->do_adapt56){
hdlc->state = HDLC_SEND_FAST_FLAG;
} else {
hdlc->state = HDLC_SENDFLAG_B0;
}
hdlc->shift_reg =
hdlc->crc & 0xff;
} else if (!hdlc->do_adapt56)
hdlc->state =
HDLC_SEND_FAST_FLAG;
else
hdlc->state =
HDLC_SENDFLAG_B0;
}
}
}
switch(hdlc->state){
switch (hdlc->state) {
case STOPPED:
while (dsize--)
*dst++ = 0xff;
return dsize;
case HDLC_SEND_FAST_FLAG:
hdlc->do_closing = 0;
if(slen == 0){
*dst++ = hdlc->ffvalue;
if (slen == 0) {
/* the code is for bitreverse streams */
if (hdlc->do_bitreverse == 0)
*dst++ = bitrev8(hdlc->ffvalue);
else
*dst++ = hdlc->ffvalue;
len++;
dsize--;
break;
}
if(hdlc->bit_shift==8){
hdlc->cbin = hdlc->ffvalue>>(8-hdlc->data_bits);
/* fall through */
case HDLC_SENDFLAG_ONE:
if (hdlc->bit_shift == 8) {
hdlc->cbin = hdlc->ffvalue >>
(8 - hdlc->data_bits);
hdlc->state = HDLC_SEND_DATA;
hdlc->crc = 0xffff;
hdlc->hdlc_bits1 = 0;
@ -413,17 +432,17 @@ int isdnhdlc_encode(struct isdnhdlc_vars *hdlc, const unsigned char *src,
hdlc->cbin <<= 1;
hdlc->data_bits++;
hdlc->cbin++;
if(++hdlc->hdlc_bits1 == 6)
if (++hdlc->hdlc_bits1 == 6)
hdlc->state = HDLC_SENDFLAG_B7;
break;
case HDLC_SENDFLAG_B7:
hdlc->cbin <<= 1;
hdlc->data_bits++;
if(slen == 0){
if (slen == 0) {
hdlc->state = HDLC_SENDFLAG_B0;
break;
}
if(hdlc->bit_shift==8){
if (hdlc->bit_shift == 8) {
hdlc->state = HDLC_SEND_DATA;
hdlc->crc = 0xffff;
hdlc->hdlc_bits1 = 0;
@ -432,7 +451,7 @@ int isdnhdlc_encode(struct isdnhdlc_vars *hdlc, const unsigned char *src,
break;
case HDLC_SEND_FIRST_FLAG:
hdlc->data_received = 1;
if(hdlc->data_bits==8){
if (hdlc->data_bits == 8) {
hdlc->state = HDLC_SEND_DATA;
hdlc->crc = 0xffff;
hdlc->hdlc_bits1 = 0;
@ -440,11 +459,11 @@ int isdnhdlc_encode(struct isdnhdlc_vars *hdlc, const unsigned char *src,
}
hdlc->cbin <<= 1;
hdlc->data_bits++;
if(hdlc->shift_reg & 0x01)
if (hdlc->shift_reg & 0x01)
hdlc->cbin++;
hdlc->shift_reg >>= 1;
hdlc->bit_shift--;
if(hdlc->bit_shift==0){
if (hdlc->bit_shift == 0) {
hdlc->state = HDLC_SEND_DATA;
hdlc->crc = 0xffff;
hdlc->hdlc_bits1 = 0;
@ -453,14 +472,14 @@ int isdnhdlc_encode(struct isdnhdlc_vars *hdlc, const unsigned char *src,
case HDLC_SEND_DATA:
hdlc->cbin <<= 1;
hdlc->data_bits++;
if(hdlc->hdlc_bits1 == 5){
if (hdlc->hdlc_bits1 == 5) {
hdlc->hdlc_bits1 = 0;
break;
}
if(hdlc->bit_shift==8){
hdlc->crc = crc_ccitt_byte(hdlc->crc, hdlc->shift_reg);
}
if(hdlc->shift_reg & 0x01){
if (hdlc->bit_shift == 8)
hdlc->crc = crc_ccitt_byte(hdlc->crc,
hdlc->shift_reg);
if (hdlc->shift_reg & 0x01) {
hdlc->hdlc_bits1++;
hdlc->cbin++;
hdlc->shift_reg >>= 1;
@ -474,11 +493,11 @@ int isdnhdlc_encode(struct isdnhdlc_vars *hdlc, const unsigned char *src,
case HDLC_SEND_CRC1:
hdlc->cbin <<= 1;
hdlc->data_bits++;
if(hdlc->hdlc_bits1 == 5){
if (hdlc->hdlc_bits1 == 5) {
hdlc->hdlc_bits1 = 0;
break;
}
if(hdlc->shift_reg & 0x01){
if (hdlc->shift_reg & 0x01) {
hdlc->hdlc_bits1++;
hdlc->cbin++;
hdlc->shift_reg >>= 1;
@ -488,7 +507,7 @@ int isdnhdlc_encode(struct isdnhdlc_vars *hdlc, const unsigned char *src,
hdlc->shift_reg >>= 1;
hdlc->bit_shift--;
}
if(hdlc->bit_shift==0){
if (hdlc->bit_shift == 0) {
hdlc->shift_reg = (hdlc->crc >> 8);
hdlc->state = HDLC_SEND_CRC2;
hdlc->bit_shift = 8;
@ -497,11 +516,11 @@ int isdnhdlc_encode(struct isdnhdlc_vars *hdlc, const unsigned char *src,
case HDLC_SEND_CRC2:
hdlc->cbin <<= 1;
hdlc->data_bits++;
if(hdlc->hdlc_bits1 == 5){
if (hdlc->hdlc_bits1 == 5) {
hdlc->hdlc_bits1 = 0;
break;
}
if(hdlc->shift_reg & 0x01){
if (hdlc->shift_reg & 0x01) {
hdlc->hdlc_bits1++;
hdlc->cbin++;
hdlc->shift_reg >>= 1;
@ -511,7 +530,7 @@ int isdnhdlc_encode(struct isdnhdlc_vars *hdlc, const unsigned char *src,
hdlc->shift_reg >>= 1;
hdlc->bit_shift--;
}
if(hdlc->bit_shift==0){
if (hdlc->bit_shift == 0) {
hdlc->shift_reg = 0x7e;
hdlc->state = HDLC_SEND_CLOSING_FLAG;
hdlc->bit_shift = 8;
@ -520,33 +539,36 @@ int isdnhdlc_encode(struct isdnhdlc_vars *hdlc, const unsigned char *src,
case HDLC_SEND_CLOSING_FLAG:
hdlc->cbin <<= 1;
hdlc->data_bits++;
if(hdlc->hdlc_bits1 == 5){
if (hdlc->hdlc_bits1 == 5) {
hdlc->hdlc_bits1 = 0;
break;
}
if(hdlc->shift_reg & 0x01){
if (hdlc->shift_reg & 0x01)
hdlc->cbin++;
}
hdlc->shift_reg >>= 1;
hdlc->bit_shift--;
if(hdlc->bit_shift==0){
hdlc->ffvalue = xfast_flag_value[hdlc->data_bits];
if(hdlc->dchannel){
if (hdlc->bit_shift == 0) {
hdlc->ffvalue =
xfast_flag_value[hdlc->data_bits];
if (hdlc->dchannel) {
hdlc->ffvalue = 0x7e;
hdlc->state = HDLC_SEND_IDLE1;
hdlc->bit_shift = 8-hdlc->data_bits;
if(hdlc->bit_shift==0)
hdlc->state = HDLC_SEND_FAST_IDLE;
if (hdlc->bit_shift == 0)
hdlc->state =
HDLC_SEND_FAST_IDLE;
} else {
if(!hdlc->do_adapt56){
hdlc->state = HDLC_SEND_FAST_FLAG;
if (!hdlc->do_adapt56) {
hdlc->state =
HDLC_SEND_FAST_FLAG;
hdlc->data_received = 0;
} else {
hdlc->state = HDLC_SENDFLAG_B0;
hdlc->data_received = 0;
}
// Finished with this frame, send flags
if (dsize > 1) dsize = 1;
/* Finished this frame, send flags */
if (dsize > 1)
dsize = 1;
}
}
break;
@ -556,7 +578,7 @@ int isdnhdlc_encode(struct isdnhdlc_vars *hdlc, const unsigned char *src,
hdlc->cbin++;
hdlc->data_bits++;
hdlc->bit_shift--;
if(hdlc->bit_shift==0){
if (hdlc->bit_shift == 0) {
hdlc->state = HDLC_SEND_FAST_IDLE;
hdlc->bit_shift = 0;
}
@ -565,12 +587,17 @@ int isdnhdlc_encode(struct isdnhdlc_vars *hdlc, const unsigned char *src,
hdlc->do_closing = 0;
hdlc->cbin = 0xff;
hdlc->data_bits = 8;
if(hdlc->bit_shift == 8){
if (hdlc->bit_shift == 8) {
hdlc->cbin = 0x7e;
hdlc->state = HDLC_SEND_FIRST_FLAG;
} else {
*dst++ = hdlc->cbin;
hdlc->bit_shift = hdlc->data_bits = 0;
/* the code is for bitreverse streams */
if (hdlc->do_bitreverse == 0)
*dst++ = bitrev8(hdlc->cbin);
else
*dst++ = hdlc->cbin;
hdlc->bit_shift = 0;
hdlc->data_bits = 0;
len++;
dsize = 0;
}
@ -578,15 +605,19 @@ int isdnhdlc_encode(struct isdnhdlc_vars *hdlc, const unsigned char *src,
default:
break;
}
if(hdlc->do_adapt56){
if(hdlc->data_bits==7){
if (hdlc->do_adapt56) {
if (hdlc->data_bits == 7) {
hdlc->cbin <<= 1;
hdlc->cbin++;
hdlc->data_bits++;
}
}
if(hdlc->data_bits==8){
*dst++ = hdlc->cbin;
if (hdlc->data_bits == 8) {
/* the code is for bitreverse streams */
if (hdlc->do_bitreverse == 0)
*dst++ = bitrev8(hdlc->cbin);
else
*dst++ = hdlc->cbin;
hdlc->data_bits = 0;
len++;
dsize--;
@ -596,8 +627,4 @@ int isdnhdlc_encode(struct isdnhdlc_vars *hdlc, const unsigned char *src,
return len;
}
EXPORT_SYMBOL(isdnhdlc_rcv_init);
EXPORT_SYMBOL(isdnhdlc_decode);
EXPORT_SYMBOL(isdnhdlc_out_init);
EXPORT_SYMBOL(isdnhdlc_encode);

15
drivers/isdn/mISDN/hwchannel.c
View File

@ -114,13 +114,14 @@ mISDN_freedchannel(struct dchannel *ch)
}
EXPORT_SYMBOL(mISDN_freedchannel);
int
mISDN_freebchannel(struct bchannel *ch)
void
mISDN_clear_bchannel(struct bchannel *ch)
{
if (ch->tx_skb) {
dev_kfree_skb(ch->tx_skb);
ch->tx_skb = NULL;
}
ch->tx_idx = 0;
if (ch->rx_skb) {
dev_kfree_skb(ch->rx_skb);
ch->rx_skb = NULL;
@ -129,6 +130,16 @@ mISDN_freebchannel(struct bchannel *ch)
dev_kfree_skb(ch->next_skb);
ch->next_skb = NULL;
}
test_and_clear_bit(FLG_TX_BUSY, &ch->Flags);
test_and_clear_bit(FLG_TX_NEXT, &ch->Flags);
test_and_clear_bit(FLG_ACTIVE, &ch->Flags);
}
EXPORT_SYMBOL(mISDN_clear_bchannel);
int
mISDN_freebchannel(struct bchannel *ch)
{
mISDN_clear_bchannel(ch);
skb_queue_purge(&ch->rqueue);
ch->rcount = 0;
flush_scheduled_work();

2
drivers/isdn/mISDN/layer2.c
View File

@ -1832,8 +1832,6 @@ static struct FsmNode L2FnList[] =
{ST_L2_8, EV_L1_DEACTIVATE, l2_persistant_da},
};
#define L2_FN_COUNT (sizeof(L2FnList)/sizeof(struct FsmNode))
static int
ph_data_indication(struct layer2 *l2, struct mISDNhead *hh, struct sk_buff *skb)
{

82
include/linux/isdn/hdlc.h Normal file
View File

@ -0,0 +1,82 @@
/*
* hdlc.h -- General purpose ISDN HDLC decoder.
*
* Implementation of a HDLC decoder/encoder in software.
* Neccessary because some ISDN devices don't have HDLC
* controllers.
*
* Copyright (C)
* 2009 Karsten Keil <keil@b1-systems.de>
* 2002 Wolfgang Mües <wolfgang@iksw-muees.de>
* 2001 Frode Isaksen <fisaksen@bewan.com>
* 2001 Kai Germaschewski <kai.germaschewski@gmx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ISDNHDLC_H__
#define __ISDNHDLC_H__
struct isdnhdlc_vars {
int bit_shift;
int hdlc_bits1;
int data_bits;
int ffbit_shift; /* encoding only */
int state;
int dstpos;
u16 crc;
u8 cbin;
u8 shift_reg;
u8 ffvalue;
/* set if transferring data */
u32 data_received:1;
/* set if D channel (send idle instead of flags) */
u32 dchannel:1;
/* set if 56K adaptation */
u32 do_adapt56:1;
/* set if in closing phase (need to send CRC + flag) */
u32 do_closing:1;
/* set if data is bitreverse */
u32 do_bitreverse:1;
};
/* Feature Flags */
#define HDLC_56KBIT 0x01
#define HDLC_DCHANNEL 0x02
#define HDLC_BITREVERSE 0x04
/*
The return value from isdnhdlc_decode is
the frame length, 0 if no complete frame was decoded,
or a negative error number
*/
#define HDLC_FRAMING_ERROR 1
#define HDLC_CRC_ERROR 2
#define HDLC_LENGTH_ERROR 3
extern void isdnhdlc_rcv_init(struct isdnhdlc_vars *hdlc, u32 features);
extern int isdnhdlc_decode(struct isdnhdlc_vars *hdlc, const u8 *src,
int slen, int *count, u8 *dst, int dsize);
extern void isdnhdlc_out_init(struct isdnhdlc_vars *hdlc, u32 features);
extern int isdnhdlc_encode(struct isdnhdlc_vars *hdlc, const u8 *src,
u16 slen, int *count, u8 *dst, int dsize);
#endif /* __ISDNHDLC_H__ */

1
include/linux/mISDNhw.h
View File

@ -168,6 +168,7 @@ struct bchannel {
extern int mISDN_initdchannel(struct dchannel *, int, void *);
extern int mISDN_initbchannel(struct bchannel *, int);
extern int mISDN_freedchannel(struct dchannel *);
extern void mISDN_clear_bchannel(struct bchannel *);
extern int mISDN_freebchannel(struct bchannel *);
extern void queue_ch_frame(struct mISDNchannel *, u_int,
int, struct sk_buff *);

16
include/linux/mISDNif.h
View File

@ -37,7 +37,7 @@
*/
#define MISDN_MAJOR_VERSION 1
#define MISDN_MINOR_VERSION 1
#define MISDN_RELEASE 20
#define MISDN_RELEASE 21
/* primitives for information exchange
* generell format
@ -153,6 +153,18 @@
#define HFC_VOL_CHANGE_RX 0x2602
#define HFC_SPL_LOOP_ON 0x2603
#define HFC_SPL_LOOP_OFF 0x2604
/* for T30 FAX and analog modem */
#define HW_MOD_FRM 0x4000
#define HW_MOD_FRH 0x4001
#define HW_MOD_FTM 0x4002
#define HW_MOD_FTH 0x4003
#define HW_MOD_FTS 0x4004
#define HW_MOD_CONNECT 0x4010
#define HW_MOD_OK 0x4011
#define HW_MOD_NOCARR 0x4012
#define HW_MOD_FCERROR 0x4013
#define HW_MOD_READY 0x4014
#define HW_MOD_LASTDATA 0x4015
/* DSP_TONE_PATT_ON parameter */
#define TONE_OFF 0x0000
@ -224,6 +236,8 @@
#define ISDN_P_B_L2DTMF 0x24
#define ISDN_P_B_L2DSP 0x25
#define ISDN_P_B_L2DSPHDLC 0x26
#define ISDN_P_B_T30_FAX 0x27
#define ISDN_P_B_MODEM_ASYNC 0x28
#define OPTION_L2_PMX 1
#define OPTION_L2_PTP 2