forked from luck/tmp_suning_uos_patched
ARM: ARMv7-M: Allow the building of new kernel port
This patch modifies the required Kconfig and Makefile files to allow the building of kernel for Cortex-M3. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Jonathan Austin <jonathan.austin@arm.com> Tested-by: Jonathan Austin <jonathan.austin@arm.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
This commit is contained in:
Uwe Kleine-König
parent
19c4d593f0
commit
4477ca45fb
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@ -9,7 +9,7 @@ config ARM
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select BUILDTIME_EXTABLE_SORT if MMU
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select CPU_PM if (SUSPEND || CPU_IDLE)
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select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
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select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
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select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
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select GENERIC_CLOCKEVENTS_BROADCAST if SMP
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select GENERIC_IRQ_PROBE
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select GENERIC_IRQ_SHOW
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@ -1685,7 +1685,7 @@ config SCHED_HRTICK
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config THUMB2_KERNEL
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bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
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depends on CPU_V7 && !CPU_V6 && !CPU_V6K
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depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
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default y if CPU_THUMBONLY
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select AEABI
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select ARM_ASM_UNIFIED
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@ -28,7 +28,7 @@ config FLASH_SIZE
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config PROCESSOR_ID
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hex 'Hard wire the processor ID'
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default 0x00007700
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depends on !CPU_CP15
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depends on !(CPU_CP15 || CPU_V7M)
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help
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If processor has no CP15 register, this processor ID is
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used instead of the auto-probing which utilizes the register.
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@ -59,6 +59,7 @@ comma = ,
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# Note that GCC does not numerically define an architecture version
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# macro, but instead defines a whole series of macros which makes
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# testing for a specific architecture or later rather impossible.
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arch-$(CONFIG_CPU_32v7M) :=-D__LINUX_ARM_ARCH__=7 -march=armv7-m -Wa,-march=armv7-m
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arch-$(CONFIG_CPU_32v7) :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
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arch-$(CONFIG_CPU_32v6) :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
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# Only override the compiler option if ARMv6. The ARMv6K extensions are
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@ -15,7 +15,7 @@ CFLAGS_REMOVE_return_address.o = -pg
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# Object file lists.
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obj-y := elf.o entry-armv.o entry-common.o irq.o opcodes.o \
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obj-y := elf.o entry-common.o irq.o opcodes.o \
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process.o ptrace.o return_address.o sched_clock.o \
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setup.o signal.o stacktrace.o sys_arm.o time.o traps.o
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@ -23,6 +23,12 @@ obj-$(CONFIG_ATAGS) += atags_parse.o
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obj-$(CONFIG_ATAGS_PROC) += atags_proc.o
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obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += atags_compat.o
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ifeq ($(CONFIG_CPU_V7M),y)
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obj-y += entry-v7m.o
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else
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obj-y += entry-armv.o
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endif
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obj-$(CONFIG_OC_ETM) += etm.o
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obj-$(CONFIG_CPU_IDLE) += cpuidle.o
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obj-$(CONFIG_ISA_DMA_API) += dma.o
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@ -397,6 +397,15 @@ config CPU_V7
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select CPU_PABRT_V7
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select CPU_TLB_V7 if MMU
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# ARMv7M
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config CPU_V7M
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bool
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select CPU_32v7M
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select CPU_ABRT_NOMMU
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select CPU_CACHE_NOP
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select CPU_PABRT_LEGACY
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select CPU_THUMBONLY
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config CPU_THUMBONLY
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bool
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# There are no CPUs available with MMU that don't implement an ARM ISA:
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@ -441,6 +450,9 @@ config CPU_32v6K
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config CPU_32v7
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bool
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config CPU_32v7M
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bool
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# The abort model
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config CPU_ABRT_NOMMU
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bool
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@ -494,6 +506,9 @@ config CPU_CACHE_V6
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config CPU_CACHE_V7
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bool
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config CPU_CACHE_NOP
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bool
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config CPU_CACHE_VIVT
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bool
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@ -616,7 +631,11 @@ config ARCH_DMA_ADDR_T_64BIT
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config ARM_THUMB
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bool "Support Thumb user binaries" if !CPU_THUMBONLY
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depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON
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depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || \
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CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || \
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CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
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CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || \
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CPU_V7 || CPU_FEROCEON || CPU_V7M
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default y
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help
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Say Y if you want to include kernel support for running user space
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@ -40,6 +40,7 @@ obj-$(CONFIG_CPU_CACHE_V4WB) += cache-v4wb.o
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obj-$(CONFIG_CPU_CACHE_V6) += cache-v6.o
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obj-$(CONFIG_CPU_CACHE_V7) += cache-v7.o
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obj-$(CONFIG_CPU_CACHE_FA) += cache-fa.o
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obj-$(CONFIG_CPU_CACHE_NOP) += cache-nop.o
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AFLAGS_cache-v6.o :=-Wa,-march=armv6
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AFLAGS_cache-v7.o :=-Wa,-march=armv7-a
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@ -88,6 +89,7 @@ obj-$(CONFIG_CPU_FEROCEON) += proc-feroceon.o
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obj-$(CONFIG_CPU_V6) += proc-v6.o
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obj-$(CONFIG_CPU_V6K) += proc-v6.o
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obj-$(CONFIG_CPU_V7) += proc-v7.o
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obj-$(CONFIG_CPU_V7M) += proc-v7m.o
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AFLAGS_proc-v6.o :=-Wa,-march=armv6
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AFLAGS_proc-v7.o :=-Wa,-march=armv7-a
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