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clk: samsung: exynos5433: Add clocks for CMU_HEVC domain

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This patch adds the mux/divider/gate clocks for CMU_HEVC domain which
generates the clocks for HEVC(High Efficiency Video Codec) decoder IP.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Chanwoo Choi 2015-02-03 09:13:53 +09:00 committed by Sylwester Nawrocki
parent 9910b6bbaa
commit 45e58aa5f7
3 changed files with 156 additions and 1 deletions
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15
Documentation/devicetree/bindings/clock/exynos5433-clock.txt
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@ -41,6 +41,8 @@ Required Properties:
which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs.
- "samsung,exynos5433-cmu-mfc" - clock controller compatible for CMU_MFC
which generates clocks for MFC(Multi-Format Codec) IP.
- "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC
which generates clocks for HEVC(High Efficiency Video Codec) decoder IP.
- reg: physical base address of the controller and length of memory mapped
region.
@ -131,6 +133,10 @@ Required Properties:
- oscclk
- aclk_mfc_400
Input clocks for hevc clock controller:
- oscclk
- aclk_hevc_400
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume.
@ -355,6 +361,15 @@ Example 2: Examples of clock controller nodes are listed below.
clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
};
cmu_hevc: clock-controller@14f80000 {
compatible = "samsung,exynos5433-cmu-hevc";
reg = <0x14f80000 0x0b08>;
#clock-cells = <1>;
clock-names = "oscclk", "aclk_hevc_400";
clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
};
Example 3: UART controller node that consumes the clock generated by the clock
controller.

115
drivers/clk/samsung/clk-exynos5433.c
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@ -560,6 +560,9 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = {
GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",
ENABLE_ACLK_TOP, 14,
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400",
ENABLE_ACLK_TOP, 5,
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400",
ENABLE_ACLK_TOP, 3,
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
@ -4103,3 +4106,115 @@ static void __init exynos5433_cmu_mfc_init(struct device_node *np)
}
CLK_OF_DECLARE(exynos5433_cmu_mfc, "samsung,exynos5433-cmu-mfc",
exynos5433_cmu_mfc_init);
/*
* Register offset definitions for CMU_HEVC
*/
#define MUX_SEL_HEVC 0x0200
#define MUX_ENABLE_HEVC 0x0300
#define MUX_STAT_HEVC 0x0400
#define DIV_HEVC 0x0600
#define DIV_STAT_HEVC 0x0700
#define ENABLE_ACLK_HEVC 0x0800
#define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC 0x0804
#define ENABLE_PCLK_HEVC 0x0900
#define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC 0x0904
#define ENABLE_IP_HEVC0 0x0b00
#define ENABLE_IP_HEVC1 0x0b04
#define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08
static unsigned long hevc_clk_regs[] __initdata = {
MUX_SEL_HEVC,
MUX_ENABLE_HEVC,
MUX_STAT_HEVC,
DIV_HEVC,
DIV_STAT_HEVC,
ENABLE_ACLK_HEVC,
ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
ENABLE_PCLK_HEVC,
ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
ENABLE_IP_HEVC0,
ENABLE_IP_HEVC1,
ENABLE_IP_HEVC_SECURE_SMMU_HEVC,
};
PNAME(mout_aclk_hevc_400_user_p) = { "oscclk", "aclk_hevc_400", };
static struct samsung_mux_clock hevc_mux_clks[] __initdata = {
/* MUX_SEL_HEVC */
MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user",
mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0),
};
static struct samsung_div_clock hevc_div_clks[] __initdata = {
/* DIV_HEVC */
DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user",
DIV_HEVC, 0, 2),
};
static struct samsung_gate_clock hevc_gate_clks[] __initdata = {
/* ENABLE_ACLK_HEVC */
GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user",
ENABLE_ACLK_HEVC, 6, 0, 0),
GATE(CLK_ACLK_BTS_HEVC_0, "aclk_bts_hevc_0", "mout_aclk_hevc_400_user",
ENABLE_ACLK_HEVC, 5, 0, 0),
GATE(CLK_ACLK_AHB2APB_HEVCP, "aclk_ahb2apb_hevcp", "div_pclk_hevc",
ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_XIU_HEVCX, "aclk_xiu_hevcx", "mout_aclk_hevc_400_user",
ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_HEVCNP_100, "aclk_hevcnp_100", "div_pclk_hevc",
ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_HEVCND_400, "aclk_hevcnd_400", "mout_aclk_hevc_400_user",
ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_HEVC, "aclk_hevc", "mout_aclk_hevc_400_user",
ENABLE_ACLK_HEVC, 0, 0, 0),
/* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */
GATE(CLK_ACLK_SMMU_HEVC_1, "aclk_smmu_hevc_1",
"mout_aclk_hevc_400_user",
ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_SMMU_HEVC_0, "aclk_smmu_hevc_0",
"mout_aclk_hevc_400_user",
ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_HEVC */
GATE(CLK_PCLK_BTS_HEVC_1, "pclk_bts_hevc_1", "div_pclk_hevc",
ENABLE_PCLK_HEVC, 4, 0, 0),
GATE(CLK_PCLK_BTS_HEVC_0, "pclk_bts_hevc_0", "div_pclk_hevc",
ENABLE_PCLK_HEVC, 3, 0, 0),
GATE(CLK_PCLK_PMU_HEVC, "pclk_pmu_hevc", "div_pclk_hevc",
ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SYSREG_HEVC, "pclk_sysreg_hevc", "div_pclk_hevc",
ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_HEVC, "pclk_hevc", "div_pclk_hevc",
ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */
GATE(CLK_PCLK_SMMU_HEVC_1, "pclk_smmu_hevc_1", "div_pclk_hevc",
ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SMMU_HEVC_0, "pclk_smmu_hevc_0", "div_pclk_hevc",
ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
0, CLK_IGNORE_UNUSED, 0),
};
static struct samsung_cmu_info hevc_cmu_info __initdata = {
.mux_clks = hevc_mux_clks,
.nr_mux_clks = ARRAY_SIZE(hevc_mux_clks),
.div_clks = hevc_div_clks,
.nr_div_clks = ARRAY_SIZE(hevc_div_clks),
.gate_clks = hevc_gate_clks,
.nr_gate_clks = ARRAY_SIZE(hevc_gate_clks),
.nr_clk_ids = HEVC_NR_CLK,
.clk_regs = hevc_clk_regs,
.nr_clk_regs = ARRAY_SIZE(hevc_clk_regs),
};
static void __init exynos5433_cmu_hevc_init(struct device_node *np)
{
samsung_cmu_register_one(np, &hevc_cmu_info);
}
CLK_OF_DECLARE(exynos5433_cmu_hevc, "samsung,exynos5433-cmu-hevc",
exynos5433_cmu_hevc_init);

27
include/dt-bindings/clock/exynos5433.h
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@ -154,8 +154,9 @@
#define CLK_SCLK_JPEG_MSCL 234
#define CLK_ACLK_MSCL_400 235
#define CLK_ACLK_MFC_400 236
#define CLK_ACLK_HEVC_400 237
#define TOP_NR_CLK 237
#define TOP_NR_CLK 238
/* CMU_CPIF */
#define CLK_FOUT_MPHY_PLL 1
@ -1001,4 +1002,28 @@
#define MFC_NR_CLK 19
/* CMU_HEVC */
#define CLK_MOUT_ACLK_HEVC_400_USER 1
#define CLK_DIV_PCLK_HEVC 2
#define CLK_ACLK_BTS_HEVC_1 3
#define CLK_ACLK_BTS_HEVC_0 4
#define CLK_ACLK_AHB2APB_HEVCP 5
#define CLK_ACLK_XIU_HEVCX 6
#define CLK_ACLK_HEVCNP_100 7
#define CLK_ACLK_HEVCND_400 8
#define CLK_ACLK_HEVC 9
#define CLK_ACLK_SMMU_HEVC_1 10
#define CLK_ACLK_SMMU_HEVC_0 11
#define CLK_PCLK_BTS_HEVC_1 12
#define CLK_PCLK_BTS_HEVC_0 13
#define CLK_PCLK_PMU_HEVC 14
#define CLK_PCLK_SYSREG_HEVC 15
#define CLK_PCLK_HEVC 16
#define CLK_PCLK_SMMU_HEVC_1 17
#define CLK_PCLK_SMMU_HEVC_0 18
#define HEVC_NR_CLK 19
#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */