forked from luck/tmp_suning_uos_patched
[PATCH] ahci: add softreset
Now that libata is smart enought to handle both soft and hard resets, add softreset method. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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@ -513,6 +513,138 @@ static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, u32 opts)
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pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
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}
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static int ahci_poll_register(void __iomem *reg, u32 mask, u32 val,
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unsigned long interval_msec,
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unsigned long timeout_msec)
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{
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unsigned long timeout;
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u32 tmp;
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timeout = jiffies + (timeout_msec * HZ) / 1000;
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do {
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tmp = readl(reg);
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if ((tmp & mask) == val)
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return 0;
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msleep(interval_msec);
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} while (time_before(jiffies, timeout));
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return -1;
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}
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static int ahci_softreset(struct ata_port *ap, int verbose, unsigned int *class)
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{
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struct ahci_host_priv *hpriv = ap->host_set->private_data;
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struct ahci_port_priv *pp = ap->private_data;
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void __iomem *mmio = ap->host_set->mmio_base;
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void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
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const u32 cmd_fis_len = 5; /* five dwords */
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const char *reason = NULL;
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struct ata_taskfile tf;
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u8 *fis;
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int rc;
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DPRINTK("ENTER\n");
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/* prepare for SRST (AHCI-1.1 10.4.1) */
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rc = ahci_stop_engine(ap);
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if (rc) {
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reason = "failed to stop engine";
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goto fail_restart;
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}
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/* check BUSY/DRQ, perform Command List Override if necessary */
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ahci_tf_read(ap, &tf);
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if (tf.command & (ATA_BUSY | ATA_DRQ)) {
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u32 tmp;
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if (!(hpriv->cap & HOST_CAP_CLO)) {
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rc = -EIO;
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reason = "port busy but no CLO";
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goto fail_restart;
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}
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tmp = readl(port_mmio + PORT_CMD);
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tmp |= PORT_CMD_CLO;
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writel(tmp, port_mmio + PORT_CMD);
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readl(port_mmio + PORT_CMD); /* flush */
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if (ahci_poll_register(port_mmio + PORT_CMD, PORT_CMD_CLO, 0x0,
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1, 500)) {
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rc = -EIO;
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reason = "CLO failed";
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goto fail_restart;
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}
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}
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/* restart engine */
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ahci_start_engine(ap);
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ata_tf_init(ap, &tf, 0);
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fis = pp->cmd_tbl;
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/* issue the first D2H Register FIS */
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ahci_fill_cmd_slot(pp, cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
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tf.ctl |= ATA_SRST;
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ata_tf_to_fis(&tf, fis, 0);
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fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
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writel(1, port_mmio + PORT_CMD_ISSUE);
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readl(port_mmio + PORT_CMD_ISSUE); /* flush */
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if (ahci_poll_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x0, 1, 500)) {
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rc = -EIO;
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reason = "1st FIS failed";
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goto fail;
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}
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/* spec says at least 5us, but be generous and sleep for 1ms */
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msleep(1);
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/* issue the second D2H Register FIS */
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ahci_fill_cmd_slot(pp, cmd_fis_len);
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tf.ctl &= ~ATA_SRST;
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ata_tf_to_fis(&tf, fis, 0);
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fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
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writel(1, port_mmio + PORT_CMD_ISSUE);
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readl(port_mmio + PORT_CMD_ISSUE); /* flush */
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/* spec mandates ">= 2ms" before checking status.
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* We wait 150ms, because that was the magic delay used for
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* ATAPI devices in Hale Landis's ATADRVR, for the period of time
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* between when the ATA command register is written, and then
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* status is checked. Because waiting for "a while" before
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* checking status is fine, post SRST, we perform this magic
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* delay here as well.
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*/
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msleep(150);
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*class = ATA_DEV_NONE;
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if (sata_dev_present(ap)) {
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if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
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rc = -EIO;
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reason = "device not ready";
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goto fail;
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}
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*class = ahci_dev_classify(ap);
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}
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DPRINTK("EXIT, class=%u\n", *class);
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return 0;
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fail_restart:
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ahci_start_engine(ap);
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fail:
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if (verbose)
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printk(KERN_ERR "ata%u: softreset failed (%s)\n",
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ap->id, reason);
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else
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DPRINTK("EXIT, rc=%d reason=\"%s\"\n", rc, reason);
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return rc;
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}
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static int ahci_hardreset(struct ata_port *ap, int verbose, unsigned int *class)
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{
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int rc;
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@ -553,7 +685,8 @@ static void ahci_postreset(struct ata_port *ap, unsigned int *class)
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static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes)
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{
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return ata_drive_probe_reset(ap, NULL, NULL, ahci_hardreset,
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return ata_drive_probe_reset(ap, ata_std_probeinit,
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ahci_softreset, ahci_hardreset,
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ahci_postreset, classes);
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}
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