forked from luck/tmp_suning_uos_patched
clk: add lpc18xx ccu clk driver
Add driver for NXP LPC18xx/43xx Clock Control Unit (CCU). The CCU provides fine grained gating of most clocks present in the SoC. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
This commit is contained in:
Joachim Eastwood
Michael Turquette
parent
668c45df36
commit
472cd304a3
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@ -1 +1,2 @@
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obj-$(CONFIG_ARCH_LPC18XX) += clk-lpc18xx-cgu.o
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obj-$(CONFIG_ARCH_LPC18XX) += clk-lpc18xx-ccu.o
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293
drivers/clk/nxp/clk-lpc18xx-ccu.c
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293
drivers/clk/nxp/clk-lpc18xx-ccu.c
Normal file
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@ -0,0 +1,293 @@
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/*
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* Clk driver for NXP LPC18xx/LPC43xx Clock Control Unit (CCU)
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*
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* Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <dt-bindings/clock/lpc18xx-ccu.h>
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/* Bit defines for CCU branch configuration register */
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#define LPC18XX_CCU_RUN BIT(0)
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#define LPC18XX_CCU_AUTO BIT(1)
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#define LPC18XX_CCU_DIV BIT(5)
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#define LPC18XX_CCU_DIVSTAT BIT(27)
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/* CCU branch feature bits */
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#define CCU_BRANCH_IS_BUS BIT(0)
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#define CCU_BRANCH_HAVE_DIV2 BIT(1)
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#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
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struct lpc18xx_branch_clk_data {
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const char **name;
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int num;
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};
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struct lpc18xx_clk_branch {
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const char *base_name;
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const char *name;
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u16 offset;
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u16 flags;
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struct clk *clk;
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struct clk_gate gate;
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};
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static struct lpc18xx_clk_branch clk_branches[] = {
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{"base_apb3_clk", "apb3_bus", CLK_APB3_BUS, CCU_BRANCH_IS_BUS},
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{"base_apb3_clk", "apb3_i2c1", CLK_APB3_I2C1, 0},
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{"base_apb3_clk", "apb3_dac", CLK_APB3_DAC, 0},
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{"base_apb3_clk", "apb3_adc0", CLK_APB3_ADC0, 0},
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{"base_apb3_clk", "apb3_adc1", CLK_APB3_ADC1, 0},
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{"base_apb3_clk", "apb3_can0", CLK_APB3_CAN0, 0},
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{"base_apb1_clk", "apb1_bus", CLK_APB1_BUS, CCU_BRANCH_IS_BUS},
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{"base_apb1_clk", "apb1_mc_pwm", CLK_APB1_MOTOCON_PWM, 0},
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{"base_apb1_clk", "apb1_i2c0", CLK_APB1_I2C0, 0},
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{"base_apb1_clk", "apb1_i2s", CLK_APB1_I2S, 0},
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{"base_apb1_clk", "apb1_can1", CLK_APB1_CAN1, 0},
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{"base_spifi_clk", "spifi", CLK_SPIFI, 0},
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{"base_cpu_clk", "cpu_bus", CLK_CPU_BUS, CCU_BRANCH_IS_BUS},
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{"base_cpu_clk", "cpu_spifi", CLK_CPU_SPIFI, 0},
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{"base_cpu_clk", "cpu_gpio", CLK_CPU_GPIO, 0},
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{"base_cpu_clk", "cpu_lcd", CLK_CPU_LCD, 0},
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{"base_cpu_clk", "cpu_ethernet", CLK_CPU_ETHERNET, 0},
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{"base_cpu_clk", "cpu_usb0", CLK_CPU_USB0, 0},
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{"base_cpu_clk", "cpu_emc", CLK_CPU_EMC, 0},
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{"base_cpu_clk", "cpu_sdio", CLK_CPU_SDIO, 0},
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{"base_cpu_clk", "cpu_dma", CLK_CPU_DMA, 0},
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{"base_cpu_clk", "cpu_core", CLK_CPU_CORE, 0},
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{"base_cpu_clk", "cpu_sct", CLK_CPU_SCT, 0},
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{"base_cpu_clk", "cpu_usb1", CLK_CPU_USB1, 0},
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{"base_cpu_clk", "cpu_emcdiv", CLK_CPU_EMCDIV, CCU_BRANCH_HAVE_DIV2},
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{"base_cpu_clk", "cpu_flasha", CLK_CPU_FLASHA, CCU_BRANCH_HAVE_DIV2},
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{"base_cpu_clk", "cpu_flashb", CLK_CPU_FLASHB, CCU_BRANCH_HAVE_DIV2},
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{"base_cpu_clk", "cpu_m0app", CLK_CPU_M0APP, CCU_BRANCH_HAVE_DIV2},
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{"base_cpu_clk", "cpu_adchs", CLK_CPU_ADCHS, CCU_BRANCH_HAVE_DIV2},
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{"base_cpu_clk", "cpu_eeprom", CLK_CPU_EEPROM, CCU_BRANCH_HAVE_DIV2},
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{"base_cpu_clk", "cpu_wwdt", CLK_CPU_WWDT, 0},
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{"base_cpu_clk", "cpu_uart0", CLK_CPU_UART0, 0},
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{"base_cpu_clk", "cpu_uart1", CLK_CPU_UART1, 0},
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{"base_cpu_clk", "cpu_ssp0", CLK_CPU_SSP0, 0},
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{"base_cpu_clk", "cpu_timer0", CLK_CPU_TIMER0, 0},
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{"base_cpu_clk", "cpu_timer1", CLK_CPU_TIMER1, 0},
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{"base_cpu_clk", "cpu_scu", CLK_CPU_SCU, 0},
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{"base_cpu_clk", "cpu_creg", CLK_CPU_CREG, 0},
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{"base_cpu_clk", "cpu_ritimer", CLK_CPU_RITIMER, 0},
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{"base_cpu_clk", "cpu_uart2", CLK_CPU_UART2, 0},
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{"base_cpu_clk", "cpu_uart3", CLK_CPU_UART3, 0},
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{"base_cpu_clk", "cpu_timer2", CLK_CPU_TIMER2, 0},
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{"base_cpu_clk", "cpu_timer3", CLK_CPU_TIMER3, 0},
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{"base_cpu_clk", "cpu_ssp1", CLK_CPU_SSP1, 0},
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{"base_cpu_clk", "cpu_qei", CLK_CPU_QEI, 0},
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{"base_periph_clk", "periph_bus", CLK_PERIPH_BUS, CCU_BRANCH_IS_BUS},
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{"base_periph_clk", "periph_core", CLK_PERIPH_CORE, 0},
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{"base_periph_clk", "periph_sgpio", CLK_PERIPH_SGPIO, 0},
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{"base_usb0_clk", "usb0", CLK_USB0, 0},
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{"base_usb1_clk", "usb1", CLK_USB1, 0},
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{"base_spi_clk", "spi", CLK_SPI, 0},
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{"base_adchs_clk", "adchs", CLK_ADCHS, 0},
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{"base_audio_clk", "audio", CLK_AUDIO, 0},
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{"base_uart3_clk", "apb2_uart3", CLK_APB2_UART3, 0},
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{"base_uart2_clk", "apb2_uart2", CLK_APB2_UART2, 0},
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{"base_uart1_clk", "apb0_uart1", CLK_APB0_UART1, 0},
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{"base_uart0_clk", "apb0_uart0", CLK_APB0_UART0, 0},
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{"base_ssp1_clk", "apb2_ssp1", CLK_APB2_SSP1, 0},
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{"base_ssp0_clk", "apb0_ssp0", CLK_APB0_SSP0, 0},
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{"base_sdio_clk", "sdio", CLK_SDIO, 0},
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};
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static struct clk *lpc18xx_ccu_branch_clk_get(struct of_phandle_args *clkspec,
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void *data)
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{
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struct lpc18xx_branch_clk_data *clk_data = data;
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unsigned int offset = clkspec->args[0];
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int i, j;
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for (i = 0; i < ARRAY_SIZE(clk_branches); i++) {
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if (clk_branches[i].offset != offset)
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continue;
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for (j = 0; j < clk_data->num; j++) {
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if (!strcmp(clk_branches[i].base_name, clk_data->name[j]))
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return clk_branches[i].clk;
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}
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}
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pr_err("%s: invalid clock offset %d\n", __func__, offset);
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return ERR_PTR(-EINVAL);
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}
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static int lpc18xx_ccu_gate_endisable(struct clk_hw *hw, bool enable)
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{
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struct clk_gate *gate = to_clk_gate(hw);
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u32 val;
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/*
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* Divider field is write only, so divider stat field must
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* be read so divider field can be set accordingly.
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*/
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val = clk_readl(gate->reg);
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if (val & LPC18XX_CCU_DIVSTAT)
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val |= LPC18XX_CCU_DIV;
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if (enable) {
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val |= LPC18XX_CCU_RUN;
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} else {
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/*
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* To safely disable a branch clock a squence of two separate
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* writes must be used. First write should set the AUTO bit
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* and the next write should clear the RUN bit.
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*/
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val |= LPC18XX_CCU_AUTO;
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clk_writel(val, gate->reg);
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val &= ~LPC18XX_CCU_RUN;
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}
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clk_writel(val, gate->reg);
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return 0;
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}
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static int lpc18xx_ccu_gate_enable(struct clk_hw *hw)
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{
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return lpc18xx_ccu_gate_endisable(hw, true);
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}
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static void lpc18xx_ccu_gate_disable(struct clk_hw *hw)
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{
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lpc18xx_ccu_gate_endisable(hw, false);
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}
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static int lpc18xx_ccu_gate_is_enabled(struct clk_hw *hw)
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{
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struct clk_gate *gate = to_clk_gate(hw);
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return clk_readl(gate->reg) & LPC18XX_CCU_RUN;
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}
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static const struct clk_ops lpc18xx_ccu_gate_ops = {
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.enable = lpc18xx_ccu_gate_enable,
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.disable = lpc18xx_ccu_gate_disable,
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.is_enabled = lpc18xx_ccu_gate_is_enabled,
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};
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static void lpc18xx_ccu_register_branch_gate_div(struct lpc18xx_clk_branch *branch,
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void __iomem *reg_base,
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const char *parent)
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{
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const struct clk_ops *div_ops = NULL;
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struct clk_divider *div = NULL;
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struct clk_hw *div_hw = NULL;
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if (branch->flags & CCU_BRANCH_HAVE_DIV2) {
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div = kzalloc(sizeof(*div), GFP_KERNEL);
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if (!div)
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return;
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div->reg = branch->offset + reg_base;
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div->flags = CLK_DIVIDER_READ_ONLY;
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div->shift = 27;
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div->width = 1;
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div_hw = &div->hw;
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div_ops = &clk_divider_ops;
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}
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branch->gate.reg = branch->offset + reg_base;
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branch->gate.bit_idx = 0;
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branch->clk = clk_register_composite(NULL, branch->name, &parent, 1,
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NULL, NULL,
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div_hw, div_ops,
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&branch->gate.hw, &lpc18xx_ccu_gate_ops, 0);
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if (IS_ERR(branch->clk)) {
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kfree(div);
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pr_warn("%s: failed to register %s\n", __func__, branch->name);
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return;
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}
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/* Grab essential branch clocks for CPU and SDRAM */
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switch (branch->offset) {
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case CLK_CPU_EMC:
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case CLK_CPU_CORE:
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case CLK_CPU_CREG:
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case CLK_CPU_EMCDIV:
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clk_prepare_enable(branch->clk);
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}
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}
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static void lpc18xx_ccu_register_branch_clks(void __iomem *reg_base,
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const char *base_name)
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{
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const char *parent = base_name;
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int i;
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for (i = 0; i < ARRAY_SIZE(clk_branches); i++) {
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if (strcmp(clk_branches[i].base_name, base_name))
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continue;
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lpc18xx_ccu_register_branch_gate_div(&clk_branches[i], reg_base,
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parent);
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if (clk_branches[i].flags & CCU_BRANCH_IS_BUS)
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parent = clk_branches[i].name;
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}
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}
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static void __init lpc18xx_ccu_init(struct device_node *np)
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{
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struct lpc18xx_branch_clk_data *clk_data;
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void __iomem *reg_base;
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int i, ret;
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reg_base = of_iomap(np, 0);
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if (!reg_base) {
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pr_warn("%s: failed to map address range\n", __func__);
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return;
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}
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clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
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if (!clk_data)
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return;
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clk_data->num = of_property_count_strings(np, "clock-names");
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clk_data->name = kcalloc(clk_data->num, sizeof(char *), GFP_KERNEL);
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if (!clk_data->name) {
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kfree(clk_data);
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return;
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}
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for (i = 0; i < clk_data->num; i++) {
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ret = of_property_read_string_index(np, "clock-names", i,
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&clk_data->name[i]);
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if (ret) {
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pr_warn("%s: failed to get clock name at idx %d\n",
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__func__, i);
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continue;
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}
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lpc18xx_ccu_register_branch_clks(reg_base, clk_data->name[i]);
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}
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of_clk_add_provider(np, lpc18xx_ccu_branch_clk_get, clk_data);
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}
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CLK_OF_DECLARE(lpc18xx_ccu, "nxp,lpc1850-ccu", lpc18xx_ccu_init);
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74
include/dt-bindings/clock/lpc18xx-ccu.h
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74
include/dt-bindings/clock/lpc18xx-ccu.h
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@ -0,0 +1,74 @@
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/*
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* Copyright (c) 2015 Joachim Eastwood <manabian@gmail.com>
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*
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* This code is released using a dual license strategy: BSD/GPL
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* You can choose the licence that better fits your requirements.
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*
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* Released under the terms of 3-clause BSD License
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* Released under the terms of GNU General Public License Version 2.0
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*
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*/
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/* Clock Control Unit 1 (CCU1) clock offsets */
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#define CLK_APB3_BUS 0x100
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#define CLK_APB3_I2C1 0x108
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#define CLK_APB3_DAC 0x110
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#define CLK_APB3_ADC0 0x118
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#define CLK_APB3_ADC1 0x120
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#define CLK_APB3_CAN0 0x128
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#define CLK_APB1_BUS 0x200
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#define CLK_APB1_MOTOCON_PWM 0x208
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#define CLK_APB1_I2C0 0x210
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#define CLK_APB1_I2S 0x218
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#define CLK_APB1_CAN1 0x220
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#define CLK_SPIFI 0x300
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#define CLK_CPU_BUS 0x400
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#define CLK_CPU_SPIFI 0x408
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#define CLK_CPU_GPIO 0x410
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#define CLK_CPU_LCD 0x418
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#define CLK_CPU_ETHERNET 0x420
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#define CLK_CPU_USB0 0x428
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#define CLK_CPU_EMC 0x430
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#define CLK_CPU_SDIO 0x438
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#define CLK_CPU_DMA 0x440
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#define CLK_CPU_CORE 0x448
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#define CLK_CPU_SCT 0x468
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#define CLK_CPU_USB1 0x470
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#define CLK_CPU_EMCDIV 0x478
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#define CLK_CPU_FLASHA 0x480
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#define CLK_CPU_FLASHB 0x488
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#define CLK_CPU_M0APP 0x490
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#define CLK_CPU_ADCHS 0x498
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#define CLK_CPU_EEPROM 0x4a0
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#define CLK_CPU_WWDT 0x500
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#define CLK_CPU_UART0 0x508
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#define CLK_CPU_UART1 0x510
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#define CLK_CPU_SSP0 0x518
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#define CLK_CPU_TIMER0 0x520
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#define CLK_CPU_TIMER1 0x528
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#define CLK_CPU_SCU 0x530
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#define CLK_CPU_CREG 0x538
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#define CLK_CPU_RITIMER 0x600
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#define CLK_CPU_UART2 0x608
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#define CLK_CPU_UART3 0x610
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#define CLK_CPU_TIMER2 0x618
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#define CLK_CPU_TIMER3 0x620
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#define CLK_CPU_SSP1 0x628
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#define CLK_CPU_QEI 0x630
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#define CLK_PERIPH_BUS 0x700
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#define CLK_PERIPH_CORE 0x710
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#define CLK_PERIPH_SGPIO 0x718
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#define CLK_USB0 0x800
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#define CLK_USB1 0x900
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#define CLK_SPI 0xA00
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#define CLK_ADCHS 0xB00
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/* Clock Control Unit 2 (CCU2) clock offsets */
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#define CLK_AUDIO 0x100
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#define CLK_APB2_UART3 0x200
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#define CLK_APB2_UART2 0x300
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#define CLK_APB0_UART1 0x400
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#define CLK_APB0_UART0 0x500
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#define CLK_APB2_SSP1 0x600
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#define CLK_APB0_SSP0 0x700
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#define CLK_SDIO 0x800
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