forked from luck/tmp_suning_uos_patched
spi/bfin_spi: use structs for accessing hardware regs
Rather than hardcoding the register sizes/offsets in this file, use the existing struct in the spi header for reading/writing the hardware. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This commit is contained in:
Mike Frysinger
Grant Likely
parent
f8db4cc4f2
commit
47885ce81c
@ -58,7 +58,7 @@ struct bfin_spi_master_data {
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struct spi_master *master;
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/* Regs base of SPI controller */
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void __iomem *regs_base;
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struct bfin_spi_regs __iomem *regs;
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/* Pin request list */
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u16 *pin_req;
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@ -122,34 +122,14 @@ struct bfin_spi_slave_data {
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const struct bfin_spi_transfer_ops *ops;
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};
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#define DEFINE_SPI_REG(reg, off) \
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static inline u16 read_##reg(struct bfin_spi_master_data *drv_data) \
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{ return bfin_read16(drv_data->regs_base + off); } \
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static inline void write_##reg(struct bfin_spi_master_data *drv_data, u16 v) \
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{ bfin_write16(drv_data->regs_base + off, v); }
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DEFINE_SPI_REG(CTRL, 0x00)
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DEFINE_SPI_REG(FLAG, 0x04)
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DEFINE_SPI_REG(STAT, 0x08)
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DEFINE_SPI_REG(TDBR, 0x0C)
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DEFINE_SPI_REG(RDBR, 0x10)
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DEFINE_SPI_REG(BAUD, 0x14)
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DEFINE_SPI_REG(SHAW, 0x18)
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static void bfin_spi_enable(struct bfin_spi_master_data *drv_data)
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{
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u16 cr;
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cr = read_CTRL(drv_data);
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write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
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bfin_write_or(&drv_data->regs->ctl, BIT_CTL_ENABLE);
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}
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static void bfin_spi_disable(struct bfin_spi_master_data *drv_data)
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{
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u16 cr;
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cr = read_CTRL(drv_data);
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write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
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bfin_write_and(&drv_data->regs->ctl, ~BIT_CTL_ENABLE);
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}
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/* Caculate the SPI_BAUD register value based on input HZ */
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@ -172,10 +152,10 @@ static int bfin_spi_flush(struct bfin_spi_master_data *drv_data)
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unsigned long limit = loops_per_jiffy << 1;
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/* wait for stop and clear stat */
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && --limit)
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while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF) && --limit)
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cpu_relax();
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write_STAT(drv_data, BIT_STAT_CLR);
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bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
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return limit;
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}
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@ -183,29 +163,19 @@ static int bfin_spi_flush(struct bfin_spi_master_data *drv_data)
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/* Chip select operation functions for cs_change flag */
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static void bfin_spi_cs_active(struct bfin_spi_master_data *drv_data, struct bfin_spi_slave_data *chip)
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{
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if (likely(chip->chip_select_num < MAX_CTRL_CS)) {
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u16 flag = read_FLAG(drv_data);
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flag &= ~chip->flag;
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write_FLAG(drv_data, flag);
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} else {
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if (likely(chip->chip_select_num < MAX_CTRL_CS))
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bfin_write_and(&drv_data->regs->flg, ~chip->flag);
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else
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gpio_set_value(chip->cs_gpio, 0);
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}
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}
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static void bfin_spi_cs_deactive(struct bfin_spi_master_data *drv_data,
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struct bfin_spi_slave_data *chip)
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{
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if (likely(chip->chip_select_num < MAX_CTRL_CS)) {
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u16 flag = read_FLAG(drv_data);
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flag |= chip->flag;
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write_FLAG(drv_data, flag);
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} else {
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if (likely(chip->chip_select_num < MAX_CTRL_CS))
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bfin_write_or(&drv_data->regs->flg, chip->flag);
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else
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gpio_set_value(chip->cs_gpio, 1);
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}
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/* Move delay here for consistency */
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if (chip->cs_chg_udelay)
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@ -216,25 +186,15 @@ static void bfin_spi_cs_deactive(struct bfin_spi_master_data *drv_data,
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static inline void bfin_spi_cs_enable(struct bfin_spi_master_data *drv_data,
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struct bfin_spi_slave_data *chip)
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{
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if (chip->chip_select_num < MAX_CTRL_CS) {
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u16 flag = read_FLAG(drv_data);
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flag |= (chip->flag >> 8);
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write_FLAG(drv_data, flag);
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}
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if (chip->chip_select_num < MAX_CTRL_CS)
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bfin_write_or(&drv_data->regs->flg, chip->flag >> 8);
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}
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static inline void bfin_spi_cs_disable(struct bfin_spi_master_data *drv_data,
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struct bfin_spi_slave_data *chip)
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{
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if (chip->chip_select_num < MAX_CTRL_CS) {
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u16 flag = read_FLAG(drv_data);
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flag &= ~(chip->flag >> 8);
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write_FLAG(drv_data, flag);
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}
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if (chip->chip_select_num < MAX_CTRL_CS)
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bfin_write_and(&drv_data->regs->flg, ~(chip->flag >> 8));
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}
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/* stop controller and re-config current chip*/
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@ -243,15 +203,15 @@ static void bfin_spi_restore_state(struct bfin_spi_master_data *drv_data)
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struct bfin_spi_slave_data *chip = drv_data->cur_chip;
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/* Clear status and disable clock */
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write_STAT(drv_data, BIT_STAT_CLR);
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bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
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bfin_spi_disable(drv_data);
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dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
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SSYNC();
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/* Load the registers */
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write_CTRL(drv_data, chip->ctl_reg);
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write_BAUD(drv_data, chip->baud);
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bfin_write(&drv_data->regs->ctl, chip->ctl_reg);
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bfin_write(&drv_data->regs->baud, chip->baud);
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bfin_spi_enable(drv_data);
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bfin_spi_cs_active(drv_data, chip);
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@ -260,7 +220,7 @@ static void bfin_spi_restore_state(struct bfin_spi_master_data *drv_data)
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/* used to kick off transfer in rx mode and read unwanted RX data */
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static inline void bfin_spi_dummy_read(struct bfin_spi_master_data *drv_data)
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{
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(void) read_RDBR(drv_data);
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(void) bfin_read(&drv_data->regs->rdbr);
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}
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static void bfin_spi_u8_writer(struct bfin_spi_master_data *drv_data)
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@ -269,10 +229,10 @@ static void bfin_spi_u8_writer(struct bfin_spi_master_data *drv_data)
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bfin_spi_dummy_read(drv_data);
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while (drv_data->tx < drv_data->tx_end) {
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write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
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bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++)));
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/* wait until transfer finished.
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checking SPIF or TXS may not guarantee transfer completion */
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
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cpu_relax();
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/* discard RX data and clear RXS */
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bfin_spi_dummy_read(drv_data);
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@ -287,10 +247,10 @@ static void bfin_spi_u8_reader(struct bfin_spi_master_data *drv_data)
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bfin_spi_dummy_read(drv_data);
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while (drv_data->rx < drv_data->rx_end) {
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write_TDBR(drv_data, tx_val);
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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bfin_write(&drv_data->regs->tdbr, tx_val);
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while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
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cpu_relax();
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*(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
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*(u8 *) (drv_data->rx++) = bfin_read(&drv_data->regs->rdbr);
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}
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}
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@ -300,10 +260,10 @@ static void bfin_spi_u8_duplex(struct bfin_spi_master_data *drv_data)
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bfin_spi_dummy_read(drv_data);
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while (drv_data->rx < drv_data->rx_end) {
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write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++)));
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while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
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cpu_relax();
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*(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
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*(u8 *) (drv_data->rx++) = bfin_read(&drv_data->regs->rdbr);
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}
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}
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@ -319,11 +279,11 @@ static void bfin_spi_u16_writer(struct bfin_spi_master_data *drv_data)
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bfin_spi_dummy_read(drv_data);
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while (drv_data->tx < drv_data->tx_end) {
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write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
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bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx)));
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drv_data->tx += 2;
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/* wait until transfer finished.
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checking SPIF or TXS may not guarantee transfer completion */
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
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cpu_relax();
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/* discard RX data and clear RXS */
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bfin_spi_dummy_read(drv_data);
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@ -338,10 +298,10 @@ static void bfin_spi_u16_reader(struct bfin_spi_master_data *drv_data)
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bfin_spi_dummy_read(drv_data);
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while (drv_data->rx < drv_data->rx_end) {
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write_TDBR(drv_data, tx_val);
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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bfin_write(&drv_data->regs->tdbr, tx_val);
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while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
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cpu_relax();
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*(u16 *) (drv_data->rx) = read_RDBR(drv_data);
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*(u16 *) (drv_data->rx) = bfin_read(&drv_data->regs->rdbr);
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drv_data->rx += 2;
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}
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}
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@ -352,11 +312,11 @@ static void bfin_spi_u16_duplex(struct bfin_spi_master_data *drv_data)
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bfin_spi_dummy_read(drv_data);
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while (drv_data->rx < drv_data->rx_end) {
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write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
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bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx)));
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drv_data->tx += 2;
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
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cpu_relax();
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*(u16 *) (drv_data->rx) = read_RDBR(drv_data);
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*(u16 *) (drv_data->rx) = bfin_read(&drv_data->regs->rdbr);
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drv_data->rx += 2;
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}
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}
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@ -428,7 +388,7 @@ static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
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int loop = 0;
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/* wait until transfer finished. */
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
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cpu_relax();
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if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) ||
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@ -439,11 +399,11 @@ static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
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if (n_bytes % 2) {
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u16 *buf = (u16 *)drv_data->rx;
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for (loop = 0; loop < n_bytes / 2; loop++)
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*buf++ = read_RDBR(drv_data);
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*buf++ = bfin_read(&drv_data->regs->rdbr);
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} else {
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u8 *buf = (u8 *)drv_data->rx;
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for (loop = 0; loop < n_bytes; loop++)
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*buf++ = read_RDBR(drv_data);
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*buf++ = bfin_read(&drv_data->regs->rdbr);
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}
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drv_data->rx += n_bytes;
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}
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@ -468,15 +428,15 @@ static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
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u16 *buf = (u16 *)drv_data->rx;
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u16 *buf2 = (u16 *)drv_data->tx;
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for (loop = 0; loop < n_bytes / 2; loop++) {
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*buf++ = read_RDBR(drv_data);
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write_TDBR(drv_data, *buf2++);
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*buf++ = bfin_read(&drv_data->regs->rdbr);
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bfin_write(&drv_data->regs->tdbr, *buf2++);
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}
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} else {
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u8 *buf = (u8 *)drv_data->rx;
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u8 *buf2 = (u8 *)drv_data->tx;
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for (loop = 0; loop < n_bytes; loop++) {
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*buf++ = read_RDBR(drv_data);
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write_TDBR(drv_data, *buf2++);
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*buf++ = bfin_read(&drv_data->regs->rdbr);
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bfin_write(&drv_data->regs->tdbr, *buf2++);
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}
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}
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} else if (drv_data->rx) {
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@ -485,14 +445,14 @@ static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
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if (n_bytes % 2) {
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u16 *buf = (u16 *)drv_data->rx;
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for (loop = 0; loop < n_bytes / 2; loop++) {
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*buf++ = read_RDBR(drv_data);
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write_TDBR(drv_data, chip->idle_tx_val);
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*buf++ = bfin_read(&drv_data->regs->rdbr);
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bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
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}
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} else {
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u8 *buf = (u8 *)drv_data->rx;
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for (loop = 0; loop < n_bytes; loop++) {
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*buf++ = read_RDBR(drv_data);
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write_TDBR(drv_data, chip->idle_tx_val);
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*buf++ = bfin_read(&drv_data->regs->rdbr);
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bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
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}
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}
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} else if (drv_data->tx) {
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@ -501,14 +461,14 @@ static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
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if (n_bytes % 2) {
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u16 *buf = (u16 *)drv_data->tx;
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for (loop = 0; loop < n_bytes / 2; loop++) {
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read_RDBR(drv_data);
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write_TDBR(drv_data, *buf++);
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bfin_read(&drv_data->regs->rdbr);
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bfin_write(&drv_data->regs->tdbr, *buf++);
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}
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} else {
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u8 *buf = (u8 *)drv_data->tx;
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for (loop = 0; loop < n_bytes; loop++) {
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read_RDBR(drv_data);
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write_TDBR(drv_data, *buf++);
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bfin_read(&drv_data->regs->rdbr);
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bfin_write(&drv_data->regs->tdbr, *buf++);
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}
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}
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}
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@ -528,19 +488,19 @@ static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
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struct spi_message *msg = drv_data->cur_msg;
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unsigned long timeout;
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unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
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u16 spistat = read_STAT(drv_data);
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u16 spistat = bfin_read(&drv_data->regs->stat);
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dev_dbg(&drv_data->pdev->dev,
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"in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
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dmastat, spistat);
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if (drv_data->rx != NULL) {
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u16 cr = read_CTRL(drv_data);
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u16 cr = bfin_read(&drv_data->regs->ctl);
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/* discard old RX data and clear RXS */
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bfin_spi_dummy_read(drv_data);
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write_CTRL(drv_data, cr & ~BIT_CTL_ENABLE); /* Disable SPI */
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write_CTRL(drv_data, cr & ~BIT_CTL_TIMOD); /* Restore State */
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write_STAT(drv_data, BIT_STAT_CLR); /* Clear Status */
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bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_ENABLE); /* Disable SPI */
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bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_TIMOD); /* Restore State */
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bfin_write(&drv_data->regs->stat, BIT_STAT_CLR); /* Clear Status */
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}
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clear_dma_irqstat(drv_data->dma_channel);
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@ -552,17 +512,17 @@ static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
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* register until it goes low for 2 successive reads
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*/
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if (drv_data->tx != NULL) {
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while ((read_STAT(drv_data) & BIT_STAT_TXS) ||
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(read_STAT(drv_data) & BIT_STAT_TXS))
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while ((bfin_read(&drv_data->regs->stat) & BIT_STAT_TXS) ||
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(bfin_read(&drv_data->regs->stat) & BIT_STAT_TXS))
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cpu_relax();
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}
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dev_dbg(&drv_data->pdev->dev,
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"in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
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dmastat, read_STAT(drv_data));
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dmastat, bfin_read(&drv_data->regs->stat));
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timeout = jiffies + HZ;
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
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while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF))
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if (!time_before(jiffies, timeout)) {
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dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF");
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break;
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@ -699,9 +659,9 @@ static void bfin_spi_pump_transfers(unsigned long data)
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bfin_spi_giveback(drv_data);
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return;
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}
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cr = read_CTRL(drv_data) & ~(BIT_CTL_TIMOD | BIT_CTL_WORDSIZE);
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cr = bfin_read(&drv_data->regs->ctl) & ~(BIT_CTL_TIMOD | BIT_CTL_WORDSIZE);
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cr |= cr_width;
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write_CTRL(drv_data, cr);
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bfin_write(&drv_data->regs->ctl, cr);
|
||||
|
||||
dev_dbg(&drv_data->pdev->dev,
|
||||
"transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n",
|
||||
@ -712,11 +672,11 @@ static void bfin_spi_pump_transfers(unsigned long data)
|
||||
|
||||
/* Speed setup (surely valid because already checked) */
|
||||
if (transfer->speed_hz)
|
||||
write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
|
||||
bfin_write(&drv_data->regs->baud, hz_to_spi_baud(transfer->speed_hz));
|
||||
else
|
||||
write_BAUD(drv_data, chip->baud);
|
||||
bfin_write(&drv_data->regs->baud, chip->baud);
|
||||
|
||||
write_STAT(drv_data, BIT_STAT_CLR);
|
||||
bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
|
||||
bfin_spi_cs_active(drv_data, chip);
|
||||
|
||||
dev_dbg(&drv_data->pdev->dev,
|
||||
@ -749,7 +709,7 @@ static void bfin_spi_pump_transfers(unsigned long data)
|
||||
}
|
||||
|
||||
/* poll for SPI completion before start */
|
||||
while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
|
||||
while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF))
|
||||
cpu_relax();
|
||||
|
||||
/* dirty hack for autobuffer DMA mode */
|
||||
@ -766,7 +726,7 @@ static void bfin_spi_pump_transfers(unsigned long data)
|
||||
enable_dma(drv_data->dma_channel);
|
||||
|
||||
/* start SPI transfer */
|
||||
write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX);
|
||||
bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TIMOD_DMA_TX);
|
||||
|
||||
/* just return here, there can only be one transfer
|
||||
* in this mode
|
||||
@ -821,7 +781,7 @@ static void bfin_spi_pump_transfers(unsigned long data)
|
||||
set_dma_config(drv_data->dma_channel, dma_config);
|
||||
local_irq_save(flags);
|
||||
SSYNC();
|
||||
write_CTRL(drv_data, cr);
|
||||
bfin_write(&drv_data->regs->ctl, cr);
|
||||
enable_dma(drv_data->dma_channel);
|
||||
dma_enable_irq(drv_data->dma_channel);
|
||||
local_irq_restore(flags);
|
||||
@ -835,7 +795,7 @@ static void bfin_spi_pump_transfers(unsigned long data)
|
||||
* problems with setting up the output value in TDBR prior to the
|
||||
* start of the transfer.
|
||||
*/
|
||||
write_CTRL(drv_data, cr | BIT_CTL_TXMOD);
|
||||
bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TXMOD);
|
||||
|
||||
if (chip->pio_interrupt) {
|
||||
/* SPI irq should have been disabled by now */
|
||||
@ -845,19 +805,19 @@ static void bfin_spi_pump_transfers(unsigned long data)
|
||||
|
||||
/* start transfer */
|
||||
if (drv_data->tx == NULL)
|
||||
write_TDBR(drv_data, chip->idle_tx_val);
|
||||
bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
|
||||
else {
|
||||
int loop;
|
||||
if (bits_per_word % 16 == 0) {
|
||||
u16 *buf = (u16 *)drv_data->tx;
|
||||
for (loop = 0; loop < bits_per_word / 16;
|
||||
loop++) {
|
||||
write_TDBR(drv_data, *buf++);
|
||||
bfin_write(&drv_data->regs->tdbr, *buf++);
|
||||
}
|
||||
} else if (bits_per_word % 8 == 0) {
|
||||
u8 *buf = (u8 *)drv_data->tx;
|
||||
for (loop = 0; loop < bits_per_word / 8; loop++)
|
||||
write_TDBR(drv_data, *buf++);
|
||||
bfin_write(&drv_data->regs->tdbr, *buf++);
|
||||
}
|
||||
|
||||
drv_data->tx += drv_data->n_bytes;
|
||||
@ -1353,8 +1313,8 @@ static int __init bfin_spi_probe(struct platform_device *pdev)
|
||||
goto out_error_get_res;
|
||||
}
|
||||
|
||||
drv_data->regs_base = ioremap(res->start, resource_size(res));
|
||||
if (drv_data->regs_base == NULL) {
|
||||
drv_data->regs = ioremap(res->start, resource_size(res));
|
||||
if (drv_data->regs == NULL) {
|
||||
dev_err(dev, "Cannot map IO\n");
|
||||
status = -ENXIO;
|
||||
goto out_error_ioremap;
|
||||
@ -1397,8 +1357,8 @@ static int __init bfin_spi_probe(struct platform_device *pdev)
|
||||
/* Reset SPI registers. If these registers were used by the boot loader,
|
||||
* the sky may fall on your head if you enable the dma controller.
|
||||
*/
|
||||
write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER);
|
||||
write_FLAG(drv_data, 0xFF00);
|
||||
bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER);
|
||||
bfin_write(&drv_data->regs->flg, 0xFF00);
|
||||
|
||||
/* Register with the SPI framework */
|
||||
platform_set_drvdata(pdev, drv_data);
|
||||
@ -1408,15 +1368,15 @@ static int __init bfin_spi_probe(struct platform_device *pdev)
|
||||
goto out_error_queue_alloc;
|
||||
}
|
||||
|
||||
dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
|
||||
DRV_DESC, DRV_VERSION, drv_data->regs_base,
|
||||
dev_info(dev, "%s, Version %s, regs@%p, dma channel@%d\n",
|
||||
DRV_DESC, DRV_VERSION, drv_data->regs,
|
||||
drv_data->dma_channel);
|
||||
return status;
|
||||
|
||||
out_error_queue_alloc:
|
||||
bfin_spi_destroy_queue(drv_data);
|
||||
out_error_free_io:
|
||||
iounmap((void *) drv_data->regs_base);
|
||||
iounmap(drv_data->regs);
|
||||
out_error_ioremap:
|
||||
out_error_get_res:
|
||||
spi_master_put(master);
|
||||
@ -1473,14 +1433,14 @@ static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state)
|
||||
if (status != 0)
|
||||
return status;
|
||||
|
||||
drv_data->ctrl_reg = read_CTRL(drv_data);
|
||||
drv_data->flag_reg = read_FLAG(drv_data);
|
||||
drv_data->ctrl_reg = bfin_read(&drv_data->regs->ctl);
|
||||
drv_data->flag_reg = bfin_read(&drv_data->regs->flg);
|
||||
|
||||
/*
|
||||
* reset SPI_CTL and SPI_FLG registers
|
||||
*/
|
||||
write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER);
|
||||
write_FLAG(drv_data, 0xFF00);
|
||||
bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER);
|
||||
bfin_write(&drv_data->regs->flg, 0xFF00);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1490,8 +1450,8 @@ static int bfin_spi_resume(struct platform_device *pdev)
|
||||
struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
|
||||
int status = 0;
|
||||
|
||||
write_CTRL(drv_data, drv_data->ctrl_reg);
|
||||
write_FLAG(drv_data, drv_data->flag_reg);
|
||||
bfin_write(&drv_data->regs->ctl, drv_data->ctrl_reg);
|
||||
bfin_write(&drv_data->regs->flg, drv_data->flag_reg);
|
||||
|
||||
/* Start the queue running */
|
||||
status = bfin_spi_start_queue(drv_data);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user