forked from luck/tmp_suning_uos_patched
arm64: dts: Add msm8998 SoC and MTP board support
Add initial device tree support for the Qualcomm MSM8998 SoC and MTP8998 evaluation board. Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org> Signed-off-by: Imran Khan <kimran@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> [bjorn: Restructured, removed its node and moved to SPDX headers] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit is contained in:
Joonwoo Park
Andy Gross
parent
43fb443168
commit
4807c71cc6
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@ -6,4 +6,5 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
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13
arch/arm64/boot/dts/qcom/msm8998-mtp.dts
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13
arch/arm64/boot/dts/qcom/msm8998-mtp.dts
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@ -0,0 +1,13 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
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/dts-v1/;
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#include "msm8998-mtp.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. MSM8998 v1 MTP";
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compatible = "qcom,msm8998-mtp";
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qcom,board-id = <8 0>;
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};
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18
arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
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18
arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
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@ -0,0 +1,18 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
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#include "msm8998.dtsi"
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/ {
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aliases {
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serial0 = &blsp2_uart1;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&blsp2_uart1 {
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status = "okay";
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};
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346
arch/arm64/boot/dts/qcom/msm8998.dtsi
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346
arch/arm64/boot/dts/qcom/msm8998.dtsi
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@ -0,0 +1,346 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-msm8998.h>
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/ {
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interrupt-parent = <&intc>;
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qcom,msm-id = <292 0x0>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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memory {
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device_type = "memory";
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/* We expect the bootloader to fill in the reg */
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reg = <0 0 0 0>;
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};
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clocks {
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xo_board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <19200000>;
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};
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sleep_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32764>;
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};
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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efficiency = <1024>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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};
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L1_I_0: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_0: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x1>;
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enable-method = "psci";
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efficiency = <1024>;
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next-level-cache = <&L2_0>;
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L1_I_1: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_1: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x2>;
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enable-method = "psci";
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efficiency = <1024>;
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next-level-cache = <&L2_0>;
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L1_I_2: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_2: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x3>;
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enable-method = "psci";
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efficiency = <1024>;
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next-level-cache = <&L2_0>;
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L1_I_3: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_3: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU4: cpu@100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "psci";
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efficiency = <1536>;
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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};
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L1_I_100: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_100: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU5: cpu@101 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x101>;
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enable-method = "psci";
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efficiency = <1536>;
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next-level-cache = <&L2_1>;
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L1_I_101: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_101: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU6: cpu@102 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x102>;
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enable-method = "psci";
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efficiency = <1536>;
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next-level-cache = <&L2_1>;
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L1_I_102: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_102: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU7: cpu@103 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x103>;
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enable-method = "psci";
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efficiency = <1536>;
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next-level-cache = <&L2_1>;
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L1_I_103: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_103: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU4>;
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};
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core1 {
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cpu = <&CPU5>;
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};
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core2 {
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cpu = <&CPU6>;
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};
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core3 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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gcc: clock-controller@100000 {
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compatible = "qcom,gcc-msm8998";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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reg = <0x100000 0xb0000>;
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};
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tlmm: pinctrl@3400000 {
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compatible = "qcom,msm8998-pinctrl";
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reg = <0x3400000 0xc00000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <0x2>;
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interrupt-controller;
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#interrupt-cells = <0x2>;
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};
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spmi_bus: spmi@800f000 {
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compatible = "qcom,spmi-pmic-arb";
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reg = <0x800f000 0x1000>,
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<0x8400000 0x1000000>,
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<0x9400000 0x1000000>,
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<0xa400000 0x220000>,
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<0x800a000 0x3000>;
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reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
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interrupt-names = "periph_irq";
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interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
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qcom,ee = <0>;
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qcom,channel = <0>;
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#address-cells = <2>;
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#size-cells = <0>;
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interrupt-controller;
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#interrupt-cells = <4>;
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cell-index = <0>;
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};
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blsp2_uart1: serial@c1b0000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0xc1b0000 0x1000>;
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interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
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<&gcc GCC_BLSP2_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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timer@17920000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x17920000 0x1000>;
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frame@17921000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17921000 0x1000>,
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<0x17922000 0x1000>;
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};
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frame@17923000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17923000 0x1000>;
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status = "disabled";
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};
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frame@17924000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17924000 0x1000>;
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status = "disabled";
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};
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frame@17925000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17925000 0x1000>;
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status = "disabled";
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};
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frame@17926000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17926000 0x1000>;
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status = "disabled";
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};
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frame@17927000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17927000 0x1000>;
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status = "disabled";
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};
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frame@17928000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17928000 0x1000>;
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status = "disabled";
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};
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};
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intc: interrupt-controller@17a00000 {
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compatible = "arm,gic-v3";
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reg = <0x17a00000 0x10000>, /* GICD */
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<0x17b00000 0x100000>; /* GICR * 8 */
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#interrupt-cells = <3>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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};
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