forked from luck/tmp_suning_uos_patched
dmaengine: altera: remove DMA_SG
Commit c678fa66341c: ("dmaengine: remove DMA_SG as it is dead code in kernel") removes DMA_SG from dmaengine subsystem but missed the newly added driver, so remove it from here as well Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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@ -385,98 +385,6 @@ msgdma_prep_memcpy(struct dma_chan *dchan, dma_addr_t dma_dst,
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return &first->async_tx;
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}
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/**
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* msgdma_prep_sg - prepare descriptors for a memory sg transaction
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* @dchan: DMA channel
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* @dst_sg: Destination scatter list
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* @dst_sg_len: Number of entries in destination scatter list
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* @src_sg: Source scatter list
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* @src_sg_len: Number of entries in source scatter list
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* @flags: transfer ack flags
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*
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* Return: Async transaction descriptor on success and NULL on failure
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*/
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static struct dma_async_tx_descriptor *
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msgdma_prep_sg(struct dma_chan *dchan, struct scatterlist *dst_sg,
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unsigned int dst_sg_len, struct scatterlist *src_sg,
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unsigned int src_sg_len, unsigned long flags)
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{
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struct msgdma_device *mdev = to_mdev(dchan);
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struct msgdma_sw_desc *new, *first = NULL;
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void *desc = NULL;
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size_t len, dst_avail, src_avail;
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dma_addr_t dma_dst, dma_src;
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u32 desc_cnt = 0, i;
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struct scatterlist *sg;
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for_each_sg(src_sg, sg, src_sg_len, i)
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desc_cnt += DIV_ROUND_UP(sg_dma_len(sg), MSGDMA_MAX_TRANS_LEN);
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spin_lock_bh(&mdev->lock);
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if (desc_cnt > mdev->desc_free_cnt) {
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spin_unlock_bh(&mdev->lock);
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dev_dbg(mdev->dev, "mdev %p descs are not available\n", mdev);
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return NULL;
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}
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mdev->desc_free_cnt -= desc_cnt;
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spin_unlock_bh(&mdev->lock);
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dst_avail = sg_dma_len(dst_sg);
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src_avail = sg_dma_len(src_sg);
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/* Run until we are out of scatterlist entries */
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while (true) {
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/* Allocate and populate the descriptor */
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new = msgdma_get_descriptor(mdev);
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desc = &new->hw_desc;
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len = min_t(size_t, src_avail, dst_avail);
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len = min_t(size_t, len, MSGDMA_MAX_TRANS_LEN);
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if (len == 0)
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goto fetch;
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dma_dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) -
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dst_avail;
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dma_src = sg_dma_address(src_sg) + sg_dma_len(src_sg) -
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src_avail;
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msgdma_desc_config(desc, dma_dst, dma_src, len,
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MSGDMA_DESC_STRIDE_RW);
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dst_avail -= len;
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src_avail -= len;
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if (!first)
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first = new;
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else
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list_add_tail(&new->node, &first->tx_list);
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fetch:
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/* Fetch the next dst scatterlist entry */
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if (dst_avail == 0) {
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if (dst_sg_len == 0)
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break;
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dst_sg = sg_next(dst_sg);
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if (dst_sg == NULL)
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break;
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dst_sg_len--;
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dst_avail = sg_dma_len(dst_sg);
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}
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/* Fetch the next src scatterlist entry */
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if (src_avail == 0) {
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if (src_sg_len == 0)
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break;
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src_sg = sg_next(src_sg);
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if (src_sg == NULL)
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break;
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src_sg_len--;
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src_avail = sg_dma_len(src_sg);
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}
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}
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msgdma_desc_config_eod(desc);
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first->async_tx.flags = flags;
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return &first->async_tx;
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}
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/**
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* msgdma_prep_slave_sg - prepare descriptors for a slave sg transaction
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*
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@ -943,7 +851,6 @@ static int msgdma_probe(struct platform_device *pdev)
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/* Set DMA capabilities */
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dma_cap_zero(dma_dev->cap_mask);
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dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
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dma_cap_set(DMA_SG, dma_dev->cap_mask);
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dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
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dma_dev->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
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@ -962,7 +869,6 @@ static int msgdma_probe(struct platform_device *pdev)
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dma_dev->copy_align = DMAENGINE_ALIGN_4_BYTES;
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dma_dev->device_prep_dma_memcpy = msgdma_prep_memcpy;
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dma_dev->device_prep_dma_sg = msgdma_prep_sg;
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dma_dev->device_prep_slave_sg = msgdma_prep_slave_sg;
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dma_dev->device_config = msgdma_dma_config;
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