forked from luck/tmp_suning_uos_patched
Merge branch 'drm-fixes-4.4' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
some big endian fixes and one regression fix. * 'drm-fixes-4.4' of git://people.freedesktop.org/~agd5f/linux: radeon: Fix VCE IB test on Big-Endian systems radeon: Fix VCE ring test for Big-Endian systems radeon/cik: Fix GFX IB test on Big-Endian drm/amdgpu: fix the lost duplicates checking
This commit is contained in:
commit
49307da31b
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@ -477,6 +477,14 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
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if (domain == AMDGPU_GEM_DOMAIN_CPU)
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goto error_unreserve;
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}
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list_for_each_entry(entry, &duplicates, head) {
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domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type);
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/* if anything is swapped out don't swap it in here,
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just abort and wait for the next CS */
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if (domain == AMDGPU_GEM_DOMAIN_CPU)
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goto error_unreserve;
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}
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r = amdgpu_vm_update_page_directory(adev, bo_va->vm);
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if (r)
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goto error_unreserve;
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@ -4173,11 +4173,7 @@ void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
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control |= ib->length_dw | (vm_id << 24);
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radeon_ring_write(ring, header);
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radeon_ring_write(ring,
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#ifdef __BIG_ENDIAN
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(2 << 0) |
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#endif
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(ib->gpu_addr & 0xFFFFFFFC));
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radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFFC));
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radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
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radeon_ring_write(ring, control);
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}
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@ -361,31 +361,31 @@ int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
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/* stitch together an VCE create msg */
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ib.length_dw = 0;
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ib.ptr[ib.length_dw++] = 0x0000000c; /* len */
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ib.ptr[ib.length_dw++] = 0x00000001; /* session cmd */
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ib.ptr[ib.length_dw++] = handle;
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ib.ptr[ib.length_dw++] = cpu_to_le32(0x0000000c); /* len */
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ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000001); /* session cmd */
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ib.ptr[ib.length_dw++] = cpu_to_le32(handle);
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ib.ptr[ib.length_dw++] = 0x00000030; /* len */
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ib.ptr[ib.length_dw++] = 0x01000001; /* create cmd */
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ib.ptr[ib.length_dw++] = 0x00000000;
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ib.ptr[ib.length_dw++] = 0x00000042;
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ib.ptr[ib.length_dw++] = 0x0000000a;
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ib.ptr[ib.length_dw++] = 0x00000001;
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ib.ptr[ib.length_dw++] = 0x00000080;
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ib.ptr[ib.length_dw++] = 0x00000060;
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ib.ptr[ib.length_dw++] = 0x00000100;
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ib.ptr[ib.length_dw++] = 0x00000100;
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ib.ptr[ib.length_dw++] = 0x0000000c;
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ib.ptr[ib.length_dw++] = 0x00000000;
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ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000030); /* len */
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ib.ptr[ib.length_dw++] = cpu_to_le32(0x01000001); /* create cmd */
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ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000000);
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ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000042);
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ib.ptr[ib.length_dw++] = cpu_to_le32(0x0000000a);
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ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000001);
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ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000080);
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ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000060);
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ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000100);
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ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000100);
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ib.ptr[ib.length_dw++] = cpu_to_le32(0x0000000c);
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ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000000);
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ib.ptr[ib.length_dw++] = 0x00000014; /* len */
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ib.ptr[ib.length_dw++] = 0x05000005; /* feedback buffer */
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ib.ptr[ib.length_dw++] = upper_32_bits(dummy);
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ib.ptr[ib.length_dw++] = dummy;
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ib.ptr[ib.length_dw++] = 0x00000001;
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ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000014); /* len */
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ib.ptr[ib.length_dw++] = cpu_to_le32(0x05000005); /* feedback buffer */
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ib.ptr[ib.length_dw++] = cpu_to_le32(upper_32_bits(dummy));
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ib.ptr[ib.length_dw++] = cpu_to_le32(dummy);
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ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000001);
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for (i = ib.length_dw; i < ib_size_dw; ++i)
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ib.ptr[i] = 0x0;
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ib.ptr[i] = cpu_to_le32(0x0);
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r = radeon_ib_schedule(rdev, &ib, NULL, false);
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if (r) {
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@ -428,21 +428,21 @@ int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
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/* stitch together an VCE destroy msg */
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ib.length_dw = 0;
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ib.ptr[ib.length_dw++] = 0x0000000c; /* len */
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ib.ptr[ib.length_dw++] = 0x00000001; /* session cmd */
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ib.ptr[ib.length_dw++] = handle;
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ib.ptr[ib.length_dw++] = cpu_to_le32(0x0000000c); /* len */
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ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000001); /* session cmd */
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ib.ptr[ib.length_dw++] = cpu_to_le32(handle);
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ib.ptr[ib.length_dw++] = 0x00000014; /* len */
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ib.ptr[ib.length_dw++] = 0x05000005; /* feedback buffer */
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ib.ptr[ib.length_dw++] = upper_32_bits(dummy);
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ib.ptr[ib.length_dw++] = dummy;
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ib.ptr[ib.length_dw++] = 0x00000001;
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ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000014); /* len */
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ib.ptr[ib.length_dw++] = cpu_to_le32(0x05000005); /* feedback buffer */
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ib.ptr[ib.length_dw++] = cpu_to_le32(upper_32_bits(dummy));
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ib.ptr[ib.length_dw++] = cpu_to_le32(dummy);
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ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000001);
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ib.ptr[ib.length_dw++] = 0x00000008; /* len */
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ib.ptr[ib.length_dw++] = 0x02000001; /* destroy cmd */
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ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000008); /* len */
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ib.ptr[ib.length_dw++] = cpu_to_le32(0x02000001); /* destroy cmd */
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for (i = ib.length_dw; i < ib_size_dw; ++i)
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ib.ptr[i] = 0x0;
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ib.ptr[i] = cpu_to_le32(0x0);
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r = radeon_ib_schedule(rdev, &ib, NULL, false);
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if (r) {
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@ -699,12 +699,12 @@ bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
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{
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uint64_t addr = semaphore->gpu_addr;
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radeon_ring_write(ring, VCE_CMD_SEMAPHORE);
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radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);
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radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);
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radeon_ring_write(ring, 0x01003000 | (emit_wait ? 1 : 0));
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radeon_ring_write(ring, cpu_to_le32(VCE_CMD_SEMAPHORE));
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radeon_ring_write(ring, cpu_to_le32((addr >> 3) & 0x000FFFFF));
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radeon_ring_write(ring, cpu_to_le32((addr >> 23) & 0x000FFFFF));
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radeon_ring_write(ring, cpu_to_le32(0x01003000 | (emit_wait ? 1 : 0)));
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if (!emit_wait)
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radeon_ring_write(ring, VCE_CMD_END);
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radeon_ring_write(ring, cpu_to_le32(VCE_CMD_END));
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return true;
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}
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@ -719,10 +719,10 @@ bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
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void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
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{
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struct radeon_ring *ring = &rdev->ring[ib->ring];
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radeon_ring_write(ring, VCE_CMD_IB);
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radeon_ring_write(ring, ib->gpu_addr);
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radeon_ring_write(ring, upper_32_bits(ib->gpu_addr));
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radeon_ring_write(ring, ib->length_dw);
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radeon_ring_write(ring, cpu_to_le32(VCE_CMD_IB));
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radeon_ring_write(ring, cpu_to_le32(ib->gpu_addr));
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radeon_ring_write(ring, cpu_to_le32(upper_32_bits(ib->gpu_addr)));
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radeon_ring_write(ring, cpu_to_le32(ib->length_dw));
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}
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/**
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@ -738,12 +738,12 @@ void radeon_vce_fence_emit(struct radeon_device *rdev,
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struct radeon_ring *ring = &rdev->ring[fence->ring];
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uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;
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radeon_ring_write(ring, VCE_CMD_FENCE);
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radeon_ring_write(ring, addr);
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radeon_ring_write(ring, upper_32_bits(addr));
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radeon_ring_write(ring, fence->seq);
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radeon_ring_write(ring, VCE_CMD_TRAP);
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radeon_ring_write(ring, VCE_CMD_END);
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radeon_ring_write(ring, cpu_to_le32(VCE_CMD_FENCE));
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radeon_ring_write(ring, cpu_to_le32(addr));
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radeon_ring_write(ring, cpu_to_le32(upper_32_bits(addr)));
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radeon_ring_write(ring, cpu_to_le32(fence->seq));
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radeon_ring_write(ring, cpu_to_le32(VCE_CMD_TRAP));
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radeon_ring_write(ring, cpu_to_le32(VCE_CMD_END));
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}
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/**
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@ -765,7 +765,7 @@ int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
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ring->idx, r);
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return r;
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}
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radeon_ring_write(ring, VCE_CMD_END);
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radeon_ring_write(ring, cpu_to_le32(VCE_CMD_END));
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radeon_ring_unlock_commit(rdev, ring, false);
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for (i = 0; i < rdev->usec_timeout; i++) {
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