forked from luck/tmp_suning_uos_patched
[PATCH] powerpc/cell: add iommu support for larger memory
So far, the iommu code was hardwired to a linear mapping between 0x20000000 and 0x40000000, so it could only support 512MB of RAM. This patch still keeps the linear mapping, but looks for proper ibm,dma-window properties to set up larger windows, this makes the maximum supported RAM size 2GB. If there is anything unusual about the dma-window properties, we fall back to the old behavior. We also support switching off the iommu completely now with the regular iommu=off command line option. Signed-off-by: Arnd Bergmann <arndb@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Jens.Osterkamp@de.ibm.com
Paul Mackerras
parent
38307341af
commit
49d65b3ac5
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@ -29,6 +29,8 @@
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#include <linux/bootmem.h>
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#include <linux/mm.h>
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#include <linux/dma-mapping.h>
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#include <linux/kernel.h>
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#include <linux/compiler.h>
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#include <asm/sections.h>
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#include <asm/iommu.h>
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@ -40,6 +42,7 @@
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#include <asm/abs_addr.h>
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#include <asm/system.h>
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#include <asm/ppc-pci.h>
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#include <asm/udbg.h>
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#include "iommu.h"
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@ -220,8 +223,6 @@ set_iopt_cache(void __iomem *base, unsigned long index,
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{
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unsigned long __iomem *tags = base + IOC_PT_CACHE_DIR;
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unsigned long __iomem *p = base + IOC_PT_CACHE_REG;
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pr_debug("iopt %02lx was v%016lx/t%016lx, store v%016lx/t%016lx\n",
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index, get_iopt_cache(base, index, &oldtag), oldtag, val, tag);
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out_be64(p, val);
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out_be64(&tags[index], tag);
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@ -248,66 +249,175 @@ set_iocmd_config(void __iomem *base)
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out_be64(p, conf | IOCMD_CONF_TE);
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}
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/* FIXME: get these from the device tree */
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#define ioc_base 0x20000511000ull
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#define ioc_mmio_base 0x20000510000ull
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#define ioid 0x48a
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#define iopt_phys_offset (- 0x20000000) /* We have a 512MB offset from the SB */
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#define io_page_size 0x1000000
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static unsigned long map_iopt_entry(unsigned long address)
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static void enable_mapping(void __iomem *base, void __iomem *mmio_base)
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{
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switch (address >> 20) {
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case 0x600:
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address = 0x24020000000ull; /* spider i/o */
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break;
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default:
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address += iopt_phys_offset;
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break;
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}
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return get_iopt_entry(address, ioid, IOPT_PROT_RW);
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set_iocmd_config(base);
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set_iost_origin(mmio_base);
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}
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static void iommu_bus_setup_null(struct pci_bus *b) { }
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static void iommu_dev_setup_null(struct pci_dev *d) { }
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static void iommu_bus_setup_null(struct pci_bus *b) { }
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struct cell_iommu {
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unsigned long base;
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unsigned long mmio_base;
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void __iomem *mapped_base;
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void __iomem *mapped_mmio_base;
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};
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static struct cell_iommu cell_iommus[NR_CPUS];
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/* initialize the iommu to support a simple linear mapping
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* for each DMA window used by any device. For now, we
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* happen to know that there is only one DMA window in use,
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* starting at iopt_phys_offset. */
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static void cell_map_iommu(void)
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static void cell_do_map_iommu(struct cell_iommu *iommu,
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unsigned int ioid,
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unsigned long map_start,
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unsigned long map_size)
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{
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unsigned long address;
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void __iomem *base;
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unsigned long io_address, real_address;
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void __iomem *ioc_base, *ioc_mmio_base;
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ioste ioste;
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unsigned long index;
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base = __ioremap(ioc_base, 0x1000, _PAGE_NO_CACHE);
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pr_debug("%lx mapped to %p\n", ioc_base, base);
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set_iocmd_config(base);
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iounmap(base);
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/* we pretend the io page table was at a very high address */
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const unsigned long fake_iopt = 0x10000000000ul;
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const unsigned long io_page_size = 0x1000000; /* use 16M pages */
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const unsigned long io_segment_size = 0x10000000; /* 256M */
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base = __ioremap(ioc_mmio_base, 0x1000, _PAGE_NO_CACHE);
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pr_debug("%lx mapped to %p\n", ioc_mmio_base, base);
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ioc_base = iommu->mapped_base;
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ioc_mmio_base = iommu->mapped_mmio_base;
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set_iost_origin(base);
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for (address = 0; address < 0x100000000ul; address += io_page_size) {
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ioste = get_iost_entry(0x10000000000ul, address, io_page_size);
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if ((address & 0xfffffff) == 0) /* segment start */
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set_iost_cache(base, address >> 28, ioste);
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index = get_ioc_hash_1way(ioste, address);
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for (real_address = 0, io_address = 0;
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io_address <= map_start + map_size;
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real_address += io_page_size, io_address += io_page_size) {
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ioste = get_iost_entry(fake_iopt, io_address, io_page_size);
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if ((real_address % io_segment_size) == 0) /* segment start */
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set_iost_cache(ioc_mmio_base,
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io_address >> 28, ioste);
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index = get_ioc_hash_1way(ioste, io_address);
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pr_debug("addr %08lx, index %02lx, ioste %016lx\n",
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address, index, ioste.val);
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set_iopt_cache(base,
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get_ioc_hash_1way(ioste, address),
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get_ioc_tag(ioste, address),
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map_iopt_entry(address));
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io_address, index, ioste.val);
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set_iopt_cache(ioc_mmio_base,
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get_ioc_hash_1way(ioste, io_address),
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get_ioc_tag(ioste, io_address),
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get_iopt_entry(real_address-map_start, ioid, IOPT_PROT_RW));
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}
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iounmap(base);
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}
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static void iommu_devnode_setup(struct device_node *d)
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{
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unsigned int *ioid;
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unsigned long *dma_window, map_start, map_size, token;
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struct cell_iommu *iommu;
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ioid = (unsigned int *)get_property(d, "ioid", NULL);
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if (!ioid)
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pr_debug("No ioid entry found !\n");
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dma_window = (unsigned long *)get_property(d, "ibm,dma-window", NULL);
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if (!dma_window)
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pr_debug("No ibm,dma-window entry found !\n");
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map_start = dma_window[1];
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map_size = dma_window[2];
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token = dma_window[0] >> 32;
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iommu = &cell_iommus[token];
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cell_do_map_iommu(iommu, *ioid, map_start, map_size);
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}
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static void iommu_bus_setup(struct pci_bus *b)
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{
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struct device_node *d = (struct device_node *)b->sysdata;
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iommu_devnode_setup(d);
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}
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static int cell_map_iommu_hardcoded(int num_nodes)
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{
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struct cell_iommu *iommu = NULL;
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pr_debug("%s(%d): Using hardcoded defaults\n", __FUNCTION__, __LINE__);
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/* node 0 */
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iommu = &cell_iommus[0];
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iommu->mapped_base = __ioremap(0x20000511000, 0x1000, _PAGE_NO_CACHE);
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iommu->mapped_mmio_base = __ioremap(0x20000510000, 0x1000, _PAGE_NO_CACHE);
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enable_mapping(iommu->mapped_base, iommu->mapped_mmio_base);
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cell_do_map_iommu(iommu, 0x048a,
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0x20000000ul,0x20000000ul);
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if (num_nodes < 2)
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return 0;
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/* node 1 */
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iommu = &cell_iommus[1];
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iommu->mapped_base = __ioremap(0x30000511000, 0x1000, _PAGE_NO_CACHE);
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iommu->mapped_mmio_base = __ioremap(0x30000510000, 0x1000, _PAGE_NO_CACHE);
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enable_mapping(iommu->mapped_base, iommu->mapped_mmio_base);
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cell_do_map_iommu(iommu, 0x048a,
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0x20000000,0x20000000ul);
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return 0;
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}
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static int cell_map_iommu(void)
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{
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unsigned int num_nodes = 0, *node_id;
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unsigned long *base, *mmio_base;
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struct device_node *dn;
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struct cell_iommu *iommu = NULL;
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/* determine number of nodes (=iommus) */
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pr_debug("%s(%d): determining number of nodes...", __FUNCTION__, __LINE__);
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for(dn = of_find_node_by_type(NULL, "cpu");
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dn;
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dn = of_find_node_by_type(dn, "cpu")) {
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node_id = (unsigned int *)get_property(dn, "node-id", NULL);
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if (num_nodes < *node_id)
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num_nodes = *node_id;
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}
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num_nodes++;
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pr_debug("%i found.\n", num_nodes);
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/* map the iommu registers for each node */
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pr_debug("%s(%d): Looping through nodes\n", __FUNCTION__, __LINE__);
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for(dn = of_find_node_by_type(NULL, "cpu");
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dn;
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dn = of_find_node_by_type(dn, "cpu")) {
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node_id = (unsigned int *)get_property(dn, "node-id", NULL);
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base = (unsigned long *)get_property(dn, "ioc-cache", NULL);
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mmio_base = (unsigned long *)get_property(dn, "ioc-translation", NULL);
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if (!base || !mmio_base || !node_id)
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return cell_map_iommu_hardcoded(num_nodes);
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iommu = &cell_iommus[*node_id];
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iommu->base = *base;
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iommu->mmio_base = *mmio_base;
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iommu->mapped_base = __ioremap(*base, 0x1000, _PAGE_NO_CACHE);
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iommu->mapped_mmio_base = __ioremap(*mmio_base, 0x1000, _PAGE_NO_CACHE);
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enable_mapping(iommu->mapped_base,
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iommu->mapped_mmio_base);
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/* everything else will be done in iommu_bus_setup */
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}
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return 1;
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}
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static void *cell_alloc_coherent(struct device *hwdev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag)
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@ -365,11 +475,28 @@ static int cell_dma_supported(struct device *dev, u64 mask)
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void cell_init_iommu(void)
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{
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cell_map_iommu();
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int setup_bus = 0;
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/* Direct I/O, IOMMU off */
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ppc_md.iommu_dev_setup = iommu_dev_setup_null;
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ppc_md.iommu_bus_setup = iommu_bus_setup_null;
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if (of_find_node_by_path("/mambo")) {
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pr_info("Not using iommu on systemsim\n");
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} else {
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if (!(of_chosen &&
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get_property(of_chosen, "linux,iommu-off", NULL)))
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setup_bus = cell_map_iommu();
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if (setup_bus) {
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pr_debug("%s: IOMMU mapping activated\n", __FUNCTION__);
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ppc_md.iommu_dev_setup = iommu_dev_setup_null;
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ppc_md.iommu_bus_setup = iommu_bus_setup;
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} else {
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pr_debug("%s: IOMMU mapping activated, "
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"no device action necessary\n", __FUNCTION__);
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/* Direct I/O, IOMMU off */
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ppc_md.iommu_dev_setup = iommu_dev_setup_null;
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ppc_md.iommu_bus_setup = iommu_bus_setup_null;
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}
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}
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pci_dma_ops.alloc_coherent = cell_alloc_coherent;
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pci_dma_ops.free_coherent = cell_free_coherent;
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