forked from luck/tmp_suning_uos_patched
interconnect patches for 5.4
Here are the interconnect driver updates for the 5.4-rc1 merge window. - New feature is the path tagging support that helps with grouping and aggregating the bandwidth requests into separate buckets based on a tag. - The first user of the path tagging is the Qualcomm sdm845 driver that now implements support for wake/sleep sets. This allows consumer drivers to express their bandwidth needs for the different CPU power states. - New interconnect driver for the qcs404 platforms and a driver that communicates bandwidth requests with remote processor over shared memory. - Cleanups and fixes. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJdX/5XAAoJEIDQzArG2BZjK88QAKqqfxwnvGwRGxRuDM2k2nnw B41wgEkrOg0ArIDIBEyiI/QVV8u7kch6d8oJQpy27xTmXNKH4hTUVA6GUlzVLd5e Kdr9COUNjXrxUZ834cEonE3bJYosudgLH3qWOJ2nM3nEHipeJcFB1Z/+QmVwZPs4 P7RM6T04VqMlXxq1TIeqQs7T+nt6m+Bo+gJ/EfTUtK7EtP9np5cY1ufSnSJahJLX IfFJsya8e22xaQKV6Z3tR4LhR8u7q32mgaj2EVC1qL3H33M73UBcov/bGGpTrlqC dpElzdexML0iFxL/YxLkYmMoqx6fxCA2+in0Jy9/OBs7S82qWmejdRerEvHKvnWY J5g7NwL6sBvCn0To3W6FGXfvlC+4cFsT+GMQWD9q5EakkH1bzFBmn/k2QdAynOYn 9bjVw1i9Y+AsdK9eBxj+4DUZCGBPgSEwKpPdwYsPg2dt6Cwdk6AURLdWTZGI/UtD YzKe0n/ilrwHCF/lTaSuQpMaZTbbjw0mgKVbD0G4GVtT6JhF/AOhvmE0vD7SBs6h sqnjwfFOnzjOjYhbHLPXD8FhR33siyzrB7pAioMhsDxGkprdJD9QTKjNT0Hv+0MW GPNOxvRtlzDiGhFfvQQ+gbyJ+t3NXbQzS5XzMhu+39c6iRclr7Tp5R7nwN5tNc3D XSrY2BkLuspsnV2iCO76 =TVC/ -----END PGP SIGNATURE----- Merge tag 'icc-5.4-rc1' of https://git.linaro.org/people/georgi.djakov/linux into char-misc-next Georgi writes: interconnect patches for 5.4 Here are the interconnect driver updates for the 5.4-rc1 merge window. - New feature is the path tagging support that helps with grouping and aggregating the bandwidth requests into separate buckets based on a tag. - The first user of the path tagging is the Qualcomm sdm845 driver that now implements support for wake/sleep sets. This allows consumer drivers to express their bandwidth needs for the different CPU power states. - New interconnect driver for the qcs404 platforms and a driver that communicates bandwidth requests with remote processor over shared memory. - Cleanups and fixes. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> * tag 'icc-5.4-rc1' of https://git.linaro.org/people/georgi.djakov/linux: drivers: qcom: Add BCM vote macro to header interconnect: qcom: remove COMPILE_TEST from CONFIG_INTERCONNECT_QCOM_QCS404 interconnect: qcom: Add QCS404 interconnect provider driver interconnect: qcom: Add interconnect RPM over SMD driver dt-bindings: interconnect: Add Qualcomm QCS404 DT bindings interconnect: qcom: Add tagging and wake/sleep support for sdm845 interconnect: Add pre_aggregate() callback interconnect: Add support for path tags
This commit is contained in:
Greg Kroah-Hartman
commit
4a79ce748f
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@ -0,0 +1,45 @@
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Qualcomm QCS404 Network-On-Chip interconnect driver binding
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-----------------------------------------------------------
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Required properties :
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- compatible : shall contain only one of the following:
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"qcom,qcs404-bimc"
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"qcom,qcs404-pcnoc"
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"qcom,qcs404-snoc"
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- #interconnect-cells : should contain 1
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reg : specifies the physical base address and size of registers
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clocks : list of phandles and specifiers to all interconnect bus clocks
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clock-names : clock names should include both "bus" and "bus_a"
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Example:
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soc {
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...
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bimc: interconnect@400000 {
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reg = <0x00400000 0x80000>;
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compatible = "qcom,qcs404-bimc";
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#interconnect-cells = <1>;
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clock-names = "bus", "bus_a";
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clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
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<&rpmcc RPM_SMD_BIMC_A_CLK>;
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};
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pnoc: interconnect@500000 {
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reg = <0x00500000 0x15080>;
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compatible = "qcom,qcs404-pcnoc";
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#interconnect-cells = <1>;
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clock-names = "bus", "bus_a";
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clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
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<&rpmcc RPM_SMD_PNOC_A_CLK>;
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};
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snoc: interconnect@580000 {
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reg = <0x00580000 0x23080>;
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compatible = "qcom,qcs404-snoc";
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#interconnect-cells = <1>;
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clock-names = "bus", "bus_a";
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clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
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<&rpmcc RPM_SMD_SNOC_A_CLK>;
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};
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};
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018, The Linux Foundation. All rights reserved.
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* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
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*/
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#include <linux/clk-provider.h>
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@ -12,23 +12,13 @@
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#include <linux/platform_device.h>
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#include <soc/qcom/cmd-db.h>
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#include <soc/qcom/rpmh.h>
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#include <soc/qcom/tcs.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#define CLK_RPMH_ARC_EN_OFFSET 0
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#define CLK_RPMH_VRM_EN_OFFSET 4
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#define BCM_TCS_CMD_COMMIT_MASK 0x40000000
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#define BCM_TCS_CMD_VALID_SHIFT 29
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#define BCM_TCS_CMD_VOTE_MASK 0x3fff
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#define BCM_TCS_CMD_VOTE_SHIFT 0
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#define BCM_TCS_CMD(valid, vote) \
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(BCM_TCS_CMD_COMMIT_MASK | \
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((valid) << BCM_TCS_CMD_VALID_SHIFT) | \
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((vote & BCM_TCS_CMD_VOTE_MASK) \
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<< BCM_TCS_CMD_VOTE_SHIFT))
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/**
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* struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager(BCM)
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* @unit: divisor used to convert Hz value to an RPMh msg
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@ -269,7 +259,7 @@ static int clk_rpmh_bcm_send_cmd(struct clk_rpmh *c, bool enable)
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}
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cmd.addr = c->res_addr;
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cmd.data = BCM_TCS_CMD(enable, cmd_state);
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cmd.data = BCM_TCS_CMD(1, enable, 0, cmd_state);
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ret = rpmh_write_async(c->dev, RPMH_ACTIVE_ONLY_STATE, &cmd, 1);
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if (ret) {
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@ -29,6 +29,7 @@ static struct dentry *icc_debugfs_dir;
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* @req_node: entry in list of requests for the particular @node
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* @node: the interconnect node to which this constraint applies
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* @dev: reference to the device that sets the constraints
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* @tag: path tag (optional)
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* @avg_bw: an integer describing the average bandwidth in kBps
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* @peak_bw: an integer describing the peak bandwidth in kBps
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*/
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@ -36,6 +37,7 @@ struct icc_req {
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struct hlist_node req_node;
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struct icc_node *node;
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struct device *dev;
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u32 tag;
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u32 avg_bw;
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u32 peak_bw;
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};
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@ -203,8 +205,11 @@ static int aggregate_requests(struct icc_node *node)
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node->avg_bw = 0;
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node->peak_bw = 0;
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if (p->pre_aggregate)
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p->pre_aggregate(node);
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hlist_for_each_entry(r, &node->req_list, req_node)
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p->aggregate(node, r->avg_bw, r->peak_bw,
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p->aggregate(node, r->tag, r->avg_bw, r->peak_bw,
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&node->avg_bw, &node->peak_bw);
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return 0;
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@ -385,6 +390,26 @@ struct icc_path *of_icc_get(struct device *dev, const char *name)
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}
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EXPORT_SYMBOL_GPL(of_icc_get);
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/**
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* icc_set_tag() - set an optional tag on a path
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* @path: the path we want to tag
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* @tag: the tag value
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*
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* This function allows consumers to append a tag to the requests associated
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* with a path, so that a different aggregation could be done based on this tag.
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*/
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void icc_set_tag(struct icc_path *path, u32 tag)
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{
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int i;
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if (!path)
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return;
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for (i = 0; i < path->num_nodes; i++)
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path->reqs[i].tag = tag;
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}
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EXPORT_SYMBOL_GPL(icc_set_tag);
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/**
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* icc_set_bw() - set bandwidth constraints on an interconnect path
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* @path: reference to the path returned by icc_get()
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@ -5,6 +5,15 @@ config INTERCONNECT_QCOM
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help
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Support for Qualcomm's Network-on-Chip interconnect hardware.
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config INTERCONNECT_QCOM_QCS404
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tristate "Qualcomm QCS404 interconnect driver"
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depends on INTERCONNECT_QCOM
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depends on QCOM_SMD_RPM
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select INTERCONNECT_QCOM_SMD_RPM
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help
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This is a driver for the Qualcomm Network-on-Chip on qcs404-based
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platforms.
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config INTERCONNECT_QCOM_SDM845
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tristate "Qualcomm SDM845 interconnect driver"
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depends on INTERCONNECT_QCOM
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@ -12,3 +21,6 @@ config INTERCONNECT_QCOM_SDM845
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help
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This is a driver for the Qualcomm Network-on-Chip on sdm845-based
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platforms.
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config INTERCONNECT_QCOM_SMD_RPM
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tristate
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@ -1,5 +1,9 @@
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# SPDX-License-Identifier: GPL-2.0
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qnoc-qcs404-objs := qcs404.o
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qnoc-sdm845-objs := sdm845.o
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icc-smd-rpm-objs := smd-rpm.o
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obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.o
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539
drivers/interconnect/qcom/qcs404.c
Normal file
539
drivers/interconnect/qcom/qcs404.c
Normal file
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@ -0,0 +1,539 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Linaro Ltd
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*/
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#include <dt-bindings/interconnect/qcom,qcs404.h>
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/interconnect-provider.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "smd-rpm.h"
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#define RPM_BUS_MASTER_REQ 0x73616d62
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#define RPM_BUS_SLAVE_REQ 0x766c7362
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enum {
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QCS404_MASTER_AMPSS_M0 = 1,
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QCS404_MASTER_GRAPHICS_3D,
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QCS404_MASTER_MDP_PORT0,
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QCS404_SNOC_BIMC_1_MAS,
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QCS404_MASTER_TCU_0,
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QCS404_MASTER_SPDM,
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QCS404_MASTER_BLSP_1,
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QCS404_MASTER_BLSP_2,
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QCS404_MASTER_XM_USB_HS1,
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QCS404_MASTER_CRYPTO_CORE0,
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QCS404_MASTER_SDCC_1,
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QCS404_MASTER_SDCC_2,
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QCS404_SNOC_PNOC_MAS,
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QCS404_MASTER_QPIC,
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QCS404_MASTER_QDSS_BAM,
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QCS404_BIMC_SNOC_MAS,
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QCS404_PNOC_SNOC_MAS,
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QCS404_MASTER_QDSS_ETR,
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QCS404_MASTER_EMAC,
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QCS404_MASTER_PCIE,
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QCS404_MASTER_USB3,
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QCS404_PNOC_INT_0,
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QCS404_PNOC_INT_2,
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QCS404_PNOC_INT_3,
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QCS404_PNOC_SLV_0,
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QCS404_PNOC_SLV_1,
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QCS404_PNOC_SLV_2,
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QCS404_PNOC_SLV_3,
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QCS404_PNOC_SLV_4,
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QCS404_PNOC_SLV_6,
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QCS404_PNOC_SLV_7,
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QCS404_PNOC_SLV_8,
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QCS404_PNOC_SLV_9,
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QCS404_PNOC_SLV_10,
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QCS404_PNOC_SLV_11,
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QCS404_SNOC_QDSS_INT,
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QCS404_SNOC_INT_0,
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QCS404_SNOC_INT_1,
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QCS404_SNOC_INT_2,
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QCS404_SLAVE_EBI_CH0,
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QCS404_BIMC_SNOC_SLV,
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QCS404_SLAVE_SPDM_WRAPPER,
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QCS404_SLAVE_PDM,
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QCS404_SLAVE_PRNG,
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QCS404_SLAVE_TCSR,
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QCS404_SLAVE_SNOC_CFG,
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QCS404_SLAVE_MESSAGE_RAM,
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QCS404_SLAVE_DISPLAY_CFG,
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QCS404_SLAVE_GRAPHICS_3D_CFG,
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QCS404_SLAVE_BLSP_1,
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QCS404_SLAVE_TLMM_NORTH,
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QCS404_SLAVE_PCIE_1,
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QCS404_SLAVE_EMAC_CFG,
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QCS404_SLAVE_BLSP_2,
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QCS404_SLAVE_TLMM_EAST,
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QCS404_SLAVE_TCU,
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QCS404_SLAVE_PMIC_ARB,
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QCS404_SLAVE_SDCC_1,
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QCS404_SLAVE_SDCC_2,
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QCS404_SLAVE_TLMM_SOUTH,
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QCS404_SLAVE_USB_HS,
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QCS404_SLAVE_USB3,
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QCS404_SLAVE_CRYPTO_0_CFG,
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QCS404_PNOC_SNOC_SLV,
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QCS404_SLAVE_APPSS,
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QCS404_SLAVE_WCSS,
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QCS404_SNOC_BIMC_1_SLV,
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QCS404_SLAVE_OCIMEM,
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QCS404_SNOC_PNOC_SLV,
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QCS404_SLAVE_QDSS_STM,
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QCS404_SLAVE_CATS_128,
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QCS404_SLAVE_OCMEM_64,
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QCS404_SLAVE_LPASS,
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};
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#define to_qcom_provider(_provider) \
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container_of(_provider, struct qcom_icc_provider, provider)
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static const struct clk_bulk_data bus_clocks[] = {
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{ .id = "bus" },
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{ .id = "bus_a" },
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};
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/**
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* struct qcom_icc_provider - Qualcomm specific interconnect provider
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* @provider: generic interconnect provider
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* @bus_clks: the clk_bulk_data table of bus clocks
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* @num_clks: the total number of clk_bulk_data entries
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*/
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struct qcom_icc_provider {
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struct icc_provider provider;
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struct clk_bulk_data *bus_clks;
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int num_clks;
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};
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#define QCS404_MAX_LINKS 12
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/**
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* struct qcom_icc_node - Qualcomm specific interconnect nodes
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* @name: the node name used in debugfs
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* @id: a unique node identifier
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* @links: an array of nodes where we can go next while traversing
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* @num_links: the total number of @links
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* @buswidth: width of the interconnect between a node and the bus (bytes)
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* @mas_rpm_id: RPM id for devices that are bus masters
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* @slv_rpm_id: RPM id for devices that are bus slaves
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* @rate: current bus clock rate in Hz
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*/
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struct qcom_icc_node {
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unsigned char *name;
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u16 id;
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u16 links[QCS404_MAX_LINKS];
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u16 num_links;
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u16 buswidth;
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int mas_rpm_id;
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int slv_rpm_id;
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u64 rate;
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};
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struct qcom_icc_desc {
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struct qcom_icc_node **nodes;
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size_t num_nodes;
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};
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#define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \
|
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...) \
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static struct qcom_icc_node _name = { \
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.name = #_name, \
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.id = _id, \
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.buswidth = _buswidth, \
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.mas_rpm_id = _mas_rpm_id, \
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.slv_rpm_id = _slv_rpm_id, \
|
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.num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \
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.links = { __VA_ARGS__ }, \
|
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}
|
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|
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DEFINE_QNODE(mas_apps_proc, QCS404_MASTER_AMPSS_M0, 8, 0, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV);
|
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DEFINE_QNODE(mas_oxili, QCS404_MASTER_GRAPHICS_3D, 8, 6, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV);
|
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DEFINE_QNODE(mas_mdp, QCS404_MASTER_MDP_PORT0, 8, 8, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV);
|
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DEFINE_QNODE(mas_snoc_bimc_1, QCS404_SNOC_BIMC_1_MAS, 8, 76, -1, QCS404_SLAVE_EBI_CH0);
|
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DEFINE_QNODE(mas_tcu_0, QCS404_MASTER_TCU_0, 8, -1, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV);
|
||||
DEFINE_QNODE(mas_spdm, QCS404_MASTER_SPDM, 4, -1, -1, QCS404_PNOC_INT_3);
|
||||
DEFINE_QNODE(mas_blsp_1, QCS404_MASTER_BLSP_1, 4, 41, -1, QCS404_PNOC_INT_3);
|
||||
DEFINE_QNODE(mas_blsp_2, QCS404_MASTER_BLSP_2, 4, 39, -1, QCS404_PNOC_INT_3);
|
||||
DEFINE_QNODE(mas_xi_usb_hs1, QCS404_MASTER_XM_USB_HS1, 8, 138, -1, QCS404_PNOC_INT_0);
|
||||
DEFINE_QNODE(mas_crypto, QCS404_MASTER_CRYPTO_CORE0, 8, 23, -1, QCS404_PNOC_SNOC_SLV, QCS404_PNOC_INT_2);
|
||||
DEFINE_QNODE(mas_sdcc_1, QCS404_MASTER_SDCC_1, 8, 33, -1, QCS404_PNOC_INT_0);
|
||||
DEFINE_QNODE(mas_sdcc_2, QCS404_MASTER_SDCC_2, 8, 35, -1, QCS404_PNOC_INT_0);
|
||||
DEFINE_QNODE(mas_snoc_pcnoc, QCS404_SNOC_PNOC_MAS, 8, 77, -1, QCS404_PNOC_INT_2);
|
||||
DEFINE_QNODE(mas_qpic, QCS404_MASTER_QPIC, 4, -1, -1, QCS404_PNOC_INT_0);
|
||||
DEFINE_QNODE(mas_qdss_bam, QCS404_MASTER_QDSS_BAM, 4, -1, -1, QCS404_SNOC_QDSS_INT);
|
||||
DEFINE_QNODE(mas_bimc_snoc, QCS404_BIMC_SNOC_MAS, 8, 21, -1, QCS404_SLAVE_OCMEM_64, QCS404_SLAVE_CATS_128, QCS404_SNOC_INT_0, QCS404_SNOC_INT_1);
|
||||
DEFINE_QNODE(mas_pcnoc_snoc, QCS404_PNOC_SNOC_MAS, 8, 29, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_2, QCS404_SNOC_INT_0);
|
||||
DEFINE_QNODE(mas_qdss_etr, QCS404_MASTER_QDSS_ETR, 8, -1, -1, QCS404_SNOC_QDSS_INT);
|
||||
DEFINE_QNODE(mas_emac, QCS404_MASTER_EMAC, 8, -1, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_1);
|
||||
DEFINE_QNODE(mas_pcie, QCS404_MASTER_PCIE, 8, -1, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_1);
|
||||
DEFINE_QNODE(mas_usb3, QCS404_MASTER_USB3, 8, -1, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_1);
|
||||
DEFINE_QNODE(pcnoc_int_0, QCS404_PNOC_INT_0, 8, 85, 114, QCS404_PNOC_SNOC_SLV, QCS404_PNOC_INT_2);
|
||||
DEFINE_QNODE(pcnoc_int_2, QCS404_PNOC_INT_2, 8, 124, 184, QCS404_PNOC_SLV_10, QCS404_SLAVE_TCU, QCS404_PNOC_SLV_11, QCS404_PNOC_SLV_2, QCS404_PNOC_SLV_3, QCS404_PNOC_SLV_0, QCS404_PNOC_SLV_1, QCS404_PNOC_SLV_6, QCS404_PNOC_SLV_7, QCS404_PNOC_SLV_4, QCS404_PNOC_SLV_8, QCS404_PNOC_SLV_9);
|
||||
DEFINE_QNODE(pcnoc_int_3, QCS404_PNOC_INT_3, 8, 125, 185, QCS404_PNOC_SNOC_SLV);
|
||||
DEFINE_QNODE(pcnoc_s_0, QCS404_PNOC_SLV_0, 4, 89, 118, QCS404_SLAVE_PRNG, QCS404_SLAVE_SPDM_WRAPPER, QCS404_SLAVE_PDM);
|
||||
DEFINE_QNODE(pcnoc_s_1, QCS404_PNOC_SLV_1, 4, 90, 119, QCS404_SLAVE_TCSR);
|
||||
DEFINE_QNODE(pcnoc_s_2, QCS404_PNOC_SLV_2, 4, -1, -1, QCS404_SLAVE_GRAPHICS_3D_CFG);
|
||||
DEFINE_QNODE(pcnoc_s_3, QCS404_PNOC_SLV_3, 4, 92, 121, QCS404_SLAVE_MESSAGE_RAM);
|
||||
DEFINE_QNODE(pcnoc_s_4, QCS404_PNOC_SLV_4, 4, 93, 122, QCS404_SLAVE_SNOC_CFG);
|
||||
DEFINE_QNODE(pcnoc_s_6, QCS404_PNOC_SLV_6, 4, 94, 123, QCS404_SLAVE_BLSP_1, QCS404_SLAVE_TLMM_NORTH, QCS404_SLAVE_EMAC_CFG);
|
||||
DEFINE_QNODE(pcnoc_s_7, QCS404_PNOC_SLV_7, 4, 95, 124, QCS404_SLAVE_TLMM_SOUTH, QCS404_SLAVE_DISPLAY_CFG, QCS404_SLAVE_SDCC_1, QCS404_SLAVE_PCIE_1, QCS404_SLAVE_SDCC_2);
|
||||
DEFINE_QNODE(pcnoc_s_8, QCS404_PNOC_SLV_8, 4, 96, 125, QCS404_SLAVE_CRYPTO_0_CFG);
|
||||
DEFINE_QNODE(pcnoc_s_9, QCS404_PNOC_SLV_9, 4, 97, 126, QCS404_SLAVE_BLSP_2, QCS404_SLAVE_TLMM_EAST, QCS404_SLAVE_PMIC_ARB);
|
||||
DEFINE_QNODE(pcnoc_s_10, QCS404_PNOC_SLV_10, 4, 157, -1, QCS404_SLAVE_USB_HS);
|
||||
DEFINE_QNODE(pcnoc_s_11, QCS404_PNOC_SLV_11, 4, 158, 246, QCS404_SLAVE_USB3);
|
||||
DEFINE_QNODE(qdss_int, QCS404_SNOC_QDSS_INT, 8, -1, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_1);
|
||||
DEFINE_QNODE(snoc_int_0, QCS404_SNOC_INT_0, 8, 99, 130, QCS404_SLAVE_LPASS, QCS404_SLAVE_APPSS, QCS404_SLAVE_WCSS);
|
||||
DEFINE_QNODE(snoc_int_1, QCS404_SNOC_INT_1, 8, 100, 131, QCS404_SNOC_PNOC_SLV, QCS404_SNOC_INT_2);
|
||||
DEFINE_QNODE(snoc_int_2, QCS404_SNOC_INT_2, 8, 134, 197, QCS404_SLAVE_QDSS_STM, QCS404_SLAVE_OCIMEM);
|
||||
DEFINE_QNODE(slv_ebi, QCS404_SLAVE_EBI_CH0, 8, -1, 0, 0);
|
||||
DEFINE_QNODE(slv_bimc_snoc, QCS404_BIMC_SNOC_SLV, 8, -1, 2, QCS404_BIMC_SNOC_MAS);
|
||||
DEFINE_QNODE(slv_spdm, QCS404_SLAVE_SPDM_WRAPPER, 4, -1, -1, 0);
|
||||
DEFINE_QNODE(slv_pdm, QCS404_SLAVE_PDM, 4, -1, 41, 0);
|
||||
DEFINE_QNODE(slv_prng, QCS404_SLAVE_PRNG, 4, -1, 44, 0);
|
||||
DEFINE_QNODE(slv_tcsr, QCS404_SLAVE_TCSR, 4, -1, 50, 0);
|
||||
DEFINE_QNODE(slv_snoc_cfg, QCS404_SLAVE_SNOC_CFG, 4, -1, 70, 0);
|
||||
DEFINE_QNODE(slv_message_ram, QCS404_SLAVE_MESSAGE_RAM, 4, -1, 55, 0);
|
||||
DEFINE_QNODE(slv_disp_ss_cfg, QCS404_SLAVE_DISPLAY_CFG, 4, -1, -1, 0);
|
||||
DEFINE_QNODE(slv_gpu_cfg, QCS404_SLAVE_GRAPHICS_3D_CFG, 4, -1, -1, 0);
|
||||
DEFINE_QNODE(slv_blsp_1, QCS404_SLAVE_BLSP_1, 4, -1, 39, 0);
|
||||
DEFINE_QNODE(slv_tlmm_north, QCS404_SLAVE_TLMM_NORTH, 4, -1, 214, 0);
|
||||
DEFINE_QNODE(slv_pcie, QCS404_SLAVE_PCIE_1, 4, -1, -1, 0);
|
||||
DEFINE_QNODE(slv_ethernet, QCS404_SLAVE_EMAC_CFG, 4, -1, -1, 0);
|
||||
DEFINE_QNODE(slv_blsp_2, QCS404_SLAVE_BLSP_2, 4, -1, 37, 0);
|
||||
DEFINE_QNODE(slv_tlmm_east, QCS404_SLAVE_TLMM_EAST, 4, -1, 213, 0);
|
||||
DEFINE_QNODE(slv_tcu, QCS404_SLAVE_TCU, 8, -1, -1, 0);
|
||||
DEFINE_QNODE(slv_pmic_arb, QCS404_SLAVE_PMIC_ARB, 4, -1, 59, 0);
|
||||
DEFINE_QNODE(slv_sdcc_1, QCS404_SLAVE_SDCC_1, 4, -1, 31, 0);
|
||||
DEFINE_QNODE(slv_sdcc_2, QCS404_SLAVE_SDCC_2, 4, -1, 33, 0);
|
||||
DEFINE_QNODE(slv_tlmm_south, QCS404_SLAVE_TLMM_SOUTH, 4, -1, -1, 0);
|
||||
DEFINE_QNODE(slv_usb_hs, QCS404_SLAVE_USB_HS, 4, -1, 40, 0);
|
||||
DEFINE_QNODE(slv_usb3, QCS404_SLAVE_USB3, 4, -1, 22, 0);
|
||||
DEFINE_QNODE(slv_crypto_0_cfg, QCS404_SLAVE_CRYPTO_0_CFG, 4, -1, 52, 0);
|
||||
DEFINE_QNODE(slv_pcnoc_snoc, QCS404_PNOC_SNOC_SLV, 8, -1, 45, QCS404_PNOC_SNOC_MAS);
|
||||
DEFINE_QNODE(slv_kpss_ahb, QCS404_SLAVE_APPSS, 4, -1, -1, 0);
|
||||
DEFINE_QNODE(slv_wcss, QCS404_SLAVE_WCSS, 4, -1, 23, 0);
|
||||
DEFINE_QNODE(slv_snoc_bimc_1, QCS404_SNOC_BIMC_1_SLV, 8, -1, 104, QCS404_SNOC_BIMC_1_MAS);
|
||||
DEFINE_QNODE(slv_imem, QCS404_SLAVE_OCIMEM, 8, -1, 26, 0);
|
||||
DEFINE_QNODE(slv_snoc_pcnoc, QCS404_SNOC_PNOC_SLV, 8, -1, 28, QCS404_SNOC_PNOC_MAS);
|
||||
DEFINE_QNODE(slv_qdss_stm, QCS404_SLAVE_QDSS_STM, 4, -1, 30, 0);
|
||||
DEFINE_QNODE(slv_cats_0, QCS404_SLAVE_CATS_128, 16, -1, -1, 0);
|
||||
DEFINE_QNODE(slv_cats_1, QCS404_SLAVE_OCMEM_64, 8, -1, -1, 0);
|
||||
DEFINE_QNODE(slv_lpass, QCS404_SLAVE_LPASS, 4, -1, -1, 0);
|
||||
|
||||
static struct qcom_icc_node *qcs404_bimc_nodes[] = {
|
||||
[MASTER_AMPSS_M0] = &mas_apps_proc,
|
||||
[MASTER_OXILI] = &mas_oxili,
|
||||
[MASTER_MDP_PORT0] = &mas_mdp,
|
||||
[MASTER_SNOC_BIMC_1] = &mas_snoc_bimc_1,
|
||||
[MASTER_TCU_0] = &mas_tcu_0,
|
||||
[SLAVE_EBI_CH0] = &slv_ebi,
|
||||
[SLAVE_BIMC_SNOC] = &slv_bimc_snoc,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc qcs404_bimc = {
|
||||
.nodes = qcs404_bimc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(qcs404_bimc_nodes),
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *qcs404_pcnoc_nodes[] = {
|
||||
[MASTER_SPDM] = &mas_spdm,
|
||||
[MASTER_BLSP_1] = &mas_blsp_1,
|
||||
[MASTER_BLSP_2] = &mas_blsp_2,
|
||||
[MASTER_XI_USB_HS1] = &mas_xi_usb_hs1,
|
||||
[MASTER_CRYPT0] = &mas_crypto,
|
||||
[MASTER_SDCC_1] = &mas_sdcc_1,
|
||||
[MASTER_SDCC_2] = &mas_sdcc_2,
|
||||
[MASTER_SNOC_PCNOC] = &mas_snoc_pcnoc,
|
||||
[MASTER_QPIC] = &mas_qpic,
|
||||
[PCNOC_INT_0] = &pcnoc_int_0,
|
||||
[PCNOC_INT_2] = &pcnoc_int_2,
|
||||
[PCNOC_INT_3] = &pcnoc_int_3,
|
||||
[PCNOC_S_0] = &pcnoc_s_0,
|
||||
[PCNOC_S_1] = &pcnoc_s_1,
|
||||
[PCNOC_S_2] = &pcnoc_s_2,
|
||||
[PCNOC_S_3] = &pcnoc_s_3,
|
||||
[PCNOC_S_4] = &pcnoc_s_4,
|
||||
[PCNOC_S_6] = &pcnoc_s_6,
|
||||
[PCNOC_S_7] = &pcnoc_s_7,
|
||||
[PCNOC_S_8] = &pcnoc_s_8,
|
||||
[PCNOC_S_9] = &pcnoc_s_9,
|
||||
[PCNOC_S_10] = &pcnoc_s_10,
|
||||
[PCNOC_S_11] = &pcnoc_s_11,
|
||||
[SLAVE_SPDM] = &slv_spdm,
|
||||
[SLAVE_PDM] = &slv_pdm,
|
||||
[SLAVE_PRNG] = &slv_prng,
|
||||
[SLAVE_TCSR] = &slv_tcsr,
|
||||
[SLAVE_SNOC_CFG] = &slv_snoc_cfg,
|
||||
[SLAVE_MESSAGE_RAM] = &slv_message_ram,
|
||||
[SLAVE_DISP_SS_CFG] = &slv_disp_ss_cfg,
|
||||
[SLAVE_GPU_CFG] = &slv_gpu_cfg,
|
||||
[SLAVE_BLSP_1] = &slv_blsp_1,
|
||||
[SLAVE_BLSP_2] = &slv_blsp_2,
|
||||
[SLAVE_TLMM_NORTH] = &slv_tlmm_north,
|
||||
[SLAVE_PCIE] = &slv_pcie,
|
||||
[SLAVE_ETHERNET] = &slv_ethernet,
|
||||
[SLAVE_TLMM_EAST] = &slv_tlmm_east,
|
||||
[SLAVE_TCU] = &slv_tcu,
|
||||
[SLAVE_PMIC_ARB] = &slv_pmic_arb,
|
||||
[SLAVE_SDCC_1] = &slv_sdcc_1,
|
||||
[SLAVE_SDCC_2] = &slv_sdcc_2,
|
||||
[SLAVE_TLMM_SOUTH] = &slv_tlmm_south,
|
||||
[SLAVE_USB_HS] = &slv_usb_hs,
|
||||
[SLAVE_USB3] = &slv_usb3,
|
||||
[SLAVE_CRYPTO_0_CFG] = &slv_crypto_0_cfg,
|
||||
[SLAVE_PCNOC_SNOC] = &slv_pcnoc_snoc,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc qcs404_pcnoc = {
|
||||
.nodes = qcs404_pcnoc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(qcs404_pcnoc_nodes),
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *qcs404_snoc_nodes[] = {
|
||||
[MASTER_QDSS_BAM] = &mas_qdss_bam,
|
||||
[MASTER_BIMC_SNOC] = &mas_bimc_snoc,
|
||||
[MASTER_PCNOC_SNOC] = &mas_pcnoc_snoc,
|
||||
[MASTER_QDSS_ETR] = &mas_qdss_etr,
|
||||
[MASTER_EMAC] = &mas_emac,
|
||||
[MASTER_PCIE] = &mas_pcie,
|
||||
[MASTER_USB3] = &mas_usb3,
|
||||
[QDSS_INT] = &qdss_int,
|
||||
[SNOC_INT_0] = &snoc_int_0,
|
||||
[SNOC_INT_1] = &snoc_int_1,
|
||||
[SNOC_INT_2] = &snoc_int_2,
|
||||
[SLAVE_KPSS_AHB] = &slv_kpss_ahb,
|
||||
[SLAVE_WCSS] = &slv_wcss,
|
||||
[SLAVE_SNOC_BIMC_1] = &slv_snoc_bimc_1,
|
||||
[SLAVE_IMEM] = &slv_imem,
|
||||
[SLAVE_SNOC_PCNOC] = &slv_snoc_pcnoc,
|
||||
[SLAVE_QDSS_STM] = &slv_qdss_stm,
|
||||
[SLAVE_CATS_0] = &slv_cats_0,
|
||||
[SLAVE_CATS_1] = &slv_cats_1,
|
||||
[SLAVE_LPASS] = &slv_lpass,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc qcs404_snoc = {
|
||||
.nodes = qcs404_snoc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(qcs404_snoc_nodes),
|
||||
};
|
||||
|
||||
static int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
|
||||
u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
|
||||
{
|
||||
*agg_avg += avg_bw;
|
||||
*agg_peak = max(*agg_peak, peak_bw);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
|
||||
{
|
||||
struct qcom_icc_provider *qp;
|
||||
struct qcom_icc_node *qn;
|
||||
struct icc_provider *provider;
|
||||
struct icc_node *n;
|
||||
u64 sum_bw;
|
||||
u64 max_peak_bw;
|
||||
u64 rate;
|
||||
u32 agg_avg = 0;
|
||||
u32 agg_peak = 0;
|
||||
int ret, i;
|
||||
|
||||
qn = src->data;
|
||||
provider = src->provider;
|
||||
qp = to_qcom_provider(provider);
|
||||
|
||||
list_for_each_entry(n, &provider->nodes, node_list)
|
||||
qcom_icc_aggregate(n, 0, n->avg_bw, n->peak_bw,
|
||||
&agg_avg, &agg_peak);
|
||||
|
||||
sum_bw = icc_units_to_bps(agg_avg);
|
||||
max_peak_bw = icc_units_to_bps(agg_peak);
|
||||
|
||||
/* send bandwidth request message to the RPM processor */
|
||||
if (qn->mas_rpm_id != -1) {
|
||||
ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE,
|
||||
RPM_BUS_MASTER_REQ,
|
||||
qn->mas_rpm_id,
|
||||
sum_bw);
|
||||
if (ret) {
|
||||
pr_err("qcom_icc_rpm_smd_send mas %d error %d\n",
|
||||
qn->mas_rpm_id, ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
if (qn->slv_rpm_id != -1) {
|
||||
ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE,
|
||||
RPM_BUS_SLAVE_REQ,
|
||||
qn->slv_rpm_id,
|
||||
sum_bw);
|
||||
if (ret) {
|
||||
pr_err("qcom_icc_rpm_smd_send slv error %d\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
rate = max(sum_bw, max_peak_bw);
|
||||
|
||||
do_div(rate, qn->buswidth);
|
||||
|
||||
if (qn->rate == rate)
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < qp->num_clks; i++) {
|
||||
ret = clk_set_rate(qp->bus_clks[i].clk, rate);
|
||||
if (ret) {
|
||||
pr_err("%s clk_set_rate error: %d\n",
|
||||
qp->bus_clks[i].id, ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
qn->rate = rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qnoc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
const struct qcom_icc_desc *desc;
|
||||
struct icc_onecell_data *data;
|
||||
struct icc_provider *provider;
|
||||
struct qcom_icc_node **qnodes;
|
||||
struct qcom_icc_provider *qp;
|
||||
struct icc_node *node;
|
||||
size_t num_nodes, i;
|
||||
int ret;
|
||||
|
||||
/* wait for the RPM proxy */
|
||||
if (!qcom_icc_rpm_smd_available())
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
desc = of_device_get_match_data(dev);
|
||||
if (!desc)
|
||||
return -EINVAL;
|
||||
|
||||
qnodes = desc->nodes;
|
||||
num_nodes = desc->num_nodes;
|
||||
|
||||
qp = devm_kzalloc(dev, sizeof(*qp), GFP_KERNEL);
|
||||
if (!qp)
|
||||
return -ENOMEM;
|
||||
|
||||
data = devm_kcalloc(dev, num_nodes, sizeof(*node), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
qp->bus_clks = devm_kmemdup(dev, bus_clocks, sizeof(bus_clocks),
|
||||
GFP_KERNEL);
|
||||
if (!qp->bus_clks)
|
||||
return -ENOMEM;
|
||||
|
||||
qp->num_clks = ARRAY_SIZE(bus_clocks);
|
||||
ret = devm_clk_bulk_get(dev, qp->num_clks, qp->bus_clks);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_bulk_prepare_enable(qp->num_clks, qp->bus_clks);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
provider = &qp->provider;
|
||||
INIT_LIST_HEAD(&provider->nodes);
|
||||
provider->dev = dev;
|
||||
provider->set = qcom_icc_set;
|
||||
provider->aggregate = qcom_icc_aggregate;
|
||||
provider->xlate = of_icc_xlate_onecell;
|
||||
provider->data = data;
|
||||
|
||||
ret = icc_provider_add(provider);
|
||||
if (ret) {
|
||||
dev_err(dev, "error adding interconnect provider: %d\n", ret);
|
||||
clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
|
||||
return ret;
|
||||
}
|
||||
|
||||
for (i = 0; i < num_nodes; i++) {
|
||||
size_t j;
|
||||
|
||||
node = icc_node_create(qnodes[i]->id);
|
||||
if (IS_ERR(node)) {
|
||||
ret = PTR_ERR(node);
|
||||
goto err;
|
||||
}
|
||||
|
||||
node->name = qnodes[i]->name;
|
||||
node->data = qnodes[i];
|
||||
icc_node_add(node, provider);
|
||||
|
||||
dev_dbg(dev, "registered node %s\n", node->name);
|
||||
|
||||
/* populate links */
|
||||
for (j = 0; j < qnodes[i]->num_links; j++)
|
||||
icc_link_create(node, qnodes[i]->links[j]);
|
||||
|
||||
data->nodes[i] = node;
|
||||
}
|
||||
data->num_nodes = num_nodes;
|
||||
|
||||
platform_set_drvdata(pdev, qp);
|
||||
|
||||
return 0;
|
||||
err:
|
||||
list_for_each_entry(node, &provider->nodes, node_list) {
|
||||
icc_node_del(node);
|
||||
icc_node_destroy(node->id);
|
||||
}
|
||||
clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
|
||||
icc_provider_del(provider);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int qnoc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
|
||||
struct icc_provider *provider = &qp->provider;
|
||||
struct icc_node *n;
|
||||
|
||||
list_for_each_entry(n, &provider->nodes, node_list) {
|
||||
icc_node_del(n);
|
||||
icc_node_destroy(n->id);
|
||||
}
|
||||
clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
|
||||
|
||||
return icc_provider_del(provider);
|
||||
}
|
||||
|
||||
static const struct of_device_id qcs404_noc_of_match[] = {
|
||||
{ .compatible = "qcom,qcs404-bimc", .data = &qcs404_bimc },
|
||||
{ .compatible = "qcom,qcs404-pcnoc", .data = &qcs404_pcnoc },
|
||||
{ .compatible = "qcom,qcs404-snoc", .data = &qcs404_snoc },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, qcs404_noc_of_match);
|
||||
|
||||
static struct platform_driver qcs404_noc_driver = {
|
||||
.probe = qnoc_probe,
|
||||
.remove = qnoc_remove,
|
||||
.driver = {
|
||||
.name = "qnoc-qcs404",
|
||||
.of_match_table = qcs404_noc_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(qcs404_noc_driver);
|
||||
MODULE_DESCRIPTION("Qualcomm QCS404 NoC driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
*/
|
||||
|
||||
|
|
@ -20,23 +20,6 @@
|
|||
#include <soc/qcom/rpmh.h>
|
||||
#include <soc/qcom/tcs.h>
|
||||
|
||||
#define BCM_TCS_CMD_COMMIT_SHFT 30
|
||||
#define BCM_TCS_CMD_COMMIT_MASK 0x40000000
|
||||
#define BCM_TCS_CMD_VALID_SHFT 29
|
||||
#define BCM_TCS_CMD_VALID_MASK 0x20000000
|
||||
#define BCM_TCS_CMD_VOTE_X_SHFT 14
|
||||
#define BCM_TCS_CMD_VOTE_MASK 0x3fff
|
||||
#define BCM_TCS_CMD_VOTE_Y_SHFT 0
|
||||
#define BCM_TCS_CMD_VOTE_Y_MASK 0xfffc000
|
||||
|
||||
#define BCM_TCS_CMD(commit, valid, vote_x, vote_y) \
|
||||
(((commit) << BCM_TCS_CMD_COMMIT_SHFT) | \
|
||||
((valid) << BCM_TCS_CMD_VALID_SHFT) | \
|
||||
((cpu_to_le32(vote_x) & \
|
||||
BCM_TCS_CMD_VOTE_MASK) << BCM_TCS_CMD_VOTE_X_SHFT) | \
|
||||
((cpu_to_le32(vote_y) & \
|
||||
BCM_TCS_CMD_VOTE_MASK) << BCM_TCS_CMD_VOTE_Y_SHFT))
|
||||
|
||||
#define to_qcom_provider(_provider) \
|
||||
container_of(_provider, struct qcom_icc_provider, provider)
|
||||
|
||||
|
|
@ -66,6 +49,22 @@ struct bcm_db {
|
|||
#define SDM845_MAX_BCM_PER_NODE 2
|
||||
#define SDM845_MAX_VCD 10
|
||||
|
||||
/*
|
||||
* The AMC bucket denotes constraints that are applied to hardware when
|
||||
* icc_set_bw() completes, whereas the WAKE and SLEEP constraints are applied
|
||||
* when the execution environment transitions between active and low power mode.
|
||||
*/
|
||||
#define QCOM_ICC_BUCKET_AMC 0
|
||||
#define QCOM_ICC_BUCKET_WAKE 1
|
||||
#define QCOM_ICC_BUCKET_SLEEP 2
|
||||
#define QCOM_ICC_NUM_BUCKETS 3
|
||||
#define QCOM_ICC_TAG_AMC BIT(QCOM_ICC_BUCKET_AMC)
|
||||
#define QCOM_ICC_TAG_WAKE BIT(QCOM_ICC_BUCKET_WAKE)
|
||||
#define QCOM_ICC_TAG_SLEEP BIT(QCOM_ICC_BUCKET_SLEEP)
|
||||
#define QCOM_ICC_TAG_ACTIVE_ONLY (QCOM_ICC_TAG_AMC | QCOM_ICC_TAG_WAKE)
|
||||
#define QCOM_ICC_TAG_ALWAYS (QCOM_ICC_TAG_AMC | QCOM_ICC_TAG_WAKE |\
|
||||
QCOM_ICC_TAG_SLEEP)
|
||||
|
||||
/**
|
||||
* struct qcom_icc_node - Qualcomm specific interconnect nodes
|
||||
* @name: the node name used in debugfs
|
||||
|
|
@ -86,8 +85,8 @@ struct qcom_icc_node {
|
|||
u16 num_links;
|
||||
u16 channels;
|
||||
u16 buswidth;
|
||||
u64 sum_avg;
|
||||
u64 max_peak;
|
||||
u64 sum_avg[QCOM_ICC_NUM_BUCKETS];
|
||||
u64 max_peak[QCOM_ICC_NUM_BUCKETS];
|
||||
struct qcom_icc_bcm *bcms[SDM845_MAX_BCM_PER_NODE];
|
||||
size_t num_bcms;
|
||||
};
|
||||
|
|
@ -112,8 +111,8 @@ struct qcom_icc_bcm {
|
|||
const char *name;
|
||||
u32 type;
|
||||
u32 addr;
|
||||
u64 vote_x;
|
||||
u64 vote_y;
|
||||
u64 vote_x[QCOM_ICC_NUM_BUCKETS];
|
||||
u64 vote_y[QCOM_ICC_NUM_BUCKETS];
|
||||
bool dirty;
|
||||
bool keepalive;
|
||||
struct bcm_db aux_data;
|
||||
|
|
@ -555,7 +554,7 @@ inline void tcs_cmd_gen(struct tcs_cmd *cmd, u64 vote_x, u64 vote_y,
|
|||
cmd->wait = true;
|
||||
}
|
||||
|
||||
static void tcs_list_gen(struct list_head *bcm_list,
|
||||
static void tcs_list_gen(struct list_head *bcm_list, int bucket,
|
||||
struct tcs_cmd tcs_list[SDM845_MAX_VCD],
|
||||
int n[SDM845_MAX_VCD])
|
||||
{
|
||||
|
|
@ -573,8 +572,8 @@ static void tcs_list_gen(struct list_head *bcm_list,
|
|||
commit = true;
|
||||
cur_vcd_size = 0;
|
||||
}
|
||||
tcs_cmd_gen(&tcs_list[idx], bcm->vote_x, bcm->vote_y,
|
||||
bcm->addr, commit);
|
||||
tcs_cmd_gen(&tcs_list[idx], bcm->vote_x[bucket],
|
||||
bcm->vote_y[bucket], bcm->addr, commit);
|
||||
idx++;
|
||||
n[batch]++;
|
||||
/*
|
||||
|
|
@ -595,38 +594,56 @@ static void tcs_list_gen(struct list_head *bcm_list,
|
|||
|
||||
static void bcm_aggregate(struct qcom_icc_bcm *bcm)
|
||||
{
|
||||
size_t i;
|
||||
u64 agg_avg = 0;
|
||||
u64 agg_peak = 0;
|
||||
size_t i, bucket;
|
||||
u64 agg_avg[QCOM_ICC_NUM_BUCKETS] = {0};
|
||||
u64 agg_peak[QCOM_ICC_NUM_BUCKETS] = {0};
|
||||
u64 temp;
|
||||
|
||||
for (i = 0; i < bcm->num_nodes; i++) {
|
||||
temp = bcm->nodes[i]->sum_avg * bcm->aux_data.width;
|
||||
do_div(temp, bcm->nodes[i]->buswidth * bcm->nodes[i]->channels);
|
||||
agg_avg = max(agg_avg, temp);
|
||||
for (bucket = 0; bucket < QCOM_ICC_NUM_BUCKETS; bucket++) {
|
||||
for (i = 0; i < bcm->num_nodes; i++) {
|
||||
temp = bcm->nodes[i]->sum_avg[bucket] * bcm->aux_data.width;
|
||||
do_div(temp, bcm->nodes[i]->buswidth * bcm->nodes[i]->channels);
|
||||
agg_avg[bucket] = max(agg_avg[bucket], temp);
|
||||
|
||||
temp = bcm->nodes[i]->max_peak * bcm->aux_data.width;
|
||||
do_div(temp, bcm->nodes[i]->buswidth);
|
||||
agg_peak = max(agg_peak, temp);
|
||||
temp = bcm->nodes[i]->max_peak[bucket] * bcm->aux_data.width;
|
||||
do_div(temp, bcm->nodes[i]->buswidth);
|
||||
agg_peak[bucket] = max(agg_peak[bucket], temp);
|
||||
}
|
||||
|
||||
temp = agg_avg[bucket] * 1000ULL;
|
||||
do_div(temp, bcm->aux_data.unit);
|
||||
bcm->vote_x[bucket] = temp;
|
||||
|
||||
temp = agg_peak[bucket] * 1000ULL;
|
||||
do_div(temp, bcm->aux_data.unit);
|
||||
bcm->vote_y[bucket] = temp;
|
||||
}
|
||||
|
||||
temp = agg_avg * 1000ULL;
|
||||
do_div(temp, bcm->aux_data.unit);
|
||||
bcm->vote_x = temp;
|
||||
|
||||
temp = agg_peak * 1000ULL;
|
||||
do_div(temp, bcm->aux_data.unit);
|
||||
bcm->vote_y = temp;
|
||||
|
||||
if (bcm->keepalive && bcm->vote_x == 0 && bcm->vote_y == 0) {
|
||||
bcm->vote_x = 1;
|
||||
bcm->vote_y = 1;
|
||||
if (bcm->keepalive && bcm->vote_x[QCOM_ICC_BUCKET_AMC] == 0 &&
|
||||
bcm->vote_y[QCOM_ICC_BUCKET_AMC] == 0) {
|
||||
bcm->vote_x[QCOM_ICC_BUCKET_AMC] = 1;
|
||||
bcm->vote_x[QCOM_ICC_BUCKET_WAKE] = 1;
|
||||
bcm->vote_y[QCOM_ICC_BUCKET_AMC] = 1;
|
||||
bcm->vote_y[QCOM_ICC_BUCKET_WAKE] = 1;
|
||||
}
|
||||
|
||||
bcm->dirty = false;
|
||||
}
|
||||
|
||||
static int qcom_icc_aggregate(struct icc_node *node, u32 avg_bw,
|
||||
static void qcom_icc_pre_aggregate(struct icc_node *node)
|
||||
{
|
||||
size_t i;
|
||||
struct qcom_icc_node *qn;
|
||||
|
||||
qn = node->data;
|
||||
|
||||
for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++) {
|
||||
qn->sum_avg[i] = 0;
|
||||
qn->max_peak[i] = 0;
|
||||
}
|
||||
}
|
||||
|
||||
static int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
|
||||
u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
|
||||
{
|
||||
size_t i;
|
||||
|
|
@ -634,12 +651,19 @@ static int qcom_icc_aggregate(struct icc_node *node, u32 avg_bw,
|
|||
|
||||
qn = node->data;
|
||||
|
||||
if (!tag)
|
||||
tag = QCOM_ICC_TAG_ALWAYS;
|
||||
|
||||
for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++) {
|
||||
if (tag & BIT(i)) {
|
||||
qn->sum_avg[i] += avg_bw;
|
||||
qn->max_peak[i] = max_t(u32, qn->max_peak[i], peak_bw);
|
||||
}
|
||||
}
|
||||
|
||||
*agg_avg += avg_bw;
|
||||
*agg_peak = max_t(u32, *agg_peak, peak_bw);
|
||||
|
||||
qn->sum_avg = *agg_avg;
|
||||
qn->max_peak = *agg_peak;
|
||||
|
||||
for (i = 0; i < qn->num_bcms; i++)
|
||||
qn->bcms[i]->dirty = true;
|
||||
|
||||
|
|
@ -675,7 +699,7 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
|
|||
* Construct the command list based on a pre ordered list of BCMs
|
||||
* based on VCD.
|
||||
*/
|
||||
tcs_list_gen(&commit_list, cmds, commit_idx);
|
||||
tcs_list_gen(&commit_list, QCOM_ICC_BUCKET_AMC, cmds, commit_idx);
|
||||
|
||||
if (!commit_idx[0])
|
||||
return ret;
|
||||
|
|
@ -693,6 +717,41 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
|
|||
return ret;
|
||||
}
|
||||
|
||||
INIT_LIST_HEAD(&commit_list);
|
||||
|
||||
for (i = 0; i < qp->num_bcms; i++) {
|
||||
/*
|
||||
* Only generate WAKE and SLEEP commands if a resource's
|
||||
* requirements change as the execution environment transitions
|
||||
* between different power states.
|
||||
*/
|
||||
if (qp->bcms[i]->vote_x[QCOM_ICC_BUCKET_WAKE] !=
|
||||
qp->bcms[i]->vote_x[QCOM_ICC_BUCKET_SLEEP] ||
|
||||
qp->bcms[i]->vote_y[QCOM_ICC_BUCKET_WAKE] !=
|
||||
qp->bcms[i]->vote_y[QCOM_ICC_BUCKET_SLEEP]) {
|
||||
list_add_tail(&qp->bcms[i]->list, &commit_list);
|
||||
}
|
||||
}
|
||||
|
||||
if (list_empty(&commit_list))
|
||||
return ret;
|
||||
|
||||
tcs_list_gen(&commit_list, QCOM_ICC_BUCKET_WAKE, cmds, commit_idx);
|
||||
|
||||
ret = rpmh_write_batch(qp->dev, RPMH_WAKE_ONLY_STATE, cmds, commit_idx);
|
||||
if (ret) {
|
||||
pr_err("Error sending WAKE RPMH requests (%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
tcs_list_gen(&commit_list, QCOM_ICC_BUCKET_SLEEP, cmds, commit_idx);
|
||||
|
||||
ret = rpmh_write_batch(qp->dev, RPMH_SLEEP_STATE, cmds, commit_idx);
|
||||
if (ret) {
|
||||
pr_err("Error sending SLEEP RPMH requests (%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -738,6 +797,7 @@ static int qnoc_probe(struct platform_device *pdev)
|
|||
provider = &qp->provider;
|
||||
provider->dev = &pdev->dev;
|
||||
provider->set = qcom_icc_set;
|
||||
provider->pre_aggregate = qcom_icc_pre_aggregate;
|
||||
provider->aggregate = qcom_icc_aggregate;
|
||||
provider->xlate = of_icc_xlate_onecell;
|
||||
INIT_LIST_HEAD(&provider->nodes);
|
||||
|
|
|
|||
77
drivers/interconnect/qcom/smd-rpm.c
Normal file
77
drivers/interconnect/qcom/smd-rpm.c
Normal file
|
|
@ -0,0 +1,77 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* RPM over SMD communication wrapper for interconnects
|
||||
*
|
||||
* Copyright (C) 2019 Linaro Ltd
|
||||
* Author: Georgi Djakov <georgi.djakov@linaro.org>
|
||||
*/
|
||||
|
||||
#include <linux/interconnect-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/soc/qcom/smd-rpm.h>
|
||||
|
||||
#include "smd-rpm.h"
|
||||
|
||||
#define RPM_KEY_BW 0x00007762
|
||||
|
||||
static struct qcom_smd_rpm *icc_smd_rpm;
|
||||
|
||||
struct icc_rpm_smd_req {
|
||||
__le32 key;
|
||||
__le32 nbytes;
|
||||
__le32 value;
|
||||
};
|
||||
|
||||
bool qcom_icc_rpm_smd_available(void)
|
||||
{
|
||||
return !!icc_smd_rpm;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(qcom_icc_rpm_smd_available);
|
||||
|
||||
int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val)
|
||||
{
|
||||
struct icc_rpm_smd_req req = {
|
||||
.key = cpu_to_le32(RPM_KEY_BW),
|
||||
.nbytes = cpu_to_le32(sizeof(u32)),
|
||||
.value = cpu_to_le32(val),
|
||||
};
|
||||
|
||||
return qcom_rpm_smd_write(icc_smd_rpm, ctx, rsc_type, id, &req,
|
||||
sizeof(req));
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(qcom_icc_rpm_smd_send);
|
||||
|
||||
static int qcom_icc_rpm_smd_remove(struct platform_device *pdev)
|
||||
{
|
||||
icc_smd_rpm = NULL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qcom_icc_rpm_smd_probe(struct platform_device *pdev)
|
||||
{
|
||||
icc_smd_rpm = dev_get_drvdata(pdev->dev.parent);
|
||||
|
||||
if (!icc_smd_rpm) {
|
||||
dev_err(&pdev->dev, "unable to retrieve handle to RPM\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver qcom_interconnect_rpm_smd_driver = {
|
||||
.driver = {
|
||||
.name = "icc_smd_rpm",
|
||||
},
|
||||
.probe = qcom_icc_rpm_smd_probe,
|
||||
.remove = qcom_icc_rpm_smd_remove,
|
||||
};
|
||||
module_platform_driver(qcom_interconnect_rpm_smd_driver);
|
||||
MODULE_AUTHOR("Georgi Djakov <georgi.djakov@linaro.org>");
|
||||
MODULE_DESCRIPTION("Qualcomm SMD RPM interconnect proxy driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:icc_smd_rpm");
|
||||
15
drivers/interconnect/qcom/smd-rpm.h
Normal file
15
drivers/interconnect/qcom/smd-rpm.h
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2019, Linaro Ltd.
|
||||
* Author: Georgi Djakov <georgi.djakov@linaro.org>
|
||||
*/
|
||||
|
||||
#ifndef __DRIVERS_INTERCONNECT_QCOM_SMD_RPM_H
|
||||
#define __DRIVERS_INTERCONNECT_QCOM_SMD_RPM_H
|
||||
|
||||
#include <linux/soc/qcom/smd-rpm.h>
|
||||
|
||||
bool qcom_icc_rpm_smd_available(void);
|
||||
int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val);
|
||||
|
||||
#endif
|
||||
88
include/dt-bindings/interconnect/qcom,qcs404.h
Normal file
88
include/dt-bindings/interconnect/qcom,qcs404.h
Normal file
|
|
@ -0,0 +1,88 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Qualcomm interconnect IDs
|
||||
*
|
||||
* Copyright (c) 2019, Linaro Ltd.
|
||||
* Author: Georgi Djakov <georgi.djakov@linaro.org>
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_QCS404_H
|
||||
#define __DT_BINDINGS_INTERCONNECT_QCOM_QCS404_H
|
||||
|
||||
#define MASTER_AMPSS_M0 0
|
||||
#define MASTER_OXILI 1
|
||||
#define MASTER_MDP_PORT0 2
|
||||
#define MASTER_SNOC_BIMC_1 3
|
||||
#define MASTER_TCU_0 4
|
||||
#define SLAVE_EBI_CH0 5
|
||||
#define SLAVE_BIMC_SNOC 6
|
||||
|
||||
#define MASTER_SPDM 0
|
||||
#define MASTER_BLSP_1 1
|
||||
#define MASTER_BLSP_2 2
|
||||
#define MASTER_XI_USB_HS1 3
|
||||
#define MASTER_CRYPT0 4
|
||||
#define MASTER_SDCC_1 5
|
||||
#define MASTER_SDCC_2 6
|
||||
#define MASTER_SNOC_PCNOC 7
|
||||
#define MASTER_QPIC 8
|
||||
#define PCNOC_INT_0 9
|
||||
#define PCNOC_INT_2 10
|
||||
#define PCNOC_INT_3 11
|
||||
#define PCNOC_S_0 12
|
||||
#define PCNOC_S_1 13
|
||||
#define PCNOC_S_2 14
|
||||
#define PCNOC_S_3 15
|
||||
#define PCNOC_S_4 16
|
||||
#define PCNOC_S_6 17
|
||||
#define PCNOC_S_7 18
|
||||
#define PCNOC_S_8 19
|
||||
#define PCNOC_S_9 20
|
||||
#define PCNOC_S_10 21
|
||||
#define PCNOC_S_11 22
|
||||
#define SLAVE_SPDM 23
|
||||
#define SLAVE_PDM 24
|
||||
#define SLAVE_PRNG 25
|
||||
#define SLAVE_TCSR 26
|
||||
#define SLAVE_SNOC_CFG 27
|
||||
#define SLAVE_MESSAGE_RAM 28
|
||||
#define SLAVE_DISP_SS_CFG 29
|
||||
#define SLAVE_GPU_CFG 30
|
||||
#define SLAVE_BLSP_1 31
|
||||
#define SLAVE_BLSP_2 32
|
||||
#define SLAVE_TLMM_NORTH 33
|
||||
#define SLAVE_PCIE 34
|
||||
#define SLAVE_ETHERNET 35
|
||||
#define SLAVE_TLMM_EAST 36
|
||||
#define SLAVE_TCU 37
|
||||
#define SLAVE_PMIC_ARB 38
|
||||
#define SLAVE_SDCC_1 39
|
||||
#define SLAVE_SDCC_2 40
|
||||
#define SLAVE_TLMM_SOUTH 41
|
||||
#define SLAVE_USB_HS 42
|
||||
#define SLAVE_USB3 43
|
||||
#define SLAVE_CRYPTO_0_CFG 44
|
||||
#define SLAVE_PCNOC_SNOC 45
|
||||
|
||||
#define MASTER_QDSS_BAM 0
|
||||
#define MASTER_BIMC_SNOC 1
|
||||
#define MASTER_PCNOC_SNOC 2
|
||||
#define MASTER_QDSS_ETR 3
|
||||
#define MASTER_EMAC 4
|
||||
#define MASTER_PCIE 5
|
||||
#define MASTER_USB3 6
|
||||
#define QDSS_INT 7
|
||||
#define SNOC_INT_0 8
|
||||
#define SNOC_INT_1 9
|
||||
#define SNOC_INT_2 10
|
||||
#define SLAVE_KPSS_AHB 11
|
||||
#define SLAVE_WCSS 12
|
||||
#define SLAVE_SNOC_BIMC_1 13
|
||||
#define SLAVE_IMEM 14
|
||||
#define SLAVE_SNOC_PCNOC 15
|
||||
#define SLAVE_QDSS_STM 16
|
||||
#define SLAVE_CATS_0 17
|
||||
#define SLAVE_CATS_1 18
|
||||
#define SLAVE_LPASS 19
|
||||
|
||||
#endif
|
||||
|
|
@ -36,6 +36,8 @@ struct icc_node *of_icc_xlate_onecell(struct of_phandle_args *spec,
|
|||
* @nodes: internal list of the interconnect provider nodes
|
||||
* @set: pointer to device specific set operation function
|
||||
* @aggregate: pointer to device specific aggregate operation function
|
||||
* @pre_aggregate: pointer to device specific function that is called
|
||||
* before the aggregation begins (optional)
|
||||
* @xlate: provider-specific callback for mapping nodes from phandle arguments
|
||||
* @dev: the device this interconnect provider belongs to
|
||||
* @users: count of active users
|
||||
|
|
@ -45,8 +47,9 @@ struct icc_provider {
|
|||
struct list_head provider_list;
|
||||
struct list_head nodes;
|
||||
int (*set)(struct icc_node *src, struct icc_node *dst);
|
||||
int (*aggregate)(struct icc_node *node, u32 avg_bw, u32 peak_bw,
|
||||
u32 *agg_avg, u32 *agg_peak);
|
||||
int (*aggregate)(struct icc_node *node, u32 tag, u32 avg_bw,
|
||||
u32 peak_bw, u32 *agg_avg, u32 *agg_peak);
|
||||
void (*pre_aggregate)(struct icc_node *node);
|
||||
struct icc_node* (*xlate)(struct of_phandle_args *spec, void *data);
|
||||
struct device *dev;
|
||||
int users;
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@ struct icc_path *icc_get(struct device *dev, const int src_id,
|
|||
struct icc_path *of_icc_get(struct device *dev, const char *name);
|
||||
void icc_put(struct icc_path *path);
|
||||
int icc_set_bw(struct icc_path *path, u32 avg_bw, u32 peak_bw);
|
||||
void icc_set_tag(struct icc_path *path, u32 tag);
|
||||
|
||||
#else
|
||||
|
||||
|
|
@ -54,6 +55,10 @@ static inline int icc_set_bw(struct icc_path *path, u32 avg_bw, u32 peak_bw)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static inline void icc_set_tag(struct icc_path *path, u32 tag)
|
||||
{
|
||||
}
|
||||
|
||||
#endif /* CONFIG_INTERCONNECT */
|
||||
|
||||
#endif /* __LINUX_INTERCONNECT_H */
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __SOC_QCOM_TCS_H__
|
||||
|
|
@ -53,4 +53,22 @@ struct tcs_request {
|
|||
struct tcs_cmd *cmds;
|
||||
};
|
||||
|
||||
#define BCM_TCS_CMD_COMMIT_SHFT 30
|
||||
#define BCM_TCS_CMD_COMMIT_MASK 0x40000000
|
||||
#define BCM_TCS_CMD_VALID_SHFT 29
|
||||
#define BCM_TCS_CMD_VALID_MASK 0x20000000
|
||||
#define BCM_TCS_CMD_VOTE_X_SHFT 14
|
||||
#define BCM_TCS_CMD_VOTE_MASK 0x3fff
|
||||
#define BCM_TCS_CMD_VOTE_Y_SHFT 0
|
||||
#define BCM_TCS_CMD_VOTE_Y_MASK 0xfffc000
|
||||
|
||||
/* Construct a Bus Clock Manager (BCM) specific TCS command */
|
||||
#define BCM_TCS_CMD(commit, valid, vote_x, vote_y) \
|
||||
(((commit) << BCM_TCS_CMD_COMMIT_SHFT) | \
|
||||
((valid) << BCM_TCS_CMD_VALID_SHFT) | \
|
||||
((cpu_to_le32(vote_x) & \
|
||||
BCM_TCS_CMD_VOTE_MASK) << BCM_TCS_CMD_VOTE_X_SHFT) | \
|
||||
((cpu_to_le32(vote_y) & \
|
||||
BCM_TCS_CMD_VOTE_MASK) << BCM_TCS_CMD_VOTE_Y_SHFT))
|
||||
|
||||
#endif /* __SOC_QCOM_TCS_H__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user