forked from luck/tmp_suning_uos_patched
bnx2x: GPIO accessories
A GPIO is used with the 8726 PHY. Adding the GPIO related functions in this Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Eilon Greenstein
David S. Miller
parent
87942b4678
commit
4acac6a53a
@ -982,7 +982,9 @@ struct bnx2x {
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void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
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void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
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u32 len32);
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int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
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int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
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int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
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static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
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int wait)
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@ -626,8 +626,8 @@ static void bnx2x_int_enable(struct bnx2x *bp)
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if (IS_E1HMF(bp)) {
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val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
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if (bp->port.pmf)
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/* enable nig attention */
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val |= 0x0100;
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/* enable nig and gpio3 attention */
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val |= 0x1100;
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} else
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val = 0xffff;
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@ -1836,6 +1836,36 @@ static void bnx2x_release_phy_lock(struct bnx2x *bp)
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mutex_unlock(&bp->port.phy_mutex);
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}
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int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
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{
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/* The GPIO should be swapped if swap register is set and active */
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int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
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REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
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int gpio_shift = gpio_num +
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(gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
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u32 gpio_mask = (1 << gpio_shift);
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u32 gpio_reg;
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int value;
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if (gpio_num > MISC_REGISTERS_GPIO_3) {
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BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
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return -EINVAL;
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}
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/* read GPIO value */
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gpio_reg = REG_RD(bp, MISC_REG_GPIO);
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/* get the requested pin value */
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if ((gpio_reg & gpio_mask) == gpio_mask)
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value = 1;
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else
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value = 0;
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DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
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return value;
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}
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int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
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{
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/* The GPIO should be swapped if swap register is set and active */
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@ -1889,6 +1919,52 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
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return 0;
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}
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int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
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{
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/* The GPIO should be swapped if swap register is set and active */
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int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
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REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
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int gpio_shift = gpio_num +
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(gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
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u32 gpio_mask = (1 << gpio_shift);
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u32 gpio_reg;
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if (gpio_num > MISC_REGISTERS_GPIO_3) {
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BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
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return -EINVAL;
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}
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bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
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/* read GPIO int */
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gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
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switch (mode) {
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case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
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DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
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"output low\n", gpio_num, gpio_shift);
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/* clear SET and set CLR */
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gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
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gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
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break;
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case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
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DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
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"output high\n", gpio_num, gpio_shift);
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/* clear CLR and set SET */
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gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
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gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
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break;
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default:
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break;
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}
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REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
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bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
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return 0;
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}
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static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
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{
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u32 spio_mask = (1 << spio_num);
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@ -1438,6 +1438,29 @@
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This is the result value of the pin; not the drive value. Writing these
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bits will have not effect. */
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#define MISC_REG_GPIO 0xa490
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/* [RW 8] These bits enable the GPIO_INTs to signals event to the
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IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2]
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p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2;
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[7] p1_gpio_3; */
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#define MISC_REG_GPIO_EVENT_EN 0xa2bc
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/* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a
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'1' to these bit clears the corresponding bit in the #OLD_VALUE register.
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This will acknowledge an interrupt on the falling edge of corresponding
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GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0;
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Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE
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register. This will acknowledge an interrupt on the rising edge of
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corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1;
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OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input
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value. When the ~INT_STATE bit is set; this bit indicates the OLD value
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of the pin such that if ~INT_STATE is set and this bit is '0'; then the
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interrupt is due to a low to high edge. If ~INT_STATE is set and this bit
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is '1'; then the interrupt is due to a high to low edge (reset value 0).
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[7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the
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current GPIO interrupt state for each GPIO pin. This bit is cleared when
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the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is
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set when the GPIO input does not match the current value in #OLD_VALUE
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(reset value 0). */
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#define MISC_REG_GPIO_INT 0xa494
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/* [R 28] this field hold the last information that caused reserved
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attention. bits [19:0] - address; [22:20] function; [23] reserved;
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[27:24] the master that caused the attention - according to the following
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@ -5162,6 +5185,10 @@
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#define MISC_REGISTERS_GPIO_FLOAT_POS 24
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#define MISC_REGISTERS_GPIO_HIGH 1
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#define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
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#define MISC_REGISTERS_GPIO_INT_CLR_POS 24
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#define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0
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#define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1
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#define MISC_REGISTERS_GPIO_INT_SET_POS 16
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#define MISC_REGISTERS_GPIO_LOW 0
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#define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
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#define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
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@ -5220,6 +5247,8 @@
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#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (1<<11)
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#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (1<<13)
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#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (1<<12)
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#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (1<<5)
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#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (1<<9)
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#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (1<<12)
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#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (1<<15)
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#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (1<<14)
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