forked from luck/tmp_suning_uos_patched
chelsio: use C99 style initialization
Convert some initialized structures to C99 style. Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Stephen Hemminger
Jeff Garzik
parent
4d2b8f66b8
commit
4c247db114
@ -322,9 +322,9 @@ static int mi1_mdio_write(adapter_t *adapter, int phy_addr, int mmd_addr,
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#if defined(CONFIG_CHELSIO_T1_1G) || defined(CONFIG_CHELSIO_T1_COUGAR)
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static struct mdio_ops mi1_mdio_ops = {
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mi1_mdio_init,
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mi1_mdio_read,
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mi1_mdio_write
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.init = mi1_mdio_init,
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.read = mi1_mdio_read,
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.write = mi1_mdio_write
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};
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#endif
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@ -378,9 +378,9 @@ static int mi1_mdio_ext_write(adapter_t *adapter, int phy_addr, int mmd_addr,
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}
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static struct mdio_ops mi1_mdio_ext_ops = {
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mi1_mdio_init,
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mi1_mdio_ext_read,
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mi1_mdio_ext_write
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.init = mi1_mdio_init,
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.read = mi1_mdio_ext_read,
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.write = mi1_mdio_ext_write
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};
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enum {
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@ -392,63 +392,136 @@ enum {
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CH_BRD_N204_4CU,
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};
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static struct board_info t1_board[] = {
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static const struct board_info t1_board[] = {
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{
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.board = CHBT_BOARD_CHT110,
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.port_number = 1,
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.caps = SUPPORTED_10000baseT_Full,
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.chip_term = CHBT_TERM_T1,
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.chip_mac = CHBT_MAC_PM3393,
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.chip_phy = CHBT_PHY_MY3126,
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.clock_core = 125000000,
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.clock_mc3 = 150000000,
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.clock_mc4 = 125000000,
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.espi_nports = 1,
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.clock_elmer0 = 44,
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.mdio_mdien = 1,
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.mdio_mdiinv = 1,
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.mdio_mdc = 1,
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.mdio_phybaseaddr = 1,
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.gmac = &t1_pm3393_ops,
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.gphy = &t1_my3126_ops,
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.mdio_ops = &mi1_mdio_ext_ops,
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.desc = "Chelsio T110 1x10GBase-CX4 TOE",
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},
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{ CHBT_BOARD_CHT110, 1/*ports#*/,
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SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T1,
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CHBT_MAC_PM3393, CHBT_PHY_MY3126,
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125000000/*clk-core*/, 150000000/*clk-mc3*/, 125000000/*clk-mc4*/,
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1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 1/*mdien*/,
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1/*mdiinv*/, 1/*mdc*/, 1/*phybaseaddr*/, &t1_pm3393_ops,
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&t1_my3126_ops, &mi1_mdio_ext_ops,
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"Chelsio T110 1x10GBase-CX4 TOE" },
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{
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.board = CHBT_BOARD_N110,
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.port_number = 1,
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.caps = SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE,
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.chip_term = CHBT_TERM_T1,
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.chip_mac = CHBT_MAC_PM3393,
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.chip_phy = CHBT_PHY_88X2010,
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.clock_core = 125000000,
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.espi_nports = 1,
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.clock_elmer0 = 44,
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.mdio_mdien = 0,
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.mdio_mdiinv = 0,
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.mdio_mdc = 1,
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.mdio_phybaseaddr = 0,
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.gmac = &t1_pm3393_ops,
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.gphy = &t1_mv88x201x_ops,
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.mdio_ops = &mi1_mdio_ext_ops,
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.desc = "Chelsio N110 1x10GBaseX NIC",
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},
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{ CHBT_BOARD_N110, 1/*ports#*/,
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SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T1,
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CHBT_MAC_PM3393, CHBT_PHY_88X2010,
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125000000/*clk-core*/, 0/*clk-mc3*/, 0/*clk-mc4*/,
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1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
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0/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops,
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&t1_mv88x201x_ops, &mi1_mdio_ext_ops,
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"Chelsio N110 1x10GBaseX NIC" },
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{
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.board = CHBT_BOARD_N210,
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.port_number = 1,
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.caps = SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE,
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.chip_term = CHBT_TERM_T2,
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.chip_mac = CHBT_MAC_PM3393,
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.chip_phy = CHBT_PHY_88X2010,
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.clock_core = 125000000,
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.espi_nports = 1,
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.clock_elmer0 = 44,
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.mdio_mdien = 0,
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.mdio_mdiinv = 0,
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.mdio_mdc = 1,
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.mdio_phybaseaddr = 0,
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.gmac = &t1_pm3393_ops,
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.gphy = &t1_mv88x201x_ops,
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.mdio_ops = &mi1_mdio_ext_ops,
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.desc = "Chelsio N210 1x10GBaseX NIC",
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},
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{ CHBT_BOARD_N210, 1/*ports#*/,
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SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T2,
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CHBT_MAC_PM3393, CHBT_PHY_88X2010,
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125000000/*clk-core*/, 0/*clk-mc3*/, 0/*clk-mc4*/,
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1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
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0/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops,
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&t1_mv88x201x_ops, &mi1_mdio_ext_ops,
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"Chelsio N210 1x10GBaseX NIC" },
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{
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.board = CHBT_BOARD_CHT210,
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.port_number = 1,
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.caps = SUPPORTED_10000baseT_Full,
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.chip_term = CHBT_TERM_T2,
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.chip_mac = CHBT_MAC_PM3393,
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.chip_phy = CHBT_PHY_88X2010,
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.clock_core = 125000000,
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.clock_mc3 = 133000000,
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.clock_mc4 = 125000000,
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.espi_nports = 1,
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.clock_elmer0 = 44,
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.mdio_mdien = 0,
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.mdio_mdiinv = 0,
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.mdio_mdc = 1,
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.mdio_phybaseaddr = 0,
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.gmac = &t1_pm3393_ops,
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.gphy = &t1_mv88x201x_ops,
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.mdio_ops = &mi1_mdio_ext_ops,
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.desc = "Chelsio T210 1x10GBaseX TOE",
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},
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{ CHBT_BOARD_CHT210, 1/*ports#*/,
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SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T2,
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CHBT_MAC_PM3393, CHBT_PHY_88X2010,
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125000000/*clk-core*/, 133000000/*clk-mc3*/, 125000000/*clk-mc4*/,
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1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
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0/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops,
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&t1_mv88x201x_ops, &mi1_mdio_ext_ops,
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"Chelsio T210 1x10GBaseX TOE" },
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{ CHBT_BOARD_CHT210, 1/*ports#*/,
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SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T2,
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CHBT_MAC_PM3393, CHBT_PHY_MY3126,
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125000000/*clk-core*/, 133000000/*clk-mc3*/, 125000000/*clk-mc4*/,
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1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 1/*mdien*/,
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1/*mdiinv*/, 1/*mdc*/, 1/*phybaseaddr*/, &t1_pm3393_ops,
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&t1_my3126_ops, &mi1_mdio_ext_ops,
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"Chelsio T210 1x10GBase-CX4 TOE" },
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{
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.board = CHBT_BOARD_CHT210,
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.port_number = 1,
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.caps = SUPPORTED_10000baseT_Full,
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.chip_term = CHBT_TERM_T2,
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.chip_mac = CHBT_MAC_PM3393,
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.chip_phy = CHBT_PHY_MY3126,
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.clock_core = 125000000,
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.clock_mc3 = 133000000,
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.clock_mc4 = 125000000,
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.espi_nports = 1,
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.clock_elmer0 = 44,
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.mdio_mdien = 1,
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.mdio_mdiinv = 1,
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.mdio_mdc = 1,
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.mdio_phybaseaddr = 1,
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.gmac = &t1_pm3393_ops,
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.gphy = &t1_my3126_ops,
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.mdio_ops = &mi1_mdio_ext_ops,
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.desc = "Chelsio T210 1x10GBase-CX4 TOE",
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},
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#ifdef CONFIG_CHELSIO_T1_1G
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{ CHBT_BOARD_CHN204, 4/*ports#*/,
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SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half |
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SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
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SUPPORTED_PAUSE | SUPPORTED_TP /*caps*/, CHBT_TERM_T2, CHBT_MAC_VSC7321, CHBT_PHY_88E1111,
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100000000/*clk-core*/, 0/*clk-mc3*/, 0/*clk-mc4*/,
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4/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
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0/*mdiinv*/, 1/*mdc*/, 4/*phybaseaddr*/, &t1_vsc7326_ops,
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&t1_mv88e1xxx_ops, &mi1_mdio_ops,
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"Chelsio N204 4x100/1000BaseT NIC" },
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{
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.board = CHBT_BOARD_CHN204,
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.port_number = 4,
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.caps = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full
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| SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full
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| SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
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SUPPORTED_PAUSE | SUPPORTED_TP,
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.chip_term = CHBT_TERM_T2,
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.chip_mac = CHBT_MAC_VSC7321,
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.chip_phy = CHBT_PHY_88E1111,
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.clock_core = 100000000,
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.espi_nports = 4,
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.clock_elmer0 = 44,
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.mdio_mdien = 0,
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.mdio_mdiinv = 0,
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.mdio_mdc = 0,
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.mdio_phybaseaddr = 4,
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.gmac = &t1_vsc7326_ops,
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.gphy = &t1_mv88e1xxx_ops,
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.mdio_ops = &mi1_mdio_ops,
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.desc = "Chelsio N204 4x100/1000BaseT NIC",
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},
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#endif
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};
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