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pci-v4.9-fixes-4

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-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJYQKe0AAoJEFmIoMA60/r8dmsQAJ1BjfcgWunT8cyBjh9DW8MT
 mFj4w4qEtN8JthecXYKDHYY1zTRocuuKYQTCdX6qKnnx37amJwfiEtPsLqzoio3U
 HqIx0Nyereh6ir3VHJgITa2C0317pw6ti2rEZS+oMfQyWUDWVXMKOo3nsCKYtqLJ
 fO0K1ubYSUwNr1ph3rxTbJaycRUZsXK1PAdaROVeDjiw6IPgSNd9eboQCQAg3WQm
 JFsENhhCDM7qlFpwgbjtjv2IkzK0zpxs6vkVKRUJ1x8D2OAfg0j+rxYEVaOU23bO
 isj7rnbM1fFuC3WrAB1uexPfISLuzqUSIceB46EItoTJ7x3wmQGs4BIIt9LlmUte
 Z6RNAMbUx+K/5p2+xCVJAnbhfnCQv/vLkYEKpr2uPx43PywALYJq/8I4p/qh0zIW
 562ulb7HUqh8jNMvFj/7kqCijnkFHw0iddL0zwC6VD5/lYiTeYN19/T00gUGLtB6
 YWunN1G/fl/SdtI29oo8e+xVKuWraAsyKVX7LZIl2XaZhVBTy9vTC2wC/hdZqiMg
 yXK4/lE+Fr0tnHt8vVRgEicTHTmlQYQnRKNcy9PyDQWyYndg4ExacmsafQ61u0EE
 bUKoPPT7zJT/TVDp54cWk4t/AHc4TONNONNUH2xZKAMElsAiQrHd4GwFHUAQgz/C
 MiwbEXvfYTBcPCRP4cqD
 =DhJD
 -----END PGP SIGNATURE-----

Merge tag 'pci-v4.9-fixes-4' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI fixes from Bjorn Helgaas:
 "PCI fixes:

   - Fix Read Completion Boundary setting, which fixes a boot failure on
     IBM x3850 with Mellanox MT27500 ConnectX-3

   - Update some MAINTAINERS entries and email addresses"

* tag 'pci-v4.9-fixes-4' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
  PCI: Set Read Completion Boundary to 128 iff Root Port supports it (_HPX)
  PCI: Export pcie_find_root_port
  PCI: designware-plat: Update author email
  PCI: designware: Change maintainer to Joao Pinto
  MAINTAINERS: Add devicetree binding to PCI i.MX6 entry
  MAINTAINERS: Update Richard Zhu's email address
This commit is contained in:
Linus Torvalds 2016-12-01 16:44:42 -08:00
commit 4db5e636dd
5 changed files with 46 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
MAINTAINERS
View File

@ -9257,11 +9257,12 @@ S: Maintained
F: drivers/pci/host/*layerscape*
PCI DRIVER FOR IMX6
M: Richard Zhu <Richard.Zhu@freescale.com>
M: Richard Zhu <hongxing.zhu@nxp.com>
M: Lucas Stach <l.stach@pengutronix.de>
L: linux-pci@vger.kernel.org
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
F: drivers/pci/host/*imx6*
PCI DRIVER FOR TI KEYSTONE
@ -9320,17 +9321,11 @@ F: drivers/pci/host/pci-exynos.c
PCI DRIVER FOR SYNOPSIS DESIGNWARE
M: Jingoo Han <jingoohan1@gmail.com>
M: Pratyush Anand <pratyush.anand@gmail.com>
L: linux-pci@vger.kernel.org
S: Maintained
F: drivers/pci/host/*designware*
PCI DRIVER FOR SYNOPSYS PROTOTYPING DEVICE
M: Jose Abreu <Jose.Abreu@synopsys.com>
M: Joao Pinto <Joao.Pinto@synopsys.com>
L: linux-pci@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/pci/designware-pcie.txt
F: drivers/pci/host/pcie-designware-plat.c
F: drivers/pci/host/*designware*
PCI DRIVER FOR GENERIC OF HOSTS
M: Will Deacon <will.deacon@arm.com>

2
drivers/pci/host/pcie-designware-plat.c
View File

@ -3,7 +3,7 @@
*
* Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
*
* Authors: Joao Pinto <jpmpinto@gmail.com>
* Authors: Joao Pinto <Joao.Pinto@synopsys.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

14
drivers/pci/pcie/aer/aer_inject.c
View File

@ -307,20 +307,6 @@ static int pci_bus_set_aer_ops(struct pci_bus *bus)
return 0;
}
static struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
{
while (1) {
if (!pci_is_pcie(dev))
break;
if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
return dev;
if (!dev->bus->self)
break;
dev = dev->bus->self;
}
return NULL;
}
static int find_aer_device_iter(struct device *device, void *data)
{
struct pcie_device **result = data;

28
drivers/pci/probe.c
View File

@ -1439,6 +1439,21 @@ static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
dev_warn(&dev->dev, "PCI-X settings not supported\n");
}
static bool pcie_root_rcb_set(struct pci_dev *dev)
{
struct pci_dev *rp = pcie_find_root_port(dev);
u16 lnkctl;
if (!rp)
return false;
pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl);
if (lnkctl & PCI_EXP_LNKCTL_RCB)
return true;
return false;
}
static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
{
int pos;
@ -1468,9 +1483,20 @@ static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
/* Initialize Link Control Register */
if (pcie_cap_has_lnkctl(dev))
if (pcie_cap_has_lnkctl(dev)) {
/*
* If the Root Port supports Read Completion Boundary of
* 128, set RCB to 128. Otherwise, clear it.
*/
hpp->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB;
hpp->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB;
if (pcie_root_rcb_set(dev))
hpp->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB;
pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
}
/* Find Advanced Error Reporting Enhanced Capability */
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);

14
include/linux/pci.h
View File

@ -1928,6 +1928,20 @@ static inline int pci_pcie_type(const struct pci_dev *dev)
return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
}
static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
{
while (1) {
if (!pci_is_pcie(dev))
break;
if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
return dev;
if (!dev->bus->self)
break;
dev = dev->bus->self;
}
return NULL;
}
void pci_request_acs(void);
bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
bool pci_acs_path_enabled(struct pci_dev *start,