forked from luck/tmp_suning_uos_patched
x86: lindent mpparse_32.c
Signed-off-by: Alexey Starikovskiy <astarikovskiy@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Alexey Starikovskiy
Ingo Molnar
parent
31d2092eb0
commit
4ef81297f7
@ -41,10 +41,10 @@ int smp_found_config;
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* MP-table.
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*/
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#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
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int mp_bus_id_to_type [MAX_MP_BUSSES];
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int mp_bus_id_to_type[MAX_MP_BUSSES];
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#endif
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DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
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int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
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int mp_bus_id_to_pci_bus[MAX_MP_BUSSES] = {[0 ... MAX_MP_BUSSES - 1] = -1 };
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static int mp_current_pci_id;
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int pic_mode;
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@ -53,7 +53,6 @@ int pic_mode;
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* Intel MP BIOS table parsing routines:
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*/
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/*
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* Checksum an MP configuration block.
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*/
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@ -75,8 +74,9 @@ static int __init mpf_checksum(unsigned char *mp, int len)
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* doing this ....
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*/
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static int mpc_record;
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static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __cpuinitdata;
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static int mpc_record;
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static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY]
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__cpuinitdata;
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#endif
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static void __cpuinit MP_processor_info(struct mpc_config_processor *m)
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@ -87,66 +87,63 @@ static void __cpuinit MP_processor_info(struct mpc_config_processor *m)
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disabled_cpus++;
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return;
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}
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#ifdef CONFIG_X86_NUMAQ
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apicid = mpc_apic_id(m, translation_table[mpc_record]);
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#else
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Dprintk("Processor #%d %u:%u APIC version %d\n",
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m->mpc_apicid,
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(m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
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(m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
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m->mpc_apicver);
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(m->mpc_cpufeature & CPU_MODEL_MASK) >> 4, m->mpc_apicver);
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apicid = m->mpc_apicid;
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#endif
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if (m->mpc_featureflag&(1<<0))
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if (m->mpc_featureflag & (1 << 0))
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Dprintk(" Floating point unit present.\n");
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if (m->mpc_featureflag&(1<<7))
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if (m->mpc_featureflag & (1 << 7))
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Dprintk(" Machine Exception supported.\n");
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if (m->mpc_featureflag&(1<<8))
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if (m->mpc_featureflag & (1 << 8))
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Dprintk(" 64 bit compare & exchange supported.\n");
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if (m->mpc_featureflag&(1<<9))
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if (m->mpc_featureflag & (1 << 9))
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Dprintk(" Internal APIC present.\n");
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if (m->mpc_featureflag&(1<<11))
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if (m->mpc_featureflag & (1 << 11))
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Dprintk(" SEP present.\n");
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if (m->mpc_featureflag&(1<<12))
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if (m->mpc_featureflag & (1 << 12))
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Dprintk(" MTRR present.\n");
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if (m->mpc_featureflag&(1<<13))
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if (m->mpc_featureflag & (1 << 13))
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Dprintk(" PGE present.\n");
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if (m->mpc_featureflag&(1<<14))
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if (m->mpc_featureflag & (1 << 14))
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Dprintk(" MCA present.\n");
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if (m->mpc_featureflag&(1<<15))
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if (m->mpc_featureflag & (1 << 15))
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Dprintk(" CMOV present.\n");
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if (m->mpc_featureflag&(1<<16))
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if (m->mpc_featureflag & (1 << 16))
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Dprintk(" PAT present.\n");
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if (m->mpc_featureflag&(1<<17))
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if (m->mpc_featureflag & (1 << 17))
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Dprintk(" PSE present.\n");
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if (m->mpc_featureflag&(1<<18))
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if (m->mpc_featureflag & (1 << 18))
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Dprintk(" PSN present.\n");
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if (m->mpc_featureflag&(1<<19))
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if (m->mpc_featureflag & (1 << 19))
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Dprintk(" Cache Line Flush Instruction present.\n");
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/* 20 Reserved */
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if (m->mpc_featureflag&(1<<21))
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if (m->mpc_featureflag & (1 << 21))
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Dprintk(" Debug Trace and EMON Store present.\n");
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if (m->mpc_featureflag&(1<<22))
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if (m->mpc_featureflag & (1 << 22))
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Dprintk(" ACPI Thermal Throttle Registers present.\n");
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if (m->mpc_featureflag&(1<<23))
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if (m->mpc_featureflag & (1 << 23))
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Dprintk(" MMX present.\n");
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if (m->mpc_featureflag&(1<<24))
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if (m->mpc_featureflag & (1 << 24))
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Dprintk(" FXSR present.\n");
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if (m->mpc_featureflag&(1<<25))
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if (m->mpc_featureflag & (1 << 25))
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Dprintk(" XMM present.\n");
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if (m->mpc_featureflag&(1<<26))
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if (m->mpc_featureflag & (1 << 26))
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Dprintk(" Willamette New Instructions present.\n");
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if (m->mpc_featureflag&(1<<27))
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if (m->mpc_featureflag & (1 << 27))
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Dprintk(" Self Snoop present.\n");
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if (m->mpc_featureflag&(1<<28))
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if (m->mpc_featureflag & (1 << 28))
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Dprintk(" HT present.\n");
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if (m->mpc_featureflag&(1<<29))
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if (m->mpc_featureflag & (1 << 29))
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Dprintk(" Thermal Monitor present.\n");
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/* 30, 31 Reserved */
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if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
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Dprintk(" Bootup CPU\n");
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boot_cpu_physical_apicid = m->mpc_apicid;
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@ -155,7 +152,7 @@ static void __cpuinit MP_processor_info(struct mpc_config_processor *m)
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generic_processor_info(apicid, m->mpc_apicver);
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}
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static void __init MP_bus_info (struct mpc_config_bus *m)
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static void __init MP_bus_info(struct mpc_config_bus *m)
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{
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char str[7];
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@ -171,14 +168,14 @@ static void __init MP_bus_info (struct mpc_config_bus *m)
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#if MAX_MP_BUSSES < 256
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if (m->mpc_busid >= MAX_MP_BUSSES) {
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printk(KERN_WARNING "MP table busid value (%d) for bustype %s "
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" is too large, max. supported is %d\n",
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m->mpc_busid, str, MAX_MP_BUSSES - 1);
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" is too large, max. supported is %d\n",
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m->mpc_busid, str, MAX_MP_BUSSES - 1);
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return;
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}
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#endif
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set_bit(m->mpc_busid, mp_bus_not_pci);
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if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
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if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI) - 1) == 0) {
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#ifdef CONFIG_X86_NUMAQ
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mpc_oem_pci_bus(m, translation_table[mpc_record]);
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#endif
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@ -187,11 +184,11 @@ static void __init MP_bus_info (struct mpc_config_bus *m)
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mp_current_pci_id++;
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#if defined(CONFIG_EISA) || defined (CONFIG_MCA)
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mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
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} else if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
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} else if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA) - 1) == 0) {
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mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
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} else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
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} else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA) - 1) == 0) {
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mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
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} else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
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} else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA) - 1) == 0) {
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mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
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} else {
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printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
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@ -216,13 +213,13 @@ static int bad_ioapic(unsigned long address)
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return 0;
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}
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static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
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static void __init MP_ioapic_info(struct mpc_config_ioapic *m)
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{
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if (!(m->mpc_flags & MPC_APIC_USABLE))
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return;
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printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n",
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m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
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m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
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if (bad_ioapic(m->mpc_apicaddr))
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return;
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@ -231,38 +228,41 @@ static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
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nr_ioapics++;
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}
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static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
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static void __init MP_intsrc_info(struct mpc_config_intsrc *m)
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{
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mp_irqs [mp_irq_entries] = *m;
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mp_irqs[mp_irq_entries] = *m;
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Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
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" IRQ %02x, APIC ID %x, APIC INT %02x\n",
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m->mpc_irqtype, m->mpc_irqflag & 3,
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(m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
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m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
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m->mpc_irqtype, m->mpc_irqflag & 3,
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(m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
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m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
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if (++mp_irq_entries == MAX_IRQ_SOURCES)
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panic("Max # of irq sources exceeded!!\n");
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}
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#endif
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static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
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static void __init MP_lintsrc_info(struct mpc_config_lintsrc *m)
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{
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Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
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" IRQ %02x, APIC ID %x, APIC LINT %02x\n",
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m->mpc_irqtype, m->mpc_irqflag & 3,
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(m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
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m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
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m->mpc_irqtype, m->mpc_irqflag & 3,
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(m->mpc_irqflag >> 2) & 3, m->mpc_srcbusid,
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m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
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}
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#ifdef CONFIG_X86_NUMAQ
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static void __init MP_translation_info (struct mpc_config_translation *m)
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static void __init MP_translation_info(struct mpc_config_translation *m)
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{
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printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
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printk(KERN_INFO
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"Translation: record %d, type %d, quad %d, global %d, local %d\n",
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mpc_record, m->trans_type, m->trans_quad, m->trans_global,
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m->trans_local);
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if (mpc_record >= MAX_MPC_ENTRY)
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if (mpc_record >= MAX_MPC_ENTRY)
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printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
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else
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translation_table[mpc_record] = m; /* stash this for later */
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translation_table[mpc_record] = m; /* stash this for later */
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if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
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node_set_online(m->trans_quad);
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}
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@ -271,59 +271,59 @@ static void __init MP_translation_info (struct mpc_config_translation *m)
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* Read/parse the MPC oem tables
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*/
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static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
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unsigned short oemsize)
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static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable,
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unsigned short oemsize)
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{
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int count = sizeof (*oemtable); /* the header size */
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unsigned char *oemptr = ((unsigned char *)oemtable)+count;
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int count = sizeof(*oemtable); /* the header size */
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unsigned char *oemptr = ((unsigned char *)oemtable) + count;
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mpc_record = 0;
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printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
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if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
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{
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printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
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oemtable->oem_signature[0],
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oemtable->oem_signature[1],
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oemtable->oem_signature[2],
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oemtable->oem_signature[3]);
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printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n",
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oemtable);
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if (memcmp(oemtable->oem_signature, MPC_OEM_SIGNATURE, 4)) {
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printk(KERN_WARNING
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"SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
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oemtable->oem_signature[0], oemtable->oem_signature[1],
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oemtable->oem_signature[2], oemtable->oem_signature[3]);
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return;
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}
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if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
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{
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if (mpf_checksum((unsigned char *)oemtable, oemtable->oem_length)) {
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printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
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return;
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}
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while (count < oemtable->oem_length) {
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switch (*oemptr) {
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case MP_TRANSLATION:
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case MP_TRANSLATION:
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{
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struct mpc_config_translation *m=
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(struct mpc_config_translation *)oemptr;
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struct mpc_config_translation *m =
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(struct mpc_config_translation *)oemptr;
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MP_translation_info(m);
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oemptr += sizeof(*m);
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count += sizeof(*m);
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++mpc_record;
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break;
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}
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default:
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default:
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{
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printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
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printk(KERN_WARNING
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"Unrecognised OEM table entry type! - %d\n",
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(int)*oemptr);
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return;
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}
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}
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}
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}
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}
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static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
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char *productid)
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char *productid)
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{
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if (strncmp(oem, "IBM NUMA", 8))
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printk("Warning! May not be a NUMA-Q system!\n");
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if (mpc->mpc_oemptr)
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smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
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mpc->mpc_oemsize);
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smp_read_mpc_oem((struct mp_config_oemtable *)mpc->mpc_oemptr,
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mpc->mpc_oemsize);
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}
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#endif /* CONFIG_X86_NUMAQ */
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#endif /* CONFIG_X86_NUMAQ */
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/*
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* Read/parse the MPC
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@ -333,34 +333,34 @@ static int __init smp_read_mpc(struct mp_config_table *mpc)
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{
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char str[16];
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char oem[10];
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int count=sizeof(*mpc);
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unsigned char *mpt=((unsigned char *)mpc)+count;
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int count = sizeof(*mpc);
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unsigned char *mpt = ((unsigned char *)mpc) + count;
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if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
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if (memcmp(mpc->mpc_signature, MPC_SIGNATURE, 4)) {
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printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
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*(u32 *)mpc->mpc_signature);
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*(u32 *) mpc->mpc_signature);
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return 0;
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}
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if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
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if (mpf_checksum((unsigned char *)mpc, mpc->mpc_length)) {
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printk(KERN_ERR "SMP mptable: checksum error!\n");
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return 0;
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}
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if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
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if (mpc->mpc_spec != 0x01 && mpc->mpc_spec != 0x04) {
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printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
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mpc->mpc_spec);
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mpc->mpc_spec);
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return 0;
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}
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if (!mpc->mpc_lapic) {
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printk(KERN_ERR "SMP mptable: null local APIC address!\n");
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return 0;
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}
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memcpy(oem,mpc->mpc_oem,8);
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oem[8]=0;
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printk(KERN_INFO "OEM ID: %s ",oem);
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memcpy(oem, mpc->mpc_oem, 8);
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oem[8] = 0;
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printk(KERN_INFO "OEM ID: %s ", oem);
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memcpy(str,mpc->mpc_productid,12);
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str[12]=0;
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printk("Product ID: %s ",str);
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memcpy(str, mpc->mpc_productid, 12);
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str[12] = 0;
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printk("Product ID: %s ", str);
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mps_oem_check(mpc, oem, str);
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@ -374,17 +374,17 @@ static int __init smp_read_mpc(struct mp_config_table *mpc)
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mp_lapic_addr = mpc->mpc_lapic;
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/*
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* Now process the configuration blocks.
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* Now process the configuration blocks.
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||||
*/
|
||||
#ifdef CONFIG_X86_NUMAQ
|
||||
mpc_record = 0;
|
||||
#endif
|
||||
while (count < mpc->mpc_length) {
|
||||
switch(*mpt) {
|
||||
case MP_PROCESSOR:
|
||||
switch (*mpt) {
|
||||
case MP_PROCESSOR:
|
||||
{
|
||||
struct mpc_config_processor *m=
|
||||
(struct mpc_config_processor *)mpt;
|
||||
struct mpc_config_processor *m =
|
||||
(struct mpc_config_processor *)mpt;
|
||||
/* ACPI may have already provided this data */
|
||||
if (!acpi_lapic)
|
||||
MP_processor_info(m);
|
||||
@ -392,48 +392,48 @@ static int __init smp_read_mpc(struct mp_config_table *mpc)
|
||||
count += sizeof(*m);
|
||||
break;
|
||||
}
|
||||
case MP_BUS:
|
||||
case MP_BUS:
|
||||
{
|
||||
struct mpc_config_bus *m=
|
||||
(struct mpc_config_bus *)mpt;
|
||||
struct mpc_config_bus *m =
|
||||
(struct mpc_config_bus *)mpt;
|
||||
MP_bus_info(m);
|
||||
mpt += sizeof(*m);
|
||||
count += sizeof(*m);
|
||||
break;
|
||||
}
|
||||
case MP_IOAPIC:
|
||||
case MP_IOAPIC:
|
||||
{
|
||||
#ifdef CONFIG_X86_IO_APIC
|
||||
struct mpc_config_ioapic *m=
|
||||
(struct mpc_config_ioapic *)mpt;
|
||||
struct mpc_config_ioapic *m =
|
||||
(struct mpc_config_ioapic *)mpt;
|
||||
MP_ioapic_info(m);
|
||||
#endif
|
||||
mpt+=sizeof(struct mpc_config_ioapic);
|
||||
count+=sizeof(struct mpc_config_ioapic);
|
||||
mpt += sizeof(struct mpc_config_ioapic);
|
||||
count += sizeof(struct mpc_config_ioapic);
|
||||
break;
|
||||
}
|
||||
case MP_INTSRC:
|
||||
case MP_INTSRC:
|
||||
{
|
||||
#ifdef CONFIG_X86_IO_APIC
|
||||
struct mpc_config_intsrc *m=
|
||||
(struct mpc_config_intsrc *)mpt;
|
||||
struct mpc_config_intsrc *m =
|
||||
(struct mpc_config_intsrc *)mpt;
|
||||
|
||||
MP_intsrc_info(m);
|
||||
#endif
|
||||
mpt+=sizeof(struct mpc_config_intsrc);
|
||||
count+=sizeof(struct mpc_config_intsrc);
|
||||
mpt += sizeof(struct mpc_config_intsrc);
|
||||
count += sizeof(struct mpc_config_intsrc);
|
||||
break;
|
||||
}
|
||||
case MP_LINTSRC:
|
||||
case MP_LINTSRC:
|
||||
{
|
||||
struct mpc_config_lintsrc *m=
|
||||
(struct mpc_config_lintsrc *)mpt;
|
||||
struct mpc_config_lintsrc *m =
|
||||
(struct mpc_config_lintsrc *)mpt;
|
||||
MP_lintsrc_info(m);
|
||||
mpt+=sizeof(*m);
|
||||
count+=sizeof(*m);
|
||||
mpt += sizeof(*m);
|
||||
count += sizeof(*m);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
default:
|
||||
{
|
||||
count = mpc->mpc_length;
|
||||
break;
|
||||
@ -466,7 +466,7 @@ static void __init construct_default_ioirq_mptable(int mpc_default_type)
|
||||
int ELCR_fallback = 0;
|
||||
|
||||
intsrc.mpc_type = MP_INTSRC;
|
||||
intsrc.mpc_irqflag = 0; /* conforming */
|
||||
intsrc.mpc_irqflag = 0; /* conforming */
|
||||
intsrc.mpc_srcbus = 0;
|
||||
intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
|
||||
|
||||
@ -481,12 +481,16 @@ static void __init construct_default_ioirq_mptable(int mpc_default_type)
|
||||
* If it does, we assume it's valid.
|
||||
*/
|
||||
if (mpc_default_type == 5) {
|
||||
printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
|
||||
printk(KERN_INFO
|
||||
"ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
|
||||
|
||||
if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
|
||||
printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
|
||||
if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2)
|
||||
|| ELCR_trigger(13))
|
||||
printk(KERN_WARNING
|
||||
"ELCR contains invalid data... not using ELCR\n");
|
||||
else {
|
||||
printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
|
||||
printk(KERN_INFO
|
||||
"Using ELCR to identify PCI interrupts\n");
|
||||
ELCR_fallback = 1;
|
||||
}
|
||||
}
|
||||
@ -515,13 +519,13 @@ static void __init construct_default_ioirq_mptable(int mpc_default_type)
|
||||
}
|
||||
|
||||
intsrc.mpc_srcbusirq = i;
|
||||
intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
|
||||
intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
|
||||
MP_intsrc_info(&intsrc);
|
||||
}
|
||||
|
||||
intsrc.mpc_irqtype = mp_ExtINT;
|
||||
intsrc.mpc_srcbusirq = 0;
|
||||
intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
|
||||
intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
|
||||
MP_intsrc_info(&intsrc);
|
||||
}
|
||||
|
||||
@ -551,8 +555,7 @@ static inline void __init construct_default_ISA_mptable(int mpc_default_type)
|
||||
processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
|
||||
processor.mpc_cpuflag = CPU_ENABLED;
|
||||
processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
|
||||
(boot_cpu_data.x86_model << 4) |
|
||||
boot_cpu_data.x86_mask;
|
||||
(boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
|
||||
processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
|
||||
processor.mpc_reserved[0] = 0;
|
||||
processor.mpc_reserved[1] = 0;
|
||||
@ -564,23 +567,23 @@ static inline void __init construct_default_ISA_mptable(int mpc_default_type)
|
||||
bus.mpc_type = MP_BUS;
|
||||
bus.mpc_busid = 0;
|
||||
switch (mpc_default_type) {
|
||||
default:
|
||||
printk("???\n");
|
||||
printk(KERN_ERR "Unknown standard configuration %d\n",
|
||||
mpc_default_type);
|
||||
/* fall through */
|
||||
case 1:
|
||||
case 5:
|
||||
memcpy(bus.mpc_bustype, "ISA ", 6);
|
||||
break;
|
||||
case 2:
|
||||
case 6:
|
||||
case 3:
|
||||
memcpy(bus.mpc_bustype, "EISA ", 6);
|
||||
break;
|
||||
case 4:
|
||||
case 7:
|
||||
memcpy(bus.mpc_bustype, "MCA ", 6);
|
||||
default:
|
||||
printk("???\n");
|
||||
printk(KERN_ERR "Unknown standard configuration %d\n",
|
||||
mpc_default_type);
|
||||
/* fall through */
|
||||
case 1:
|
||||
case 5:
|
||||
memcpy(bus.mpc_bustype, "ISA ", 6);
|
||||
break;
|
||||
case 2:
|
||||
case 6:
|
||||
case 3:
|
||||
memcpy(bus.mpc_bustype, "EISA ", 6);
|
||||
break;
|
||||
case 4:
|
||||
case 7:
|
||||
memcpy(bus.mpc_bustype, "MCA ", 6);
|
||||
}
|
||||
MP_bus_info(&bus);
|
||||
if (mpc_default_type > 4) {
|
||||
@ -603,7 +606,7 @@ static inline void __init construct_default_ISA_mptable(int mpc_default_type)
|
||||
construct_default_ioirq_mptable(mpc_default_type);
|
||||
#endif
|
||||
lintsrc.mpc_type = MP_LINTSRC;
|
||||
lintsrc.mpc_irqflag = 0; /* conforming */
|
||||
lintsrc.mpc_irqflag = 0; /* conforming */
|
||||
lintsrc.mpc_srcbusid = 0;
|
||||
lintsrc.mpc_srcbusirq = 0;
|
||||
lintsrc.mpc_destapic = MP_APIC_ALL;
|
||||
@ -619,23 +622,25 @@ static struct intel_mp_floating *mpf_found;
|
||||
/*
|
||||
* Scan the memory blocks for an SMP configuration block.
|
||||
*/
|
||||
void __init get_smp_config (void)
|
||||
void __init get_smp_config(void)
|
||||
{
|
||||
struct intel_mp_floating *mpf = mpf_found;
|
||||
|
||||
/*
|
||||
* ACPI supports both logical (e.g. Hyper-Threading) and physical
|
||||
* ACPI supports both logical (e.g. Hyper-Threading) and physical
|
||||
* processors, where MPS only supports physical.
|
||||
*/
|
||||
if (acpi_lapic && acpi_ioapic) {
|
||||
printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
|
||||
printk(KERN_INFO
|
||||
"Using ACPI (MADT) for SMP configuration information\n");
|
||||
return;
|
||||
}
|
||||
else if (acpi_lapic)
|
||||
printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
|
||||
} else if (acpi_lapic)
|
||||
printk(KERN_INFO
|
||||
"Using ACPI for processor (LAPIC) configuration information\n");
|
||||
|
||||
printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
|
||||
if (mpf->mpf_feature2 & (1<<7)) {
|
||||
printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n",
|
||||
mpf->mpf_specification);
|
||||
if (mpf->mpf_feature2 & (1 << 7)) {
|
||||
printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
|
||||
pic_mode = 1;
|
||||
} else {
|
||||
@ -648,7 +653,8 @@ void __init get_smp_config (void)
|
||||
*/
|
||||
if (mpf->mpf_feature1 != 0) {
|
||||
|
||||
printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
|
||||
printk(KERN_INFO "Default MP configuration #%d\n",
|
||||
mpf->mpf_feature1);
|
||||
construct_default_ISA_mptable(mpf->mpf_feature1);
|
||||
|
||||
} else if (mpf->mpf_physptr) {
|
||||
@ -659,8 +665,10 @@ void __init get_smp_config (void)
|
||||
*/
|
||||
if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
|
||||
smp_found_config = 0;
|
||||
printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
|
||||
printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
|
||||
printk(KERN_ERR
|
||||
"BIOS bug, MP table errors detected!...\n");
|
||||
printk(KERN_ERR
|
||||
"... disabling SMP support. (tell your hw vendor)\n");
|
||||
return;
|
||||
}
|
||||
|
||||
@ -673,7 +681,8 @@ void __init get_smp_config (void)
|
||||
if (!mp_irq_entries) {
|
||||
struct mpc_config_bus bus;
|
||||
|
||||
printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
|
||||
printk(KERN_ERR
|
||||
"BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
|
||||
|
||||
bus.mpc_type = MP_BUS;
|
||||
bus.mpc_busid = 0;
|
||||
@ -692,26 +701,26 @@ void __init get_smp_config (void)
|
||||
*/
|
||||
}
|
||||
|
||||
static int __init smp_scan_config (unsigned long base, unsigned long length)
|
||||
static int __init smp_scan_config(unsigned long base, unsigned long length)
|
||||
{
|
||||
unsigned long *bp = phys_to_virt(base);
|
||||
struct intel_mp_floating *mpf;
|
||||
|
||||
printk(KERN_INFO "Scan SMP from %p for %ld bytes.\n", bp,length);
|
||||
printk(KERN_INFO "Scan SMP from %p for %ld bytes.\n", bp, length);
|
||||
if (sizeof(*mpf) != 16)
|
||||
printk("Error: MPF size\n");
|
||||
|
||||
while (length > 0) {
|
||||
mpf = (struct intel_mp_floating *)bp;
|
||||
if ((*bp == SMP_MAGIC_IDENT) &&
|
||||
(mpf->mpf_length == 1) &&
|
||||
!mpf_checksum((unsigned char *)bp, 16) &&
|
||||
((mpf->mpf_specification == 1)
|
||||
|| (mpf->mpf_specification == 4)) ) {
|
||||
(mpf->mpf_length == 1) &&
|
||||
!mpf_checksum((unsigned char *)bp, 16) &&
|
||||
((mpf->mpf_specification == 1)
|
||||
|| (mpf->mpf_specification == 4))) {
|
||||
|
||||
smp_found_config = 1;
|
||||
printk(KERN_INFO "found SMP MP-table at [%p] %08lx\n",
|
||||
mpf, virt_to_phys(mpf));
|
||||
mpf, virt_to_phys(mpf));
|
||||
reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE,
|
||||
BOOTMEM_DEFAULT);
|
||||
if (mpf->mpf_physptr) {
|
||||
@ -741,7 +750,7 @@ static int __init smp_scan_config (unsigned long base, unsigned long length)
|
||||
return 0;
|
||||
}
|
||||
|
||||
void __init find_smp_config (void)
|
||||
void __init find_smp_config(void)
|
||||
{
|
||||
unsigned int address;
|
||||
|
||||
@ -753,9 +762,9 @@ void __init find_smp_config (void)
|
||||
* 2) Scan the top 1K of base RAM
|
||||
* 3) Scan the 64K of bios
|
||||
*/
|
||||
if (smp_scan_config(0x0,0x400) ||
|
||||
smp_scan_config(639*0x400,0x400) ||
|
||||
smp_scan_config(0xF0000,0x10000))
|
||||
if (smp_scan_config(0x0, 0x400) ||
|
||||
smp_scan_config(639 * 0x400, 0x400) ||
|
||||
smp_scan_config(0xF0000, 0x10000))
|
||||
return;
|
||||
/*
|
||||
* If it is an SMP machine we should know now, unless the
|
||||
@ -792,14 +801,14 @@ void __init find_smp_config (void)
|
||||
|
||||
extern struct mp_ioapic_routing mp_ioapic_routing[MAX_IO_APICS];
|
||||
|
||||
static int mp_find_ioapic (int gsi)
|
||||
static int mp_find_ioapic(int gsi)
|
||||
{
|
||||
int i = 0;
|
||||
|
||||
/* Find the IOAPIC that manages this GSI. */
|
||||
for (i = 0; i < nr_ioapics; i++) {
|
||||
if ((gsi >= mp_ioapic_routing[i].gsi_base)
|
||||
&& (gsi <= mp_ioapic_routing[i].gsi_end))
|
||||
&& (gsi <= mp_ioapic_routing[i].gsi_end))
|
||||
return i;
|
||||
}
|
||||
|
||||
@ -833,34 +842,32 @@ void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
|
||||
set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
|
||||
mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id);
|
||||
mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
|
||||
|
||||
/*
|
||||
|
||||
/*
|
||||
* Build basic GSI lookup table to facilitate gsi->io_apic lookups
|
||||
* and to prevent reprogramming of IOAPIC pins (PCI GSIs).
|
||||
*/
|
||||
mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
|
||||
mp_ioapic_routing[idx].gsi_base = gsi_base;
|
||||
mp_ioapic_routing[idx].gsi_end = gsi_base +
|
||||
io_apic_get_redir_entries(idx);
|
||||
io_apic_get_redir_entries(idx);
|
||||
|
||||
printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
|
||||
"GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
|
||||
mp_ioapics[idx].mpc_apicver,
|
||||
mp_ioapics[idx].mpc_apicaddr,
|
||||
mp_ioapic_routing[idx].gsi_base,
|
||||
mp_ioapic_routing[idx].gsi_end);
|
||||
mp_ioapic_routing[idx].gsi_base, mp_ioapic_routing[idx].gsi_end);
|
||||
|
||||
nr_ioapics++;
|
||||
}
|
||||
|
||||
void __init
|
||||
mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
|
||||
void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
|
||||
{
|
||||
struct mpc_config_intsrc intsrc;
|
||||
int ioapic = -1;
|
||||
int pin = -1;
|
||||
int ioapic = -1;
|
||||
int pin = -1;
|
||||
|
||||
/*
|
||||
/*
|
||||
* Convert 'gsi' to 'ioapic.pin'.
|
||||
*/
|
||||
ioapic = mp_find_ioapic(gsi);
|
||||
@ -870,7 +877,7 @@ mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
|
||||
|
||||
/*
|
||||
* TBD: This check is for faulty timer entries, where the override
|
||||
* erroneously sets the trigger to level, resulting in a HUGE
|
||||
* erroneously sets the trigger to level, resulting in a HUGE
|
||||
* increase of timer interrupts!
|
||||
*/
|
||||
if ((bus_irq == 0) && (trigger == 3))
|
||||
@ -880,13 +887,13 @@ mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
|
||||
intsrc.mpc_irqtype = mp_INT;
|
||||
intsrc.mpc_irqflag = (trigger << 2) | polarity;
|
||||
intsrc.mpc_srcbus = MP_ISA_BUS;
|
||||
intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
|
||||
intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
|
||||
intsrc.mpc_dstirq = pin; /* INTIN# */
|
||||
intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
|
||||
intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
|
||||
intsrc.mpc_dstirq = pin; /* INTIN# */
|
||||
|
||||
Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
|
||||
intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
|
||||
(intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
|
||||
intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
|
||||
(intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
|
||||
intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
|
||||
|
||||
mp_irqs[mp_irq_entries] = intsrc;
|
||||
@ -896,14 +903,14 @@ mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
|
||||
|
||||
int es7000_plat;
|
||||
|
||||
void __init mp_config_acpi_legacy_irqs (void)
|
||||
void __init mp_config_acpi_legacy_irqs(void)
|
||||
{
|
||||
struct mpc_config_intsrc intsrc;
|
||||
int i = 0;
|
||||
int ioapic = -1;
|
||||
|
||||
#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
|
||||
/*
|
||||
/*
|
||||
* Fabricate the legacy ISA bus (bus #31).
|
||||
*/
|
||||
mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
|
||||
@ -917,20 +924,20 @@ void __init mp_config_acpi_legacy_irqs (void)
|
||||
if (es7000_plat == 1)
|
||||
return;
|
||||
|
||||
/*
|
||||
* Locate the IOAPIC that manages the ISA IRQs (0-15).
|
||||
/*
|
||||
* Locate the IOAPIC that manages the ISA IRQs (0-15).
|
||||
*/
|
||||
ioapic = mp_find_ioapic(0);
|
||||
if (ioapic < 0)
|
||||
return;
|
||||
|
||||
intsrc.mpc_type = MP_INTSRC;
|
||||
intsrc.mpc_irqflag = 0; /* Conforming */
|
||||
intsrc.mpc_irqflag = 0; /* Conforming */
|
||||
intsrc.mpc_srcbus = MP_ISA_BUS;
|
||||
#ifdef CONFIG_X86_IO_APIC
|
||||
intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
|
||||
#endif
|
||||
/*
|
||||
/*
|
||||
* Use the default configuration for the IRQs 0-15. Unless
|
||||
* overridden by (MADT) interrupt source override entries.
|
||||
*/
|
||||
@ -941,28 +948,29 @@ void __init mp_config_acpi_legacy_irqs (void)
|
||||
struct mpc_config_intsrc *irq = mp_irqs + idx;
|
||||
|
||||
/* Do we already have a mapping for this ISA IRQ? */
|
||||
if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
|
||||
if (irq->mpc_srcbus == MP_ISA_BUS
|
||||
&& irq->mpc_srcbusirq == i)
|
||||
break;
|
||||
|
||||
/* Do we already have a mapping for this IOAPIC pin */
|
||||
if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
|
||||
(irq->mpc_dstirq == i))
|
||||
(irq->mpc_dstirq == i))
|
||||
break;
|
||||
}
|
||||
|
||||
if (idx != mp_irq_entries) {
|
||||
printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
|
||||
continue; /* IRQ already used */
|
||||
continue; /* IRQ already used */
|
||||
}
|
||||
|
||||
intsrc.mpc_irqtype = mp_INT;
|
||||
intsrc.mpc_srcbusirq = i; /* Identity mapped */
|
||||
intsrc.mpc_srcbusirq = i; /* Identity mapped */
|
||||
intsrc.mpc_dstirq = i;
|
||||
|
||||
Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
|
||||
"%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
|
||||
(intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
|
||||
intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
|
||||
"%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
|
||||
(intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
|
||||
intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
|
||||
intsrc.mpc_dstirq);
|
||||
|
||||
mp_irqs[mp_irq_entries] = intsrc;
|
||||
@ -985,7 +993,7 @@ int mp_register_gsi(u32 gsi, int triggering, int polarity)
|
||||
* represent all possible interrupts, and IRQs
|
||||
* assigned to actual devices.
|
||||
*/
|
||||
static int gsi_to_irq[MAX_GSI_NUM];
|
||||
static int gsi_to_irq[MAX_GSI_NUM];
|
||||
|
||||
/* Don't set up the ACPI SCI because it's already set up */
|
||||
if (acpi_gbl_FADT.sci_interrupt == gsi)
|
||||
@ -1002,8 +1010,8 @@ int mp_register_gsi(u32 gsi, int triggering, int polarity)
|
||||
if (ioapic_renumber_irq)
|
||||
gsi = ioapic_renumber_irq(ioapic, gsi);
|
||||
|
||||
/*
|
||||
* Avoid pin reprogramming. PRTs typically include entries
|
||||
/*
|
||||
* Avoid pin reprogramming. PRTs typically include entries
|
||||
* with redundant pin->gsi mappings (but unique PCI devices);
|
||||
* we only program the IOAPIC on the first.
|
||||
*/
|
||||
@ -1011,23 +1019,23 @@ int mp_register_gsi(u32 gsi, int triggering, int polarity)
|
||||
idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
|
||||
if (idx > 3) {
|
||||
printk(KERN_ERR "Invalid reference to IOAPIC pin "
|
||||
"%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
|
||||
ioapic_pin);
|
||||
"%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
|
||||
ioapic_pin);
|
||||
return gsi;
|
||||
}
|
||||
if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
|
||||
if ((1 << bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
|
||||
Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
|
||||
mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
|
||||
return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]);
|
||||
}
|
||||
|
||||
mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
|
||||
mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1 << bit);
|
||||
|
||||
/*
|
||||
* For GSI >= 64, use IRQ compression
|
||||
*/
|
||||
if ((gsi >= IRQ_COMPRESSION_START)
|
||||
&& (triggering == ACPI_LEVEL_SENSITIVE)) {
|
||||
&& (triggering == ACPI_LEVEL_SENSITIVE)) {
|
||||
/*
|
||||
* For PCI devices assign IRQs in order, avoiding gaps
|
||||
* due to unused I/O APIC pins.
|
||||
@ -1058,8 +1066,8 @@ int mp_register_gsi(u32 gsi, int triggering, int polarity)
|
||||
}
|
||||
|
||||
io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
|
||||
triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
|
||||
polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
|
||||
triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
|
||||
polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
|
||||
return gsi;
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user