[PATCH] dvb: frontend: mt352: fix signal strength reading

Fix two problems with the signal strength value in the mt352.c frontend:
1. the 4 most significant bits are zeroed - shift and mask wrong way round
2. need to align the 12 bits from the registers at the top of the 16 bit
   returned value - otherwise the range is not 0 to 0xffff its 0xf000 to 0xffff

Signed-off-by: Barry Scott <barry.scott@onelan.co.uk>
Signed-off-by: Johannes Stezenbach <js@linuxtv.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Barry Scott 2005-09-09 13:02:29 -07:00 committed by Linus Torvalds
parent 50b447d5b7
commit 4ff4ac1bea

View File

@ -462,9 +462,11 @@ static int mt352_read_signal_strength(struct dvb_frontend* fe, u16* strength)
{
struct mt352_state* state = fe->demodulator_priv;
u16 signal = ((mt352_read_register(state, AGC_GAIN_1) << 8) & 0x0f) |
(mt352_read_register(state, AGC_GAIN_0));
/* align the 12 bit AGC gain with the most significant bits */
u16 signal = ((mt352_read_register(state, AGC_GAIN_1) & 0x0f) << 12) |
(mt352_read_register(state, AGC_GAIN_0) << 4);
/* inverse of gain is signal strength */
*strength = ~signal;
return 0;
}