forked from luck/tmp_suning_uos_patched
powerpc sstep: Add support for prefixed load/stores
This adds emulation support for the following prefixed integer load/stores: * Prefixed Load Byte and Zero (plbz) * Prefixed Load Halfword and Zero (plhz) * Prefixed Load Halfword Algebraic (plha) * Prefixed Load Word and Zero (plwz) * Prefixed Load Word Algebraic (plwa) * Prefixed Load Doubleword (pld) * Prefixed Store Byte (pstb) * Prefixed Store Halfword (psth) * Prefixed Store Word (pstw) * Prefixed Store Doubleword (pstd) * Prefixed Load Quadword (plq) * Prefixed Store Quadword (pstq) the follow prefixed floating-point load/stores: * Prefixed Load Floating-Point Single (plfs) * Prefixed Load Floating-Point Double (plfd) * Prefixed Store Floating-Point Single (pstfs) * Prefixed Store Floating-Point Double (pstfd) and for the following prefixed VSX load/stores: * Prefixed Load VSX Scalar Doubleword (plxsd) * Prefixed Load VSX Scalar Single-Precision (plxssp) * Prefixed Load VSX Vector [0|1] (plxv, plxv0, plxv1) * Prefixed Store VSX Scalar Doubleword (pstxsd) * Prefixed Store VSX Scalar Single-Precision (pstxssp) * Prefixed Store VSX Vector [0|1] (pstxv, pstxv0, pstxv1) Signed-off-by: Jordan Niethe <jniethe5@gmail.com> Reviewed-by: Balamuruhan S <bala24@linux.ibm.com> [mpe: Use CONFIG_PPC64 not __powerpc64__, use get_op()] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200506034050.24806-30-jniethe5@gmail.com
This commit is contained in:
Jordan Niethe
Michael Ellerman
parent
9409d2f9da
commit
50b80a12e4
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@ -90,11 +90,15 @@ enum instruction_type {
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#define VSX_LDLEFT 4 /* load VSX register from left */
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#define VSX_CHECK_VEC 8 /* check MSR_VEC not MSR_VSX for reg >= 32 */
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/* Prefixed flag, ORed in with type */
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#define PREFIXED 0x800
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/* Size field in type word */
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#define SIZE(n) ((n) << 12)
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#define GETSIZE(w) ((w) >> 12)
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#define GETTYPE(t) ((t) & INSTR_TYPE_MASK)
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#define GETLENGTH(t) (((t) & PREFIXED) ? 8 : 4)
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#define MKOP(t, f, s) ((t) | (f) | SIZE(s))
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@ -13,6 +13,7 @@
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#include <linux/uaccess.h>
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#include <asm/cpu_has_feature.h>
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#include <asm/cputable.h>
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#include <asm/disassemble.h>
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extern char system_call_common[];
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@ -187,6 +188,44 @@ static nokprobe_inline unsigned long xform_ea(unsigned int instr,
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return ea;
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}
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/*
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* Calculate effective address for a MLS:D-form / 8LS:D-form
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* prefixed instruction
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*/
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static nokprobe_inline unsigned long mlsd_8lsd_ea(unsigned int instr,
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unsigned int suffix,
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const struct pt_regs *regs)
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{
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int ra, prefix_r;
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unsigned int dd;
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unsigned long ea, d0, d1, d;
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prefix_r = instr & (1ul << 20);
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ra = (suffix >> 16) & 0x1f;
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d0 = instr & 0x3ffff;
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d1 = suffix & 0xffff;
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d = (d0 << 16) | d1;
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/*
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* sign extend a 34 bit number
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*/
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dd = (unsigned int)(d >> 2);
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ea = (signed int)dd;
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ea = (ea << 2) | (d & 0x3);
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if (!prefix_r && ra)
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ea += regs->gpr[ra];
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else if (!prefix_r && !ra)
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; /* Leave ea as is */
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else if (prefix_r && !ra)
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ea += regs->nip;
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else if (prefix_r && ra)
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; /* Invalid form. Should already be checked for by caller! */
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return ea;
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}
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/*
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* Return the largest power of 2, not greater than sizeof(unsigned long),
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* such that x is a multiple of it.
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@ -1165,6 +1204,9 @@ static nokprobe_inline int trap_compare(long v1, long v2)
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int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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struct ppc_inst instr)
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{
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#ifdef CONFIG_PPC64
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unsigned int suffixopcode, prefixtype, prefix_r;
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#endif
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unsigned int opcode, ra, rb, rc, rd, spr, u;
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unsigned long int imm;
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unsigned long int val, val2;
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@ -2652,6 +2694,124 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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break;
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}
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break;
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case 1: /* Prefixed instructions */
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prefix_r = word & (1ul << 20);
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ra = (suffix >> 16) & 0x1f;
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op->update_reg = ra;
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rd = (suffix >> 21) & 0x1f;
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op->reg = rd;
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op->val = regs->gpr[rd];
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suffixopcode = get_op(suffix);
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prefixtype = (word >> 24) & 0x3;
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switch (prefixtype) {
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case 0: /* Type 00 Eight-Byte Load/Store */
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if (prefix_r && ra)
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break;
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op->ea = mlsd_8lsd_ea(word, suffix, regs);
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switch (suffixopcode) {
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case 41: /* plwa */
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op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4);
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break;
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case 42: /* plxsd */
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op->reg = rd + 32;
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op->type = MKOP(LOAD_VSX, PREFIXED, 8);
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op->element_size = 8;
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op->vsx_flags = VSX_CHECK_VEC;
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break;
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case 43: /* plxssp */
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op->reg = rd + 32;
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op->type = MKOP(LOAD_VSX, PREFIXED, 4);
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op->element_size = 8;
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op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
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break;
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case 46: /* pstxsd */
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op->reg = rd + 32;
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op->type = MKOP(STORE_VSX, PREFIXED, 8);
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op->element_size = 8;
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op->vsx_flags = VSX_CHECK_VEC;
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break;
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case 47: /* pstxssp */
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op->reg = rd + 32;
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op->type = MKOP(STORE_VSX, PREFIXED, 4);
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op->element_size = 8;
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op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
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break;
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case 51: /* plxv1 */
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op->reg += 32;
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fallthrough;
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case 50: /* plxv0 */
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op->type = MKOP(LOAD_VSX, PREFIXED, 16);
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op->element_size = 16;
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op->vsx_flags = VSX_CHECK_VEC;
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break;
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case 55: /* pstxv1 */
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op->reg = rd + 32;
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fallthrough;
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case 54: /* pstxv0 */
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op->type = MKOP(STORE_VSX, PREFIXED, 16);
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op->element_size = 16;
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op->vsx_flags = VSX_CHECK_VEC;
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break;
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case 56: /* plq */
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op->type = MKOP(LOAD, PREFIXED, 16);
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break;
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case 57: /* pld */
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op->type = MKOP(LOAD, PREFIXED, 8);
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break;
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case 60: /* stq */
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op->type = MKOP(STORE, PREFIXED, 16);
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break;
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case 61: /* pstd */
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op->type = MKOP(STORE, PREFIXED, 8);
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break;
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}
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break;
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case 1: /* Type 01 Eight-Byte Register-to-Register */
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break;
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case 2: /* Type 10 Modified Load/Store */
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if (prefix_r && ra)
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break;
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op->ea = mlsd_8lsd_ea(word, suffix, regs);
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switch (suffixopcode) {
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case 32: /* plwz */
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op->type = MKOP(LOAD, PREFIXED, 4);
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break;
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case 34: /* plbz */
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op->type = MKOP(LOAD, PREFIXED, 1);
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break;
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case 36: /* pstw */
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op->type = MKOP(STORE, PREFIXED, 4);
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break;
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case 38: /* pstb */
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op->type = MKOP(STORE, PREFIXED, 1);
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break;
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case 40: /* plhz */
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op->type = MKOP(LOAD, PREFIXED, 2);
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break;
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case 42: /* plha */
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op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 2);
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break;
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case 44: /* psth */
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op->type = MKOP(STORE, PREFIXED, 2);
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break;
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case 48: /* plfs */
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op->type = MKOP(LOAD_FP, PREFIXED | FPCONV, 4);
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break;
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case 50: /* plfd */
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op->type = MKOP(LOAD_FP, PREFIXED, 8);
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break;
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case 52: /* pstfs */
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op->type = MKOP(STORE_FP, PREFIXED | FPCONV, 4);
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break;
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case 54: /* pstfd */
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op->type = MKOP(STORE_FP, PREFIXED, 8);
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break;
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}
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break;
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case 3: /* Type 11 Modified Register-to-Register */
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break;
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}
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#endif /* __powerpc64__ */
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}
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@ -2760,7 +2920,7 @@ void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
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{
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unsigned long next_pc;
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next_pc = truncate_if_32bit(regs->msr, regs->nip + 4);
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next_pc = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op->type));
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switch (GETTYPE(op->type)) {
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case COMPUTE:
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if (op->type & SETREG)
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@ -3205,7 +3365,7 @@ int emulate_step(struct pt_regs *regs, struct ppc_inst instr)
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return 0;
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instr_done:
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regs->nip = truncate_if_32bit(regs->msr, regs->nip + 4);
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regs->nip = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op.type));
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return 1;
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}
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NOKPROBE_SYMBOL(emulate_step);
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