forked from luck/tmp_suning_uos_patched
[SPARC64]: Access TSB with physical addresses when possible.
This way we don't need to lock the TSB into the TLB. The trick is that every TSB load/store is registered into a special instruction patch section. The default uses virtual addresses, and the patch instructions use physical address load/stores. We can't do this on all chips because only cheetah+ and later have the physical variant of the atomic quad load. Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
b0fd4e49ae
commit
517af33237
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@ -4,7 +4,7 @@
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srlx %g6, 48, %g5 ! Get context
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brz,pn %g5, kvmap_dtlb ! Context 0 processing
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nop ! Delay slot (fill me)
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ldda [%g1] ASI_NUCLEUS_QUAD_LDD, %g4 ! Load TSB entry
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TSB_LOAD_QUAD(%g1, %g4) ! Load TSB entry
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nop ! Push branch to next I$ line
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cmp %g4, %g6 ! Compare TAG
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@ -4,7 +4,7 @@
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srlx %g6, 48, %g5 ! Get context
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brz,pn %g5, kvmap_itlb ! Context 0 processing
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nop ! Delay slot (fill me)
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ldda [%g1] ASI_NUCLEUS_QUAD_LDD, %g4 ! Load TSB entry
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TSB_LOAD_QUAD(%g1, %g4) ! Load TSB entry
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cmp %g4, %g6 ! Compare TAG
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sethi %hi(_PAGE_EXEC), %g4 ! Setup exec check
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@ -44,14 +44,14 @@ kvmap_itlb_tsb_miss:
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kvmap_itlb_vmalloc_addr:
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KERN_PGTABLE_WALK(%g4, %g5, %g2, kvmap_itlb_longpath)
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TSB_LOCK_TAG(%g1, %g2, %g4)
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KTSB_LOCK_TAG(%g1, %g2, %g4)
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/* Load and check PTE. */
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ldxa [%g5] ASI_PHYS_USE_EC, %g5
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brgez,a,pn %g5, kvmap_itlb_longpath
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stx %g0, [%g1]
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KTSB_STORE(%g1, %g0)
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TSB_WRITE(%g1, %g5, %g6)
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KTSB_WRITE(%g1, %g5, %g6)
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/* fallthrough to TLB load */
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@ -69,9 +69,9 @@ kvmap_itlb_longpath:
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kvmap_itlb_obp:
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OBP_TRANS_LOOKUP(%g4, %g5, %g2, %g3, kvmap_itlb_longpath)
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TSB_LOCK_TAG(%g1, %g2, %g4)
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KTSB_LOCK_TAG(%g1, %g2, %g4)
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TSB_WRITE(%g1, %g5, %g6)
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KTSB_WRITE(%g1, %g5, %g6)
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ba,pt %xcc, kvmap_itlb_load
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nop
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@ -79,9 +79,9 @@ kvmap_itlb_obp:
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kvmap_dtlb_obp:
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OBP_TRANS_LOOKUP(%g4, %g5, %g2, %g3, kvmap_dtlb_longpath)
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TSB_LOCK_TAG(%g1, %g2, %g4)
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KTSB_LOCK_TAG(%g1, %g2, %g4)
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TSB_WRITE(%g1, %g5, %g6)
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KTSB_WRITE(%g1, %g5, %g6)
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ba,pt %xcc, kvmap_dtlb_load
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nop
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@ -114,14 +114,14 @@ kvmap_linear_patch:
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kvmap_dtlb_vmalloc_addr:
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KERN_PGTABLE_WALK(%g4, %g5, %g2, kvmap_dtlb_longpath)
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TSB_LOCK_TAG(%g1, %g2, %g4)
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KTSB_LOCK_TAG(%g1, %g2, %g4)
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/* Load and check PTE. */
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ldxa [%g5] ASI_PHYS_USE_EC, %g5
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brgez,a,pn %g5, kvmap_dtlb_longpath
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stx %g0, [%g1]
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KTSB_STORE(%g1, %g0)
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TSB_WRITE(%g1, %g5, %g6)
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KTSB_WRITE(%g1, %g5, %g6)
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/* fallthrough to TLB load */
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@ -53,7 +53,7 @@ tsb_reload:
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/* Load and check PTE. */
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ldxa [%g5] ASI_PHYS_USE_EC, %g5
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brgez,a,pn %g5, tsb_do_fault
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stx %g0, [%g1]
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TSB_STORE(%g1, %g0)
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/* If it is larger than the base page size, don't
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* bother putting it into the TSB.
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@ -64,7 +64,7 @@ tsb_reload:
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and %g2, %g4, %g2
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cmp %g2, %g7
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bne,a,pn %xcc, tsb_tlb_reload
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stx %g0, [%g1]
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TSB_STORE(%g1, %g0)
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TSB_WRITE(%g1, %g5, %g6)
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@ -131,13 +131,13 @@ winfix_trampoline:
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/* Insert an entry into the TSB.
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*
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* %o0: TSB entry pointer
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* %o0: TSB entry pointer (virt or phys address)
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* %o1: tag
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* %o2: pte
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*/
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.align 32
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.globl tsb_insert
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tsb_insert:
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.globl __tsb_insert
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__tsb_insert:
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rdpr %pstate, %o5
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wrpr %o5, PSTATE_IE, %pstate
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TSB_LOCK_TAG(%o0, %g2, %g3)
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@ -146,6 +146,31 @@ tsb_insert:
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retl
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nop
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/* Flush the given TSB entry if it has the matching
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* tag.
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*
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* %o0: TSB entry pointer (virt or phys address)
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* %o1: tag
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*/
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.align 32
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.globl tsb_flush
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tsb_flush:
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sethi %hi(TSB_TAG_LOCK_HIGH), %g2
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1: TSB_LOAD_TAG(%o0, %g1)
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srlx %g1, 32, %o3
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andcc %o3, %g2, %g0
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bne,pn %icc, 1b
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membar #LoadLoad
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cmp %g1, %o1
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bne,pt %xcc, 2f
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clr %o3
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TSB_CAS_TAG(%o0, %g1, %o3)
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cmp %g1, %o3
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bne,pn %xcc, 1b
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nop
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2: retl
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TSB_MEMBAR
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/* Reload MMU related context switch state at
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* schedule() time.
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*
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@ -70,6 +70,10 @@ SECTIONS
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.con_initcall.init : { *(.con_initcall.init) }
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__con_initcall_end = .;
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SECURITY_INIT
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. = ALIGN(4);
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__tsb_phys_patch = .;
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.tsb_phys_patch : { *(.tsb_phys_patch) }
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__tsb_phys_patch_end = .;
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. = ALIGN(8192);
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__initramfs_start = .;
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.init.ramfs : { *(.init.ramfs) }
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@ -39,6 +39,7 @@
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#include <asm/tlb.h>
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#include <asm/spitfire.h>
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#include <asm/sections.h>
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#include <asm/tsb.h>
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extern void device_scan(void);
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@ -244,6 +245,16 @@ static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long c
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: "g1", "g7");
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}
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static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
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{
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unsigned long tsb_addr = (unsigned long) ent;
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if (tlb_type == cheetah_plus)
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tsb_addr = __pa(tsb_addr);
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__tsb_insert(tsb_addr, tag, pte);
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}
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void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
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{
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struct mm_struct *mm;
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@ -1040,6 +1051,24 @@ unsigned long __init find_ecache_flush_span(unsigned long size)
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return ~0UL;
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}
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static void __init tsb_phys_patch(void)
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{
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struct tsb_phys_patch_entry *p;
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p = &__tsb_phys_patch;
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while (p < &__tsb_phys_patch_end) {
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unsigned long addr = p->addr;
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*(unsigned int *) addr = p->insn;
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wmb();
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__asm__ __volatile__("flush %0"
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: /* no outputs */
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: "r" (addr));
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p++;
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}
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}
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/* paging_init() sets up the page tables */
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extern void cheetah_ecache_flush_init(void);
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@ -1052,6 +1081,9 @@ void __init paging_init(void)
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unsigned long end_pfn, pages_avail, shift;
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unsigned long real_end, i;
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if (tlb_type == cheetah_plus)
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tsb_phys_patch();
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/* Find available physical memory... */
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read_obp_memory("available", &pavail[0], &pavail_ents);
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@ -20,12 +20,9 @@ static inline unsigned long tsb_hash(unsigned long vaddr, unsigned long nentries
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return vaddr & (nentries - 1);
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}
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static inline int tag_compare(struct tsb *entry, unsigned long vaddr, unsigned long context)
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static inline int tag_compare(unsigned long tag, unsigned long vaddr, unsigned long context)
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{
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if (context == ~0UL)
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return 1;
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return (entry->tag == ((vaddr >> 22) | (context << 48)));
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return (tag == ((vaddr >> 22) | (context << 48)));
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}
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/* TSB flushes need only occur on the processor initiating the address
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unsigned long hash = tsb_hash(v, KERNEL_TSB_NENTRIES);
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struct tsb *ent = &swapper_tsb[hash];
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if (tag_compare(ent, v, 0)) {
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if (tag_compare(ent->tag, v, 0)) {
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ent->tag = 0UL;
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membar_storeload_storestore();
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}
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@ -52,24 +49,31 @@ void flush_tsb_user(struct mmu_gather *mp)
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{
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struct mm_struct *mm = mp->mm;
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struct tsb *tsb = mm->context.tsb;
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unsigned long ctx = ~0UL;
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unsigned long nentries = mm->context.tsb_nentries;
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unsigned long ctx, base;
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int i;
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if (CTX_VALID(mm->context))
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ctx = CTX_HWBITS(mm->context);
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if (unlikely(!CTX_VALID(mm->context)))
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return;
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ctx = CTX_HWBITS(mm->context);
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if (tlb_type == cheetah_plus)
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base = __pa(tsb);
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else
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base = (unsigned long) tsb;
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for (i = 0; i < mp->tlb_nr; i++) {
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unsigned long v = mp->vaddrs[i];
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struct tsb *ent;
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unsigned long tag, ent, hash;
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v &= ~0x1UL;
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ent = &tsb[tsb_hash(v, nentries)];
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if (tag_compare(ent, v, ctx)) {
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ent->tag = 0UL;
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membar_storeload_storestore();
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}
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hash = tsb_hash(v, nentries);
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ent = base + (hash * sizeof(struct tsb));
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tag = (v >> 22UL) | (ctx << 48UL);
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tsb_flush(ent, tag);
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}
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}
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@ -84,6 +88,7 @@ static void setup_tsb_params(struct mm_struct *mm, unsigned long tsb_bytes)
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tte = (_PAGE_VALID | _PAGE_L | _PAGE_CP |
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_PAGE_CV | _PAGE_P | _PAGE_W);
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tsb_paddr = __pa(mm->context.tsb);
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BUG_ON(tsb_paddr & (tsb_bytes - 1UL));
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/* Use the smallest page size that can map the whole TSB
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* in one TLB entry.
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BUG();
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};
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tsb_reg |= base;
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tsb_reg |= (tsb_paddr & (page_sz - 1UL));
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tte |= (tsb_paddr & ~(page_sz - 1UL));
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if (tlb_type == cheetah_plus) {
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/* Physical mapping, no locked TLB entry for TSB. */
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tsb_reg |= tsb_paddr;
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mm->context.tsb_reg_val = tsb_reg;
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mm->context.tsb_map_vaddr = 0;
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mm->context.tsb_map_pte = 0;
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} else {
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tsb_reg |= base;
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tsb_reg |= (tsb_paddr & (page_sz - 1UL));
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tte |= (tsb_paddr & ~(page_sz - 1UL));
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mm->context.tsb_reg_val = tsb_reg;
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mm->context.tsb_map_vaddr = base;
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mm->context.tsb_map_pte = tte;
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}
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mm->context.tsb_reg_val = tsb_reg;
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mm->context.tsb_map_vaddr = base;
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mm->context.tsb_map_pte = tte;
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}
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/* The page tables are locked against modifications while this
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@ -168,13 +183,21 @@ static void copy_tsb(struct tsb *old_tsb, unsigned long old_size,
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for (i = 0; i < old_nentries; i++) {
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register unsigned long tag asm("o4");
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register unsigned long pte asm("o5");
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unsigned long v;
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unsigned int hash;
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unsigned long v, hash;
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__asm__ __volatile__(
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"ldda [%2] %3, %0"
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: "=r" (tag), "=r" (pte)
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: "r" (&old_tsb[i]), "i" (ASI_NUCLEUS_QUAD_LDD));
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if (tlb_type == cheetah_plus) {
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__asm__ __volatile__(
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"ldda [%2] %3, %0"
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: "=r" (tag), "=r" (pte)
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: "r" (__pa(&old_tsb[i])),
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"i" (ASI_QUAD_LDD_PHYS));
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} else {
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__asm__ __volatile__(
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"ldda [%2] %3, %0"
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: "=r" (tag), "=r" (pte)
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: "r" (&old_tsb[i]),
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"i" (ASI_NUCLEUS_QUAD_LDD));
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}
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if (!tag || (tag & (1UL << TSB_TAG_LOCK_BIT)))
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continue;
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@ -198,8 +221,20 @@ static void copy_tsb(struct tsb *old_tsb, unsigned long old_size,
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v |= (i & (512UL - 1UL)) << 13UL;
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hash = tsb_hash(v, new_nentries);
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new_tsb[hash].tag = tag;
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new_tsb[hash].pte = pte;
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if (tlb_type == cheetah_plus) {
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__asm__ __volatile__(
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"stxa %0, [%1] %2\n\t"
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"stxa %3, [%4] %2"
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: /* no outputs */
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: "r" (tag),
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"r" (__pa(&new_tsb[hash].tag)),
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"i" (ASI_PHYS_USE_EC),
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"r" (pte),
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"r" (__pa(&new_tsb[hash].pte)));
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} else {
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new_tsb[hash].tag = tag;
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new_tsb[hash].pte = pte;
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}
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}
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}
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@ -97,7 +97,8 @@ struct tsb {
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unsigned long pte;
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} __attribute__((aligned(TSB_ENTRY_ALIGNMENT)));
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extern void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte);
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extern void __tsb_insert(unsigned long ent, unsigned long tag, unsigned long pte);
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extern void tsb_flush(unsigned long ent, unsigned long tag);
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typedef struct {
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unsigned long sparc64_ctx_val;
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@ -44,7 +44,89 @@
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#define TSB_MEMBAR membar #StoreStore
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/* Some cpus support physical address quad loads. We want to use
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* those if possible so we don't need to hard-lock the TSB mapping
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* into the TLB. We encode some instruction patching in order to
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* support this.
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*
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* The kernel TSB is locked into the TLB by virtue of being in the
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* kernel image, so we don't play these games for swapper_tsb access.
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*/
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#ifndef __ASSEMBLY__
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struct tsb_phys_patch_entry {
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unsigned int addr;
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unsigned int insn;
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};
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extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end;
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#endif
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#define TSB_LOAD_QUAD(TSB, REG) \
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661: ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \
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.section .tsb_phys_patch, "ax"; \
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.word 661b; \
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ldda [TSB] ASI_QUAD_LDD_PHYS, REG; \
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.previous
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#define TSB_LOAD_TAG_HIGH(TSB, REG) \
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661: lduwa [TSB] ASI_N, REG; \
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.section .tsb_phys_patch, "ax"; \
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.word 661b; \
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lduwa [TSB] ASI_PHYS_USE_EC, REG; \
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.previous
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#define TSB_LOAD_TAG(TSB, REG) \
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661: ldxa [TSB] ASI_N, REG; \
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.section .tsb_phys_patch, "ax"; \
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.word 661b; \
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ldxa [TSB] ASI_PHYS_USE_EC, REG; \
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.previous
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#define TSB_CAS_TAG_HIGH(TSB, REG1, REG2) \
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661: casa [TSB] ASI_N, REG1, REG2; \
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.section .tsb_phys_patch, "ax"; \
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.word 661b; \
|
||||
casa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
|
||||
.previous
|
||||
|
||||
#define TSB_CAS_TAG(TSB, REG1, REG2) \
|
||||
661: casxa [TSB] ASI_N, REG1, REG2; \
|
||||
.section .tsb_phys_patch, "ax"; \
|
||||
.word 661b; \
|
||||
casxa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
|
||||
.previous
|
||||
|
||||
#define TSB_STORE(ADDR, VAL) \
|
||||
661: stxa VAL, [ADDR] ASI_N; \
|
||||
.section .tsb_phys_patch, "ax"; \
|
||||
.word 661b; \
|
||||
stxa VAL, [ADDR] ASI_PHYS_USE_EC; \
|
||||
.previous
|
||||
|
||||
#define TSB_LOCK_TAG(TSB, REG1, REG2) \
|
||||
99: TSB_LOAD_TAG_HIGH(TSB, REG1); \
|
||||
sethi %hi(TSB_TAG_LOCK_HIGH), REG2;\
|
||||
andcc REG1, REG2, %g0; \
|
||||
bne,pn %icc, 99b; \
|
||||
nop; \
|
||||
TSB_CAS_TAG_HIGH(TSB, REG1, REG2); \
|
||||
cmp REG1, REG2; \
|
||||
bne,pn %icc, 99b; \
|
||||
nop; \
|
||||
TSB_MEMBAR
|
||||
|
||||
#define TSB_WRITE(TSB, TTE, TAG) \
|
||||
add TSB, 0x8, TSB; \
|
||||
TSB_STORE(TSB, TTE); \
|
||||
sub TSB, 0x8, TSB; \
|
||||
TSB_MEMBAR; \
|
||||
TSB_STORE(TSB, TAG);
|
||||
|
||||
#define KTSB_LOAD_QUAD(TSB, REG) \
|
||||
ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG;
|
||||
|
||||
#define KTSB_STORE(ADDR, VAL) \
|
||||
stxa VAL, [ADDR] ASI_N;
|
||||
|
||||
#define KTSB_LOCK_TAG(TSB, REG1, REG2) \
|
||||
99: lduwa [TSB] ASI_N, REG1; \
|
||||
sethi %hi(TSB_TAG_LOCK_HIGH), REG2;\
|
||||
andcc REG1, REG2, %g0; \
|
||||
|
@ -56,10 +138,12 @@
|
|||
nop; \
|
||||
TSB_MEMBAR
|
||||
|
||||
#define TSB_WRITE(TSB, TTE, TAG) \
|
||||
stx TTE, [TSB + 0x08]; \
|
||||
TSB_MEMBAR; \
|
||||
stx TAG, [TSB + 0x00];
|
||||
#define KTSB_WRITE(TSB, TTE, TAG) \
|
||||
add TSB, 0x8, TSB; \
|
||||
stxa TTE, [TSB] ASI_N; \
|
||||
sub TSB, 0x8, TSB; \
|
||||
TSB_MEMBAR; \
|
||||
stxa TAG, [TSB] ASI_N;
|
||||
|
||||
/* Do a kernel page table walk. Leaves physical PTE pointer in
|
||||
* REG1. Jumps to FAIL_LABEL on early page table walk termination.
|
||||
|
@ -157,7 +241,7 @@
|
|||
and REG2, (KERNEL_TSB_NENTRIES - 1), REG2; \
|
||||
sllx REG2, 4, REG2; \
|
||||
add REG1, REG2, REG2; \
|
||||
ldda [REG2] ASI_NUCLEUS_QUAD_LDD, REG3; \
|
||||
KTSB_LOAD_QUAD(REG2, REG3); \
|
||||
cmp REG3, TAG; \
|
||||
be,a,pt %xcc, OK_LABEL; \
|
||||
mov REG4, REG1;
|
||||
|
|
Loading…
Reference in New Issue
Block a user