forked from luck/tmp_suning_uos_patched
iommu/amd: Add support for IOMMUv2 domain mode
This patch adds support for protection domains that implement two-level paging for devices. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
This commit is contained in:
Joerg Roedel
parent
132bd68f18
commit
52815b7568
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@ -34,7 +34,9 @@ config AMD_IOMMU
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bool "AMD IOMMU support"
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select SWIOTLB
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select PCI_MSI
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select PCI_IOV
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select PCI_ATS
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select PCI_PRI
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select PCI_PASID
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select IOMMU_API
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depends on X86_64 && PCI && ACPI
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---help---
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@ -63,6 +63,7 @@ static struct protection_domain *pt_domain;
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static struct iommu_ops amd_iommu_ops;
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static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
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int amd_iommu_max_glx_val = -1;
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/*
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* general struct to manage commands send to an IOMMU
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@ -1598,6 +1599,11 @@ static void free_pagetable(struct protection_domain *domain)
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domain->pt_root = NULL;
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}
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static void free_gcr3_table(struct protection_domain *domain)
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{
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free_page((unsigned long)domain->gcr3_tbl);
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}
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/*
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* Free a domain, only used if something went wrong in the
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* allocation path and we need to free an already allocated page table
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@ -1699,6 +1705,32 @@ static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
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if (ats)
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flags |= DTE_FLAG_IOTLB;
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if (domain->flags & PD_IOMMUV2_MASK) {
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u64 gcr3 = __pa(domain->gcr3_tbl);
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u64 glx = domain->glx;
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u64 tmp;
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pte_root |= DTE_FLAG_GV;
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pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
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/* First mask out possible old values for GCR3 table */
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tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
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flags &= ~tmp;
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tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
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flags &= ~tmp;
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/* Encode GCR3 table into DTE */
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tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
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pte_root |= tmp;
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tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
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flags |= tmp;
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tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
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flags |= tmp;
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}
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flags &= ~(0xffffUL);
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flags |= domain->id;
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@ -1803,6 +1835,46 @@ static int __attach_device(struct iommu_dev_data *dev_data,
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return ret;
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}
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static void pdev_iommuv2_disable(struct pci_dev *pdev)
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{
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pci_disable_ats(pdev);
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pci_disable_pri(pdev);
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pci_disable_pasid(pdev);
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}
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static int pdev_iommuv2_enable(struct pci_dev *pdev)
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{
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int ret;
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/* Only allow access to user-accessible pages */
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ret = pci_enable_pasid(pdev, 0);
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if (ret)
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goto out_err;
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/* First reset the PRI state of the device */
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ret = pci_reset_pri(pdev);
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if (ret)
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goto out_err;
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/* FIXME: Hardcode number of outstanding requests for now */
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ret = pci_enable_pri(pdev, 32);
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if (ret)
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goto out_err;
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ret = pci_enable_ats(pdev, PAGE_SHIFT);
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if (ret)
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goto out_err;
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return 0;
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out_err:
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pci_disable_pri(pdev);
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pci_disable_pasid(pdev);
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return ret;
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}
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/*
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* If a device is not yet associated with a domain, this function does
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* assigns it visible for the hardware
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@ -1817,7 +1889,17 @@ static int attach_device(struct device *dev,
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dev_data = get_dev_data(dev);
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if (amd_iommu_iotlb_sup && pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
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if (domain->flags & PD_IOMMUV2_MASK) {
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if (!dev_data->iommu_v2 || !dev_data->passthrough)
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return -EINVAL;
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if (pdev_iommuv2_enable(pdev) != 0)
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return -EINVAL;
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dev_data->ats.enabled = true;
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dev_data->ats.qdep = pci_ats_queue_depth(pdev);
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} else if (amd_iommu_iotlb_sup &&
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pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
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dev_data->ats.enabled = true;
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dev_data->ats.qdep = pci_ats_queue_depth(pdev);
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}
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@ -1877,20 +1959,24 @@ static void __detach_device(struct iommu_dev_data *dev_data)
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*/
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static void detach_device(struct device *dev)
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{
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struct protection_domain *domain;
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struct iommu_dev_data *dev_data;
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unsigned long flags;
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dev_data = get_dev_data(dev);
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domain = dev_data->domain;
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/* lock device table */
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write_lock_irqsave(&amd_iommu_devtable_lock, flags);
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__detach_device(dev_data);
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write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
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if (dev_data->ats.enabled) {
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if (domain->flags & PD_IOMMUV2_MASK)
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pdev_iommuv2_disable(to_pci_dev(dev));
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else if (dev_data->ats.enabled)
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pci_disable_ats(to_pci_dev(dev));
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dev_data->ats.enabled = false;
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}
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dev_data->ats.enabled = false;
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}
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/*
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@ -2788,6 +2874,9 @@ static void amd_iommu_domain_destroy(struct iommu_domain *dom)
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if (domain->mode != PAGE_MODE_NONE)
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free_pagetable(domain);
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if (domain->flags & PD_IOMMUV2_MASK)
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free_gcr3_table(domain);
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protection_domain_free(domain);
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dom->priv = NULL;
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@ -3010,3 +3099,50 @@ void amd_iommu_domain_direct_map(struct iommu_domain *dom)
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spin_unlock_irqrestore(&domain->lock, flags);
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}
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EXPORT_SYMBOL(amd_iommu_domain_direct_map);
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int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
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{
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struct protection_domain *domain = dom->priv;
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unsigned long flags;
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int levels, ret;
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if (pasids <= 0 || pasids > (PASID_MASK + 1))
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return -EINVAL;
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/* Number of GCR3 table levels required */
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for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
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levels += 1;
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if (levels > amd_iommu_max_glx_val)
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return -EINVAL;
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spin_lock_irqsave(&domain->lock, flags);
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/*
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* Save us all sanity checks whether devices already in the
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* domain support IOMMUv2. Just force that the domain has no
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* devices attached when it is switched into IOMMUv2 mode.
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*/
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ret = -EBUSY;
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if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
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goto out;
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ret = -ENOMEM;
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domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
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if (domain->gcr3_tbl == NULL)
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goto out;
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domain->glx = levels;
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domain->flags |= PD_IOMMUV2_MASK;
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domain->updated = true;
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update_domain(domain);
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ret = 0;
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out:
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spin_unlock_irqrestore(&domain->lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
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@ -755,6 +755,7 @@ static void __init init_iommu_from_pci(struct amd_iommu *iommu)
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iommu->features = ((u64)high << 32) | low;
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if (iommu_feature(iommu, FEATURE_GT)) {
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int glxval;
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u32 pasids;
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u64 shift;
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@ -763,6 +764,14 @@ static void __init init_iommu_from_pci(struct amd_iommu *iommu)
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pasids = (1 << shift);
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amd_iommu_max_pasids = min(amd_iommu_max_pasids, pasids);
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glxval = iommu->features & FEATURE_GLXVAL_MASK;
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glxval >>= FEATURE_GLXVAL_SHIFT;
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if (amd_iommu_max_glx_val == -1)
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amd_iommu_max_glx_val = glxval;
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else
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amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
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}
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if (iommu_feature(iommu, FEATURE_GT) &&
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@ -39,6 +39,7 @@ extern bool amd_iommu_v2_supported(void);
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extern int amd_iommu_register_ppr_notifier(struct notifier_block *nb);
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extern int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb);
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extern void amd_iommu_domain_direct_map(struct iommu_domain *dom);
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extern int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids);
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#ifndef CONFIG_AMD_IOMMU_STATS
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@ -93,6 +93,11 @@
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#define FEATURE_PASID_SHIFT 32
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#define FEATURE_PASID_MASK (0x1fULL << FEATURE_PASID_SHIFT)
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#define FEATURE_GLXVAL_SHIFT 14
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#define FEATURE_GLXVAL_MASK (0x03ULL << FEATURE_GLXVAL_SHIFT)
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#define PASID_MASK 0x000fffff
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/* MMIO status bits */
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#define MMIO_STATUS_COM_WAIT_INT_MASK (1 << 2)
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#define MMIO_STATUS_PPR_INT_MASK (1 << 6)
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@ -257,6 +262,22 @@
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#define IOMMU_PTE_IW (1ULL << 62)
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#define DTE_FLAG_IOTLB (0x01UL << 32)
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#define DTE_FLAG_GV (0x01ULL << 55)
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#define DTE_GLX_SHIFT (56)
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#define DTE_GLX_MASK (3)
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#define DTE_GCR3_VAL_A(x) (((x) >> 12) & 0x00007ULL)
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#define DTE_GCR3_VAL_B(x) (((x) >> 15) & 0x0ffffULL)
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#define DTE_GCR3_VAL_C(x) (((x) >> 31) & 0xfffffULL)
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#define DTE_GCR3_INDEX_A 0
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#define DTE_GCR3_INDEX_B 1
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#define DTE_GCR3_INDEX_C 1
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#define DTE_GCR3_SHIFT_A 58
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#define DTE_GCR3_SHIFT_B 16
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#define DTE_GCR3_SHIFT_C 43
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#define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
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#define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
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@ -283,6 +304,7 @@
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domain for an IOMMU */
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#define PD_PASSTHROUGH_MASK (1UL << 2) /* domain has no page
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translation */
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#define PD_IOMMUV2_MASK (1UL << 3) /* domain has gcr3 table */
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extern bool amd_iommu_dump;
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#define DUMP_printk(format, arg...) \
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@ -344,6 +366,8 @@ struct protection_domain {
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u16 id; /* the domain id written to the device table */
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int mode; /* paging mode (0-6 levels) */
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u64 *pt_root; /* page table root pointer */
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int glx; /* Number of levels for GCR3 table */
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u64 *gcr3_tbl; /* Guest CR3 table */
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unsigned long flags; /* flags to find out type of domain */
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bool updated; /* complete domain flush required */
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unsigned dev_cnt; /* devices assigned to this domain */
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@ -611,6 +635,9 @@ extern bool amd_iommu_v2_present;
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extern bool amd_iommu_force_isolation;
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/* Max levels of glxval supported */
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extern int amd_iommu_max_glx_val;
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/* takes bus and device/function and returns the device id
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* FIXME: should that be in generic PCI code? */
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static inline u16 calc_devid(u8 bus, u8 devfn)
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