forked from luck/tmp_suning_uos_patched
powerpc: Board support for GE Fanuc SBC610
Support for the SBC610 VPX Single Board Computer from GE Fanuc (PowerPC MPC8641D). This is the basic board support for GE Fanuc's SBC610, a 6U single board computer, based on Freescale's MPC8641D. Signed-off-by: Martyn Welch <martyn.welch@gefanuc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Martyn Welch
Kumar Gala
parent
66576a87dd
commit
54508214cf
260
arch/powerpc/boot/dts/gef_sbc610.dts
Normal file
260
arch/powerpc/boot/dts/gef_sbc610.dts
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@ -0,0 +1,260 @@
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/*
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* GE Fanuc SBC610 Device Tree Source
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*
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* Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* Based on: SBS CM6 Device Tree Source
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* Copyright 2007 SBS Technologies GmbH & Co. KG
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* And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
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* Copyright 2006 Freescale Semiconductor Inc.
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*/
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/*
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* Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
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*/
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/dts-v1/;
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/ {
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model = "GEF_SBC610";
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compatible = "gef,sbc610";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8641@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <32768>; // L1, 32K
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i-cache-size = <32768>; // L1, 32K
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timebase-frequency = <0>; // From uboot
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bus-frequency = <0>; // From uboot
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clock-frequency = <0>; // From uboot
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};
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PowerPC,8641@1 {
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device_type = "cpu";
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reg = <1>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <32768>; // L1, 32K
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i-cache-size = <32768>; // L1, 32K
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timebase-frequency = <0>; // From uboot
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bus-frequency = <0>; // From uboot
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clock-frequency = <0>; // From uboot
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};
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x40000000>; // set by uboot
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};
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soc@fef00000 {
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#address-cells = <1>;
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#size-cells = <1>;
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#interrupt-cells = <2>;
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device_type = "soc";
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compatible = "simple-bus";
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ranges = <0x0 0xfef00000 0x00100000>;
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reg = <0xfef00000 0x100000>; // CCSRBAR 1M
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bus-frequency = <0>;
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i2c1: i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <0x2b 0x2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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eti@6b {
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compatible = "dallas,ds1682";
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reg = <0x6b>;
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};
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};
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i2c2: i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl-i2c";
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reg = <0x3100 0x100>;
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interrupts = <0x2b 0x2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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dma@21300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
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reg = <0x21300 0x4>;
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ranges = <0x0 0x21100 0x200>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8641-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <20 2>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8641-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <21 2>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8641-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <22 2>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8641-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <23 2>;
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};
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};
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mdio@24520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <0x24520 0x20>;
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phy0: ethernet-phy@0 {
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interrupt-parent = <&mpic>;
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interrupts = <0x0 0x1>;
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reg = <1>;
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};
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phy2: ethernet-phy@2 {
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interrupt-parent = <&mpic>;
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interrupts = <0x0 0x1>;
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reg = <3>;
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};
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};
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enet0: ethernet@24000 {
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy0>;
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phy-connection-type = "gmii";
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};
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enet1: ethernet@26000 {
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x26000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy2>;
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phy-connection-type = "gmii";
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <0>;
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interrupts = <0x2a 0x2>;
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interrupt-parent = <&mpic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4600 0x100>;
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clock-frequency = <0>;
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interrupts = <0x1c 0x2>;
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interrupt-parent = <&mpic>;
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};
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mpic: pic@40000 {
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clock-frequency = <0>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x40000 0x40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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};
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global-utilities@e0000 {
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compatible = "fsl,mpc8641-guts";
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reg = <0xe0000 0x1000>;
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fsl,has-rstcr;
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};
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};
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pci0: pcie@fef08000 {
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compatible = "fsl,mpc8641-pcie";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xfef08000 0x1000>;
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bus-range = <0x0 0xff>;
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ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
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0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
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clock-frequency = <33333333>;
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interrupt-parent = <&mpic>;
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interrupts = <0x18 0x2>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
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0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
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0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
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0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
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>;
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pcie@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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ranges = <0x02000000 0x0 0x80000000
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0x02000000 0x0 0x80000000
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0x0 0x40000000
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0x01000000 0x0 0x00000000
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0x01000000 0x0 0x00000000
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0x0 0x00400000>;
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};
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};
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};
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@ -31,6 +31,13 @@ config MPC8610_HPCD
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help
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This option enables support for the MPC8610 HPCD board.
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config GEF_SBC610
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bool "GE Fanuc SBC610"
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select DEFAULT_UIMAGE
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select HAS_RAPIDIO
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help
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This option enables support for GE Fanuc's SBC610.
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endif
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config MPC8641
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@ -39,7 +46,7 @@ config MPC8641
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select FSL_PCI if PCI
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select PPC_UDBG_16550
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select MPIC
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default y if MPC8641_HPCN || SBC8641D
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default y if MPC8641_HPCN || SBC8641D || GEF_SBC610
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config MPC8610
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bool
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@ -7,3 +7,4 @@ obj-$(CONFIG_SMP) += mpc86xx_smp.o
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obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o
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obj-$(CONFIG_SBC8641D) += sbc8641d.o
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obj-$(CONFIG_MPC8610_HPCD) += mpc8610_hpcd.o
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obj-$(CONFIG_GEF_SBC610) += gef_sbc610.o
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149
arch/powerpc/platforms/86xx/gef_sbc610.c
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149
arch/powerpc/platforms/86xx/gef_sbc610.c
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@ -0,0 +1,149 @@
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/*
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* GE Fanuc SBC610 board support
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*
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* Author: Martyn Welch <martyn.welch@gefanuc.com>
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*
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* Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* Based on: mpc86xx_hpcn.c (MPC86xx HPCN board specific routines)
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* Copyright 2006 Freescale Semiconductor Inc.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/of_platform.h>
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#include <asm/system.h>
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#include <asm/time.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <asm/mpc86xx.h>
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#include <asm/prom.h>
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#include <mm/mmu_decl.h>
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#include <asm/udbg.h>
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#include <asm/mpic.h>
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#include <sysdev/fsl_pci.h>
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#include <sysdev/fsl_soc.h>
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#include "mpc86xx.h"
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#undef DEBUG
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#ifdef DEBUG
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#define DBG (fmt...) do { printk(KERN_ERR "SBC610: " fmt); } while (0)
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#else
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#define DBG (fmt...) do { } while (0)
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#endif
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static void __init gef_sbc610_setup_arch(void)
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{
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#ifdef CONFIG_PCI
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struct device_node *np;
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for_each_compatible_node(np, "pci", "fsl,mpc8641-pcie") {
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fsl_add_bridge(np, 1);
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}
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#endif
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printk(KERN_INFO "GE Fanuc Intelligent Platforms SBC610 6U VPX SBC\n");
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#ifdef CONFIG_SMP
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mpc86xx_smp_init();
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#endif
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}
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static void gef_sbc610_show_cpuinfo(struct seq_file *m)
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{
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struct device_node *root;
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uint memsize = total_memory;
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const char *model = "";
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uint svid = mfspr(SPRN_SVR);
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seq_printf(m, "Vendor\t\t: GE Fanuc Intelligent Platforms\n");
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root = of_find_node_by_path("/");
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if (root)
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model = of_get_property(root, "model", NULL);
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seq_printf(m, "Machine\t\t: %s\n", model);
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of_node_put(root);
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seq_printf(m, "SVR\t\t: 0x%x\n", svid);
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seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
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}
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/*
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* Called very early, device-tree isn't unflattened
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*
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* This function is called to determine whether the BSP is compatible with the
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* supplied device-tree, which is assumed to be the correct one for the actual
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* board. It is expected thati, in the future, a kernel may support multiple
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* boards.
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*/
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static int __init gef_sbc610_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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if (of_flat_dt_is_compatible(root, "gef,sbc610"))
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return 1;
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return 0;
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}
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static long __init mpc86xx_time_init(void)
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{
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unsigned int temp;
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/* Set the time base to zero */
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mtspr(SPRN_TBWL, 0);
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mtspr(SPRN_TBWU, 0);
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temp = mfspr(SPRN_HID0);
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temp |= HID0_TBEN;
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mtspr(SPRN_HID0, temp);
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asm volatile("isync");
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return 0;
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}
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static __initdata struct of_device_id of_bus_ids[] = {
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{ .compatible = "simple-bus", },
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{},
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};
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static int __init declare_of_platform_devices(void)
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{
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printk(KERN_DEBUG "Probe platform devices\n");
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of_platform_bus_probe(NULL, of_bus_ids, NULL);
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return 0;
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}
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machine_device_initcall(gef_sbc610, declare_of_platform_devices);
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define_machine(gef_sbc610) {
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.name = "GE Fanuc SBC610",
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.probe = gef_sbc610_probe,
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.setup_arch = gef_sbc610_setup_arch,
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.init_IRQ = mpc86xx_init_irq,
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.show_cpuinfo = gef_sbc610_show_cpuinfo,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.time_init = mpc86xx_time_init,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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#endif
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};
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